#risc-v

1 messages · Page 1 of 1 (latest)

minor lynx
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recommendations for any open source riscv cores?

ionic ermine
tired tide
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ooh that's neat

worthy shuttle
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The Pine64 Ox64 is a RISC-V Linux-capable SBC for $8
Features BL808 from Bouffalo labs RISC-V SoC with 64MB RAM
3 cores: 64-bit RISC-V core, 32-bit RISC-V core and low power RISC-V core
Two variants of Ox64 on day one: for RTOS and Linux development – $6 and $8 respectively
Expected availability in November

worthy shuttle
minor lynx
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so I came across this riscv core with something called an "instruction uncache"

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would that be just a way to take instructions from the instruction cache? like a fetch helper?

burnt glen
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Anyone tried the CH32V003?
It seems like it is a bit of STM8 competitor and other cheap micro-controllers.
It does not have much flash and very little ram
You can buy them for pretty cheap, only the shipping costs are relatively high
https://nl.aliexpress.com/item/1005005036714708.html

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but yeah they are roughly 10 cent each without shipping

sinful heron
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A few people here have them

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Or that might have been the cortex-m0 chip with the similar designation.

green flare
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Of course if you look away there's always another chip/module
https://twitter.com/SipeedIO/status/1608366512083193857

Sipeed (@SipeedIO)

New Tiny #tinyML #AIoT module M0S coming out~
Based on BL616, WiFi6+BT5.2+Zigbee, 384MHz #RISCV RV32GCP, 4MB Flash + 512KB SRAM, and USB2.0 HS in tiny 10x11mm stamp module!
It would be <2$ ~

Likes

1108

Retweets

203

Twitter ·
analog elbow
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So since riscV has <50 instructions, is it "easier" to write assembly for it?

feral dock
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I haven't done either, but my impression is that it'd be roughly on par with ARM assembly. Easier than x86, harder than old-school 8-bit micros. But generally if you know one assembly language, you're already over the major hurdle to learning another one.

green solstice
coarse relic
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I think the original PIC12 assembly had like 33 instructions. On the one hand, it didn't take long to learn them, on the other hand, it was a pretty limited set of operations. If you were doing things it was good at (like bit manipulations), it was fine. If you were doing things it wasn't good at (like division), it was a royal pain. ARM assembly is wonderfully clear and orthogonal, the register rich architecture is appealing, and you learn to appreciate the usefulness of things like the "set flags" bit, which lets 1 instruction do the work of three (for example, "subtract" can act as "subtract", "subtract without disturbing the flags", and "compare").

prime steeple
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anyone have experience writing std / IDF rust for risc-v ESP boards who could point me towards which product I should get from adafruit? There's....a lot of options. I think I narrowed down to ESP32-C3, but really I want whatever has the easiest 'out-of-the-box' support

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price is least concern at the scale i want to experiment with

coarse relic
hazy ginkgo
# coarse relic I think the original PIC12 assembly had like 33 instructions. On the one hand, ...

This board was just mentioned on the bird place as being used in a documented-on-github embedded rust course: https://twitter.com/timClicks/status/1661229468927795201
Docs and examples here, YMMV: https://github.com/esp-rs/espressif-trainings
It looks to be $21 at mouser in single quantities.
Some specs (RAM, peripherals here: https://www.mouser.com/new/espressif/espressif-esp32-c3-devkit-rust-1-board/

hazy ginkgo
# coarse relic I think the original PIC12 assembly had like 33 instructions. On the one hand, ...

Microchip was never (OK, hardly ever; they did do a MIPS-based line) about architectural elegance or efficiency. But they'd sell to you in small quantities with a credit card, no questions asked -- at a time when most microcontroller silicon manufacturers wouldn't return calls or emails. They did innovate on the how-low-can-you-go axis -- and surprised me how low and how handy their PIC12xx line became!

coarse relic
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I was a devotee to the PIC12 line for a while. Powerful little chips for a buck apiece. Sure they were OTP, there was no compiler, and the instruction set and resources were sparse, but they were dandy for a variety of projects. However, Microchip chose to make the programming algorithms proprietary, and the support software DOS-only. Eventually all of these factors became too much for me, so I gave away all my PIC chips, programmer, UV erasable ones, etc. to a friend's daughter to learn on and jumped ship to AVR.

hazy ginkgo
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AVRs were much easier on my brain. (Of course, now they're under the same company, if memory serves.)

coarse relic
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Yeah, they are. Atmel was fabless and farmed out their production, and eventually Microchip swallowed them up. I liked the C-friendly, register rich AVR instruction set, the well-documented programming and protocols, and the (then) very cost-effective STK-500 programmer which supported a wide range of chips, ISP, chip recovery, HV programming, etc., and included switches and LEDs to use as a test/development board to boot. And its protocol was also well documented.

slender kernel
hazy ginkgo
coarse relic
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At the time, the PIC line was still OTP, while the AVRs were flash based, you could reprogram them over and over without buying an über-expensive windowed version and waiting 15 minutes to erase it with UV light.

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Then Arduino came along with the self-programming bootloader concept, and changed the microcontroller landscape practically overnight, including a nice (for the time) IDE that ran on several major platforms, and built-in USB-serial converters, removing all three of the major hurdles to getting started on microcontrollers.

hazy ginkgo
coarse relic
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That was, it turns out, not intentional, but became the unfortunate de facto standard after the first boards shipped.

slender kernel
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That's another board that would have really benefitted from better power design, although it doesn't have issues as glaring as the RPi.

hazy ginkgo
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Q: which of the many risc-v profiles are most of the 32-bit offerings coalescing around, or is that still unsettled?

slender kernel
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My understanding is that there haven't been many fully compliant implementations yet, i.e. the cheap ones are almost RISC-V but have issues.

hazy ginkgo
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Then please let me rephrase my question: Which risc-v extensions do most of them almost implement? --Or are we in for another fun fest like the ARM-7 and its many variants?
{Narrator voice: All those !@#$ variants didn't exactly make it fun!}
https://en.wikipedia.org/wiki/ARM7

Did I say something wrong? (I didn't want to be an inadvertent thread ender)

snow yacht
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Happy beaglev day

potent echo
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I am an individual member of riscv.org, and as such, I have built something called a RISCV-lab here in Costa Rica. Currently there are two, so this should take the count up to 3 in the whole world.
What is a riscv-lab? It's a collection of riscv64 hardware that is made available for the community to use for compiling, testing, etc, so if you don't have riscv64 hardware and you only want to make your software available for this new arch, you can contact me here, let me know, and I'll set up a dedicated hardware that you can use with things like github runners so that you can run a github action on this riscv64 hardware instead of github's (which they don't have any rv64 hw).

And one very cool thing, is that I have purchased a Milkv pioneer (crowd-supply) so by ~January I'll add to the lab a 64-core riscv64 box with 128G of ram (and I we all cross our fingers properly, I might get a second one) so there is plenty of room for all of us to run a kernel compile -j in an infite loop <3.

potent echo
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Oh yeah, the logo for the Costa Rica Risc-v lab, has been created by chatgpt :p
Since the lab is inside a dry forest, I asked it to make me a chip out of sticks, with a V in the center of the chip.

ember glacier
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fede2 the bing have image createor for that tooo just to compare

potent echo
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Yes, it uses the same openai stuff. We at microsoft are heavy partners with openai.

spark solar
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This may fit better in one of the help channels but, does anyone know how to use this board?

20230810_113217.jpg
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Its a sipeed m0 sense risc-v development board, its based on the bl702 mcu

potent echo
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At the bottom they show how to compile the code, so you can start by modifying one of the examples you like and then start adding your code to it.

spark solar
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It doesnt work

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Some files seem to be missing, and either the guide or the git repo is outdated

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I should have just bought another esp32

ScRR6m.jpg
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Also, the wireless functionality (ble5 and zigbee) seem to be locked behind an nda agreement, but im not sure

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And the very little documentation there is, is in chinese

potent echo
spark solar
spark solar
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the guide says to run this "build.sh" file

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this is build.sh if you want to check it out. a l s o i had to replace all "==" with "=" for it to work, im not sure why really

📎 build.sh
spark solar
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trying to buid the examples gives this error:

image.png
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the github issues page is not very helpful

image.png
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this seems to be a common thing for sipeed and BouffaloLabs, almost no support and very little documentation

SPOILER_image.png
potent echo
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I haven't tried the code yet, but it seems that the fixes you added make sense but might not be enough. I am from Costa Rica and I have a bit of trouble getting hardware from Sipeed (I do have a couple of Lichee Pi4). But as soon as I can get a bit of free time, I'll try to see how far can I take it, and maybe try get one of those boards.

spark solar
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Thank you!

spark solar
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i had an idea, if you are are able to compile code and want to test it, you should send the .uf2 file here so i can try it on my board @potent echo

tribal bolt
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This guy made his own computer inside a game . He could do a lot for the adafruit community. https://youtu.be/zXPiqk0-zDY?si=dkzFxkh3irWE4IfM

YouTube
From Scratch
I Made a 32-bit Computer Inside Terraria

I document my journey implementing Computerraria: a 32 bit CPU running inside the game Terraria. I've been working on this for over 6 months now and thought it's cool enough that other's might be interested in learning about it. Absolutely everything I talk about here is completely open source and freely available in these public repositories:

...

▶ Play video
restive ice
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That’s pretty insane

spark solar
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Let him cook

spark solar
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Someone got linux runing on scratch

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Using a risc-v emulator on scratch

potent echo
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Very cool, upcomming cpu+board. For $120, 12+4 riscv64 cores, plus 8 npus, up to 64 G of ram, all of the regular stuff you can find on a PC,
https://community.milkv.io/t/introducing-the-milk-v-oasis-with-sg2380-a-revolutionary-risc-v-desktop-experience/780

MilkV Community
Introducing the Milk-V Oasis with SG2380: A Revolutionary RISC-V De...

We are excited to unveil, in collaboration with Sophgo, the Milk-V Oasis—powered by the SG2380. This innovation marks the debut of a truly desktop-grade RISC-V PC in the convenient mini ITX form factor. What Makes SG2380 Stand Out? Integrated AI: The SG2380 is the sole RISC-V chip boasting integrated AI capabilities. Superior Performance: Cou...

spark solar
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I should have just bought the seeed xiao ble sense instead of the m0sense

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Same size, same sensors, better docs, working BLE, low power consumption, more flash memory, HAS AN ARDUINO CORE

spark solar
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Also shoutout to the ESP32C3

soft citrus
static summit
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I want a Milk-V Mars for my DevTerm. Alas they are not available that I can find.

tired pasture
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I fully understand that it's not an overnight process bringing up a new board, but with the ESP32-C3 starting to really take off, are there any plans to produce a Feather version?
P.S. "We are not allowed to talk about this yet" is an acceptable answer, I'm very well aware of the issues of both hardware and software development.

loud veldt
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I don't know why that is out of stock at the moment.

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Is there something about the C3 that is more interesting to you that another Espressif chip?

tired pasture
# loud veldt The C3 chip has very few I/O pins. We made a QT Py version which exposed what lo...

I've posted on the forums asking about this, but a project I'm thinking about will use a Music Maker Featherwing. According to the learn page for that device, the ESP32 family of chips can't do interrupt driven playback.
I'm hoping against hope that maybe the lowly ESP8266 can do interrupt based playback, but if not, the C3 looks like the next obvious choice. WiFi is needed on this, which is why Espressif chips are the obvious choice for this project.
That and the fact that I'd like to see just what I can do with Risc-V. It's an absolutely brilliant idea, a completely free open source hardware chip design. It's not part of my skillset, but I am aware that the licensing of chip cores is fairly big business. To my understanding, that's the core (pun intended) of both ARM and MIPS business models.

loud veldt
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The C3 doesn't have full native USB, so it won't be as easy to use as an S2 or S3

tired pasture
# loud veldt The problem with the Music Maker FeatherWing is generic across essentially all b...

Ahh. At the risk of going off topic, then I should assume I can't use interrupt driven playback no matter what CPU I use.
Presumably as long as I "poll" the board often enough to allow it to keep the buffers on the VS1053 full enough for continuous playback, it'll work correctly. That will probably mean a bit of a rewrite of some other code in the project, but nothing a competent software engineer can't handle.
In that case I have a couple of options open to me, I'll most likely wind up using a spare ESP32-S2 I have here.
Back to the C3, from my point of view the lack of native USB is a complete non-issue. I have no trouble at all programming an ESP8266 Feather via USB serial upload, and presumably the C3 works in much the same way. Lack of native USB only becomes a problem with the CircuitPython workflow, which I'm not using.

loud veldt
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The C3 is kind of an ESP8266 replacement, mean to be very low cost. The ESP8266 was originally designed for WiFi-controllable lightbulbs, I believe.

tired pasture
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Indeed. The Tasmota project is a testament to that. But it's absolutely perfect for other small IoT projects, which is part of the reason I'm so interested in the C3. It's got all the checkboxes I care about - reasonable performance, low cost, WiFi capable. A great IoT platform.

loud veldt
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If you can get the Music Maker working, that would be great. Good luck!

tired pasture
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Watch #show-and-tell for details. 🙂 It'll be a while because the Music Maker is currently out of stock, but I've got notifications turned on for it. No rush, I know you guys at AdaFruit are putting 110% into making the products you do, so I fully understand. Thanks for all the info on the C3, definitely all useful to know.

green solstice
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but the USB support, is only for serial interface, isn't it? ie: same as CircuitPy

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im clueless about how USB works, but imma guess you can make it show as an external storage.... by writing a fair amount of code to "virtualize" whatever the fully-fledged USB controller on the S2/S3 implements on hardware
... or maybe you can't even do that due to some hardware limitation 😅

loud veldt
green solstice
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makes complete sense, i didn't mean it as in "you could/should do it" but just as in "it is not completely impossible"

gentle forge
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there were a few popular bit-banged low-speed USB libraries, but full-speed is much harder (though possibly within reach for modern ARM MCUs)

potent echo
# tired pasture I fully understand that it's not an overnight process bringing up a new board, b...

Sparkfun has a C6 dev board.
And this, of course will take quite a while to get stable enough to be interesting, but look at this beauty announced yesterday.
https://www.cnx-software.com/2024/01/10/esp32-c61-wifi-6-soc-improved-affordability-wireless-connectivity/

CNX Software - Embedded Systems News
Espressif announces the ESP32-C61 WiFi 6 SoC with improved affordab...

Espressif has announced the ESP32-C61 SoC, a new ESP32-Cx chip with improved wireless connectivity, and expanded memory options. The ESP32-C61 builds upon

potent echo
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If you want something a bit more powerful, close to raspberry pi4 size and almost pin compatible (sorry, I'm not that familiar with the DevTerm, even if I have seen pictures of them), I'd recommend the licheepi4 which for a couple of things is faster than a pi4.
And if you can wait, in Q3 they are releasing the milkv Oasis, which is way larger than a Pi, but it's a 12+4 cores (plus lots and lots of goodies)

potent echo
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I was going to do a purchase in digikey. It goes all the way to Costa Rica so it better be a nice purchase, so I got me some C6 and H2 esp-dev boards, let's see what we can do with them.

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In other news, my 64-core, 128G ram milkv pioneer is in Miami waiting to be shipped, so it could arrive here by this week or maybe the next one.
This one is going to be used to make it available as part of the hardware in my RISC-V Lab* for Costa Rica, so if anyone needs any hardware to test software or to compile stuff, I'll be making it available as Github runners (and when I can, as an Azure DevOps 'runner'), so please write me a note if you need some.
The road from 1 core, to 2, 4 and then straight up to 64 has been very fast, so I can only imagine what we will see during 2024. (8 cores and 12+4 have already been announced and should be in real hardware in the next weeks).

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  • The official afiliation as a risc-v lab is pending. I need to make one of the other risc-v boards a monitoring system, so I'll get to it one of these days... But the working status of the lab has been functional for about a year.
potent echo
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Not only do I have the monitoring system installed (zabbix), I've just ported a c-python library to circuitpython so now I have an esp32-c3 doing API request with this library, and turning pixels green of the host is alive and without load, blue if alive and with load, and red if down.

So, riscv, monitoring riscv. (zabbix is also running on riscv)

coarse relic
slender kernel
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SPARC has register windowing doesn't it?

loud veldt
# slender kernel SPARC has register windowing doesn't it?

yes. I was in the original Berkeley RISC-I grad seminar and co-invented register windows. SPARC then picked it up. Maybe too much overhead for process context switching in the long run, but it really helped on speed. Nowadays better done by a compiler.

restive ice
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How cool to have your name on something like that 😎

loud veldt
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not sure it makes me famous. Also I am the original author of the Unix more command.

restive ice
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I thought you were really cool before, but now you are so much cooler!

loud veldt
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There is a picture of Peter Kessler and me standing next to a partially open sliding window in a Berkeley office, pointing at the overlap.

dusty kelp
loud veldt
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your writing microcode for Amdahl machines is no slouch either 😉

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CS was a lot smaller in those days, easier to be well-connected

spark solar
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Oh my god

-20209220081205917656.jpg
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What uf its another documentation catastrophe like the M0 sense

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(Months later I still have no clue how to use it and i believe BLE is still locked behind an NDA)

rocky kestrel
soft citrus
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With psram this could possibly mean espcam

restive ice
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Looks like we’re getting an update to the CH32V003

image0.jpg
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This will reportedly also be $0.10

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Or it appears that way anyway

rocky herald
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It say 006 on the picture. Is this a bigger brother?

restive ice
rocky herald
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Nice - and they have a "middle" brother v005 too ❤️

spark solar
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im glad more people have talked about the milkV

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sounds like a very interesting project, and i may get one next month

spark solar
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blinka for milkv when

ember glacier
potent echo
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I think I'll just try to tackled head on what the python folks call "manylinux" which is what they use to build the whl packages for compatibility in multiple distros. So far there isn't anything for riscv, and is needed as right now is so slow to install python stuff with dependencies.

thorny bluff
tired pasture
sweet elk
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Is anyone here planning to use the nRF54 series for the risc-v coprocessor?

warm spear
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Waiting for nRF54L20 that is reported to also have USB support.

fossil tree
young tusk
fossil tree
young tusk
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I'm not sure what M instructions are

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my interest would be running circuitpython on it 🙂

fossil tree
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Oh, I fear that requires a degree of support of the RISC-V architecture that is out of scope for this little emulator 🥰

fossil tree
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on a second thought, it turns out this little RISC-V emulator written in pure Python can run... RISC-V MicroPython 🙂

Screenshot_2025-04-09_at_00.49.41.png
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CircuitPython, I fear, might be more challenging.

young tusk
fossil tree
young tusk
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Yes, the compiler will bring in software implementations

fossil tree
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I’ll give it a shot with just RV32I instructions; then !

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I was under the impression that it asks much more of the CPU (and rightfully 🙂 )

fossil tree
young tusk
fossil tree
young tusk
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renode has one basic "peripheral" for uart I think

fossil tree
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Thanks, I’ll try to see if I we can do away with that too 🙂

fossil tree
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It now passes RISC-V compliance tests for machine mode, and runs FreeRTOS. Porting CircuitPython should be easy at this point. maybe with passthrough file system access to the host, and an emulated memory mapped serial device.

midnight comet
fossil tree
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Took a while but I got it working. I have a RISC-V CircuitPython executable that runs on the emulator, and a working REPL over emulated memory-mapped UART.

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There are still a few glitches due to my limited understanding of how CircuitPython ports work. I might ask a few questions here.

young tusk
fossil tree
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One question I have is what is the proper way to handle keyboard interrupt. The UARX rx pipeline processes it and marks the exception as pending. This works initially, but the REPL appears to set the interrupt char to -1 (disabling it) after processing any input.

fossil tree
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Tight Python loops in particular are not interruptible in my port right now.

young tusk
fossil tree
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I do the same. I think. I’ll share a snippet.

fossil tree
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mh, maybe let's take a step back. Where can I find documentation on the correct way to implement a serial console over my own (memory-mapped, polling, no hardware pins) UART implementation? I"ve added "-DCIRCUITPY_CONSOLE_UART_RX -DCIRCUITPY_CONSOLE_UART_TX" to the CFLAGS, which causes py/circuitpy_mpconfig.h to set CIRCUITPY_CONSOLE_UART=1 (which apparently can't be done directly in mphalport.h). Then supervisor/shared/serial.c provides "busio_uart_obj_t console_uart" and serial_early_init() calls my common_hal_busio_uart_construct() in common-hal/busio/UART.c . At that point everything gets routed through my common_hal_busio_uart_write() , common_hal_busio_uart_read(), common_hal_busio_uart_rx_characters_available(). Except I have to provide separately a board_serial_write_substring() in boards/MY_PORT/board.c that routes through common_hal_busio_uart_write(). At this point the REPL over UART works.

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is this the correct way to do it, or I have made a spaghetti mess? 🙂

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once the REPL works, however, if I enter a tight loop like "while True: pass" I can see the timer tick firing and the cascade of calls leading to background_callback_run_all() being called, but of course nothing is polling the UART so I can't intercept CTRL+C and the loop is un-interruptible. Since I can't seem to override RUN_BACKGROUND_TASKS, I guess the correct way to trigger UART RX polling is to add a background callback? That way my UART RX code has got a chance to detect CTRL+C and call mp_sched_keyboard_interrupt(). And then I guess the background task also has to call mp_handle_pending() or is this already done by default?

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hope this is clear. Thanks so much for any insights on this, the architecture is quite complex and there are so many possible overrides and switches...

loud veldt
fossil tree
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thanks! I'll look into that. Do you think the above approach to keyboard interrupt is correct?

loud veldt
fossil tree
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Ahah fair enough. Thanks !

fossil tree
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Finally I have a fully working CircuitPython RISC-V port that runs on my RISC-V emulator (https://github.com/ccattuto/riscv-python/). With an emulated UART backed by a pseudoterminal on the host, emulated block device backed by a filesystem image on the host, timer and tick support, CTRL+C support for tight Python loops, etc.
https://github.com/ccattuto/riscv-python/tree/main/advanced/circuitpython
The port is here, in case anybody is curious: https://github.com/ccattuto/riscv-python/tree/main/advanced/circuitpython/riscv-emu.py

GitHub
riscv-python/advanced/circuitpython at main · ccattuto/riscv-python

RISC-V Emulator in pure Python (RV32I, machine mode, Newlib support, memory-mapped IO) - ccattuto/riscv-python

GitHub
riscv-python/advanced/circuitpython/riscv-emu.py at main · ccattut...

RISC-V Emulator in pure Python (RV32I, machine mode, Newlib support, memory-mapped IO) - ccattuto/riscv-python

fossil tree
fossil tree
quaint skiff
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Hello, noob who wants to start tinkering with Linux on RISC-V here. Is this a good place to ask questions about RISC-V hardware?

loud veldt
twilit estuary
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Talk by Daniel Schultz about Fully Open Source Chip Development with RISC-V: https://youtu.be/NiTtvaCTPZs?si=40QPP-DL0OYcEQBA

YouTube
SemiTO-V RISC-V Student Team
World RISC-V Days Turin 2026: Daniel Schultz - Fully Open Source Ch...

Daniel Schultz demonstrates that it is now possible to create fully open-source chips, from core
design to silicon fabrication. By leveraging open-source RTL and EDA tools, Schultz's work
culminates in projects like ElemRV, an end-to-end open-source microcontroller built around a
RISC-V core. His talk will showcase how the openness of the RISC-V...

▶ Play video
dawn finch
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Cool but expensive. There’s 31400 mm^2 on a 200mm wafer, which means that one wafer at 1500€/mm^2 costs 47 Million euros. That’s about 100x what I would expect. The lithography photomasks should only cost 60k€, and the actual production cost should be under 100k€ (especially for an old process node)

grave prairie
# dawn finch Cool but *expensive*. There’s 31400 mm^2 on a 200mm wafer, which means that one ...

The 1500€/mm² gets you 40 chips, and is the maximum price that can occur if it barely crosses the fab threshold of a total of 90mm² of orders (so 3600mm² worth of wafer), the price drops as low as 900€/mm² as the rest of the wafer fills up.

At a full wafer it would only be 706,500€ which is ~150% of ordering a full wafer yourself which is much more reasonable markup for a "We take care of all the layout/sorting/binning/etc." surcharge IMHO.

The URL mentioned on the slide https://dk.ihp-microelectronics.com/OpenSourceRequest.php details the pricing and such a lot better, yeah.

dawn finch
young tusk
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Thanks! Deleted

shadow vector
normal kestrel
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yeah risc is good

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I'm trying to get my hands on a k210 maixduino

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for some more rust action

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I should probably focus on atsamd but I like the new shinies XD

shadow vector
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oh @normal kestrel have a couple k210s here

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will post about'em soon and/or have on a video

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looks like all of them use the same demo

normal kestrel
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kool

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are you able to sell k210 boards?

shadow vector
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@normal kestrel workin on it!

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most likely the risc-v based m5 stick

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which is a k210

normal kestrel
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cool, wasn't sure how the ip was licensed/distributed for that particular chip

shadow vector
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digging in to how all it works now as we're interested in one that works with usb and has lots o ram

normal kestrel
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mhm

#

maixduino looks beginner friendly but idk the distribution situation

#

I've only seen it on taobao and seeed

#

it's a sipeed board if you're interested

#

has micropython and arduino as the name suggests

#

I think it's ftdi or something though for usb

#

ch552

#

I imagine usb is fairly difficult to implement in fpga/asic from what I know about how difficult it is to make a hal for

#

is there a tinyusb equiv for verilog?

vernal sun
#

there is, check out valenty

acoustic oar
#

RISC isn't Risky anymore...

shadow vector
#

https://github.com/andrescv/Jupiter
https://riscvsim.com/

V-Sim is a simple assembler and runtime simulator inspired by SPIM for programming in RISC-Vassembly language and intended for educational purposes. One of the main goals was to make it functional and easy to use. Almost all the 32-bit base integer instruction set (RV32I) can be simulated, as well as the M and F extensions plus all the their respective pseudo-instructions.

GitHub
andrescv/Jupiter

RISC-V Assembler and Runtime Simulator. Contribute to andrescv/Jupiter development by creating an account on GitHub.

V-Sim Documentation

RISC-V Assembler and Runtime Simulator

burnt glen
#

Don't know if it actually legal but here is a link

#

@normal kestrel I have a maixduino, the usb driver can be a bit buggy on windows

#

For example it only shows up one com port instead of the two

normal kestrel
#

Ok

burnt glen
#

Also used an arduino sketch that just doesn't work for some reason

normal kestrel
#

I'm not planning to do much arduino coding with it

burnt glen
#

You want to use that insane amount of SRAM?

normal kestrel
#

I want to code in rust

half zodiac
#

Which chipset and firmware are we considering using? I'm assuming the gcc/gdb toolchain but we'll need firmware/bootloader to put a CircuitPython interpreter on it. Also is there an Adafuit location I should go to read the fine manual?

young tusk
#

I don't think we have a good chipset yet

normal kestrel
#

here's a good book on riscv instructions, https://github.com/RobertBaruch/lmarv/blob/master/lmarv-1/riscv-instructions-book/instr.pdf and of course the official manual is good too https://riscv.org/specifications/

GitHub
RobertBaruch/lmarv

Building a RISC-V processor out of LSI logic. Contribute to RobertBaruch/lmarv development by creating an account on GitHub.

RISC-V Foundation
Specifications - RISC-V Foundation

Please note, RISC-V ISA and related specifications are developed, ratified and maintained by RISC-V Foundation contributing members within the RISC-V Foundation Technical Committee. Operating details of the Technical Committee can be found in the RISC-V Foundation Workspace. ...

half zodiac
#

I have the ISA spec, which I'll read tonight. Thanks for the link to that GitHub repo.

normal kestrel
#

Yeah that github repo is actually a companion to a youtube series

burnt glen
#

I don't think there are any chips yet that satisfy the circuit python criteria, since there aren't any chips that can act as a USB mass storage adapter @half zodiac

#

It could be solved by using the BBC micro:bit method, using an extra chip that acts as a USB mass storage device that flashes the firmware to the main chip

#

But it is not very elegant

#

Are there any chips Risc V chips available besides HiFive and Kendryte ?

#

Not including the FPGAs

#

These chips are also very limited for example they don't even have an ADC

half zodiac
#

I don't have the EE skills to do a VLSI (do they still use VLSI?) layout and outsource a chip fabrication. Sidebar: back in the day ('95) I was a senior UINX administrator at Cirrus Logic, so I knew people who did have those design skills. Paying for the fab would be a completely different story.

burnt glen
#

HiFive does offer services to make your own SoC but to be honest they don't provide that many options

#

O never mind that is a upcoming feature

lofty ether
coarse relic
#

It seems to me that RISC-V is more aimed at CPU applications than microcontroller ones. It's always possible to use outboard peripherals to add functionality.

burnt glen
#

@coarse relic It currently mostly focused on microcontrollers. Just not microcontroller that have an analog input.

coarse relic
#

I didn't realize that.

burnt glen
#

I think there currently is only one chip available that isn't a microcontroller

#

1 of the 7

coarse relic
#

I'm just having trouble wrapping my head around the notion of a 64 or 128 bit "microcontroller".

normal kestrel
#

I think maybe it's targeted at cpus but microcontrollers are cheaper to make?

burnt glen
#

Only one of the microcontroller is 64bit but I don't understand that either

coarse relic
#

I suppose it makes sense to try to offer all-in-one, easy to integrate chips to get it out there and in use, it just seems odd to me for an architecture that was (I think) initially aimed at displacing ARM/PPC/X86 in the desktop/server/datacenter market.

normal kestrel
#

well it was initially for research

burnt glen
#

I thought it was mostly created to have an opensource ISA.
The problem when using ARM isa is that you can't release the source code of your chip design

coarse relic
#

It certainly has spurred a bunch of useful research and thinking, which is to the good (the entrenched architectures these days embody a bunch of design that we now know how to do better).

normal kestrel
#

it was created at berkeley so they could teach cpu design

burnt glen
#

Apparently the initial funding was from DARPA

#

The institute that develops weapons, surveillance and other defense related stuff

coarse relic
#

... and the internet

burnt glen
#

Yeah, many stuff from defense get's incorporated in every items

normal kestrel
#

Krste Asanović at the University of California, Berkeley, found many uses for an open-source computer system. In 2010, he decided to develop and publish one in a "short, three-month project over the summer". The plan was to help both academic and industrial users.[6] David Patterson at Berkeley also aided the effort. He originally identified the properties of Berkeley RISC,[11] and RISC-V is one of his long series of cooperative RISC research projects. At this stage, students inexpensively provided initial software, simulations, and CPU designs.[2]
https://en.wikipedia.org/wiki/RISC-V

RISC-V

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.
The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not...

coarse relic
#

It's amazing what a small group (or even a single person) can do. The stories behind ARM and AVR are similar.

cinder sierra
#

6502 and 65816 as well.

#

For me, it hit right around the time people were seriously talking about non-x86 in the data center again. At the time, folks were talking about how it was beating ARM at compute-per-watt. So there was at least some interest in the compute cloud at various points in time, even if folks aren't doing anything around that right now.

#

Presumably ARM has been making active efforts to market to the data center marketplace (I see them and their vendors at cloud conferences) which might be trying to prevent RISC V from getting a toehold therem

#

I mean there's also making sure that stuff builds, providing buildservers for open source projects, getting kernel support... Easier for ARM to invest instead of RISC V hoping people make a stone soup.

sour night
#

ARM is in the data center. Amazon has custom ARM instances now, cheaper than amd64

burnt glen
#

In the beginning it wasn't that hard to design a CPU

#

CPU's nowadays do all kind of crazy stuff

#

The 6502 only uses 4,528 transistors

#

Lol amd even straight up copied intels 8080 CPU by just making photographs of the die xD

#

Basically a ryzen 1600 has the same transitor count as 1 million 6502 cores

coarse relic
#

Google's running Power9 CPUs now in their data centers.

loud veldt
#

I was a grad student at Berkeley when the first Berkeley RISC grad seminar was held, in 1980. I attended that seminar and worked with another student on the overlapping register windows idea. That class was the start of the RISC I design. Register windows were present in SPARC and other RISC processors but were eventually mostly dropped because they made context switching expensive. http://web.cecs.pdx.edu/~alaa/ece587/papers/patterson_isca_1981.pdf

thin cape
#

But some of us still use them 😉

burnt glen
#

Hmm, it's funny how the meaning of 'reduced' instruction set has changed over the years

burnt glen
#

Not actually that there are less instructions

#

And that usually load/store branch if are included with an other instruction

coarse relic
#

I do like the register-rich, load/store model (which apparently goes back to the CDP1802). I like ARM's approach to flag setting: they made it depend on a bit in the instruction. Earlier processors would have "set flags but discard result" instructions like "compare" (basically subtract with no result). Now you can discard the result or discard flags, whatever you want.

burnt glen
#

Yeah but CISC basically it doesn't matter that much since not that many people write code in assembly

wanton sphinx
#

oh drat, I thought I'd read that the kendryte k210 had usb 😦

burnt glen
#

Definitely not 😦

#

It is made for surveillance and other AI devices that are designed to act autonomous @wanton sphinx

#

So USB is not important at all

normal kestrel
burnt glen
#

They are thinking about AI chips. That seems like they are experimenting with K210 or GAP8

#

Really nice that China is investing a lot of money into RISC-V to get more independent of the united states

#

The presidents policies of trade war with China will only enhance those efforts

coarse relic
#

The Xuantie 910 16-core RISC-V CPU is apparently targeting the 5G cell phone market.

#

Apparently, the maker, 平头哥 (Pingtouge, meaning "honey badger") will initially be FPGA based, and they're open-sourcing it.

#

I don't speak Chinese, but recognized the English words "fierce determination" when they were describing their mascot.

📎 screenshot_457.png
burnt glen
#

Where did you find that it targets the cellphone market? @coarse relic

coarse relic
cinder sierra
#

Honey Badger don't care.

burnt glen
#

Doesn't say something about that it is going to be used for cell phones

coarse relic
#

5G is the upcoming cell phone standard

burnt glen
#

Yeah but they also included many other features that are not really useful for smartphones

#

For example really low latencies, low power and many more connections per unit of area

#

I get that you think that it is going to be used for cellphones

coarse relic
#

It makes sense for manufacturers to target the cell phone market. If they can get their chips used there, they'll sell a lot of volume, which can let them also support more niche uses.

burnt glen
#

I wouldn't say the other markets are niche but will have to see how much Iot is going to grow

#

The use cases can be a lot of things. AI security cameras, drones, cars, remote scientific measuring devices and many other applications

burnt glen
#

There are already a lot of cars that send information over the mobile network to the manufacturer

potent echo
#

Can't wait to get my hand on one of those Xuantie with 16-cores.

#

I'd like to make a new motherboard for my old XO Laptop.

#

And would make porting slackware to riscv less slower 😃

#

BTW, there wasn't a #risc-v back then so I'll offer again.

#

We have a Hifive unleashed in case anyone needs to develop or test sutff on it.

#

It's shared with porting slackware, but if you need a debian or fedora chroot I'll set up access to it.

minor forum
#

Interesting set of videos from Gary Explains on youTube on RISC-V. Seems like it just because the ISA is open does not mean the implementation will be. 😕

coarse relic
#

Some implementers have said they'll open source theirs.

potent echo
#

At least the alibaba one is supposed to run on an FPGA.

#

It will be the first on silicon, with published sourced. But things like Hifive's are closed.

burnt glen
#

The now have the option to be it make it open source

#

What was not possible with arm

potent echo
#

And will also be cheaper because of no IP-cost, which I didn't knew is a large chunk of the price of an ARM.

#

The super scalar architecture will also make it easy to build large multi-core designs.

potent echo
#

Nice, RedHat has joined the Foundation.

coarse relic
#

Which means IBM has, I suppose

potent echo
#

Good point.

minor forum
#

In the video Gary makes a good point that even if an implementation for a chip is released and reuse is allowed in the same way open source code is, nothing is stopping them from 'adding' an extra black box when it's turned into silicon. It's harder for that to happen in software as it's easy to compile it yourself. Not so with a chip.

cinder sierra
#

There are some horrifying papers on hiding silicon backdoors.

potent echo
#

@cinder sierra Bunny huang's talk to the riscv community is also a great introduction to the topic.

past orbit
#

hah, I was just going to post that

young tusk
#

🚀

potent echo
#

I'm also trying to convince @static river to make a riscv-ai featherwing.
I need to make a demo or a circuitpython board interacting with a Maix Bit.

static river
#

I'll think about it 😃

potent echo
static river
#

hmm, i think there is already a ice40 feather made by @young tusk

#

and Greg Davill is making the Orange Crab with ECP5

young tusk
#

I made one but never tested it

#

it used the ice40up5

coarse relic
#

That looks really useful. I've been waiting for a solid powerful FPGA platform supported by open tools for a while

potent echo
#

@coarse relic I have a version I (with ICE40 chips) and it's the best out there. Great for robotics (servos). I'll also recommend Icestudio.

#

You drag and drop blocks, and is as simple as using node-red with code or something like that.

coarse relic
#

Good to know.

#

I'm more of a VHDL/Verilog sort

burnt glen
#

I think I finally understand why they made a 64-bit microcontroller, They probably are slicing the 64bit operations into 8, 8bit operations.
They could have done the same thing with 32bit processor but that design is a bit harder

#

And probably not needed when you work with ai workloads @coarse relic

drowsy yew
#

can we get a power isa core on an alhambra ?! 😛

wanton sphinx
#

external psram may be supported though

#

hmmm only bank0 region0 is supported, which I think means you could have psram but not flash

young tusk
#

@wanton sphinx I bet we could get it going. it just won't be able to run much

normal kestrel
#

I want someone to make like a DIP40 risc-v

#

just for cool-factor

potent echo
#

@drowsy yew You can install picosoc on alhambras. I or II?

potent echo
#

@normal kestrel This is almost at dip40 🙂

#

A company in Colombia made some prototypes and one the early ones was hand wire-bond to a dip40.

coarse relic
#

NXP offered some nice ARM CPUs in DIP packages, but they're all discontinued now. 😦

lofty ether
coarse relic
potent echo
#

Cheaper than brand STM32s...

#

One of the big things that should come with riscv is dirty cheap chips.

#

A cool new thing about this chip is that is has "USBFS (OTG)", which I'm not sure if it's the same usb thingy needed for CircuitPython.

#

It's similar in RAM to an M0.

tender mirage
#

All week the product listing page has said, "Available Aug 30, 2019." Now it says,

#

(oops) "Estimated availability Date: Oct 09, 2019"

#

I guess it's already the 30th in China and they're sold out?

#

I had looked on the GigaDevice website and couldn't find a datasheet or user manual for the gd32v.

normal kestrel
#

Rust register defintions for a chip that hasn't even shipped yet

#

now that's bleeding edge

wanton sphinx
#

I did pre-order some of those sipeed risc-v boards, please wait 2 months for manufacture + 1 month for shipping.

#

(the one @coarse relic mentioned)

normal kestrel
#

I think the first batch of preorders was supposed to go out today and the 2nd batch is october

#

that's what I heard anyway

coarse relic
#

Those are interesting, look like a cross between a Launchpad and an Arduino.

#

I usually end up using Bhiner when purchasing from Taobao.

normal kestrel
#

yeah I think it's a nucleo clone

#

I was looking at yoybuy

#

I checked a few other taobao agents and they weren't showing the longan nano

coarse relic
#

I'm not familiar with Yoybuy, but they look legit.

normal kestrel
#

lol when I joined the site it said I had a $10 coupon but it won't let me use it

coarse relic
#

That's irksome.

normal kestrel
#

oh I see

#

it's not available until tomorrow

#

or something

#

is it tomorrow in china?

#

yeah nevermind

#

it says 10:24 aug 31 which is when I registered in shenzhen time

#

so idk

coarse relic
#

Those things bewilder me. I did order a computer once, and it arrived 18 hours later, not bad at all for a trip halfway around the world.

normal kestrel
#

I'mma test their support

coarse relic
#

I'm curious, let us know how it goes

normal kestrel
#

will do

#

I thought maybe I had to spend more than the coupon to use it but that doesn't appear to be the case

coarse relic
#

Oh, they're letting you use the coupon?

normal kestrel
#

Haven't heard back yet. But adding more to my cart didn't help

coarse relic
#

Ah, so that wasn't it. Maybe you can only use coupons in phase 2?

normal kestrel
#

Phase 2?

coarse relic
#

Many of these reshipping outfits have a 2-phase process, where phase 1 is buying something and having it shipped to them, and phase 2 is reshipping it to you.

normal kestrel
#

It's asking me if I have coupons but not accepting the code

coarse relic
#

We'll see what their support people say, I guess.

normal kestrel
#

you gotta spend $20 to use it

normal kestrel
#

And it's a $6 coupon not a $10.

coarse relic
#

That's disappointing, but not really surprising.

potent echo
#

Now, making a class to teach riscv asm is just inevitable 🙂

potent echo
#

(tool, not "took")

cinder needle
#

owo riscv

#

the sipeed riscv board with ML accelerator is so nice

tender sparrow
#

32k of ram? That seems to be a step in the wrong direction. I guess they all start small and get bigger.

coarse relic
#

Could be the current implementation is built out of an FPGA, using logic blocks as RAM. To get more RAM, you'd need either external RAM (and an interface to it), a more custom chip, or possibly an FPGA with more built-in RAM.

tender sparrow
#

I'm a noob.. but I hear on the wednesday show that there is some excitement around the STM32 chip. Can anyone enlighten me as to why?

coarse relic
#

There are several vendors of ARM CPUs. There's Microchip, who makes the SAMD series that are built into a lot of AdaFruit products. There's ST, who makes the STM32 series, and NXP, who make the chip powering that Teensy 4.0, and a few others.

#

They're all fairly powerful (compared to an Arduino), so the differentiators are generally price, built-in peripherals, debugging support, and development environments. That last doesn't matter much to people who just use the Arduino IDE.

#

There are the obvious, easy to compare ones like amount of RAM, amount of flash, and CPU speed, and the trickier but still important ones like what peripherals are available, how flexible are the pinouts, and how easy the peripherals are to use (which includes quality of documentation).

tender sparrow
#

I loved when ladyada discussed the new Teensy 4.0 on the wed show.. she had @young tusk as a guest.. you could hear his excitement . 1Meg of ram would really open up some possibilities for new tasks with CP.

young tusk
#

@tender sparrow we'll get there. only so many things we can do at once

#

worse case is something better comes out before then

tender sparrow
#

ah ya.. that would be terrible 😉

young tusk
#

😄

tender sparrow
#

I have no idea what I would do with 1M of ram with CP.. but darn it I would find something 🙂

normal kestrel
#

wow so yoybuy cancelled my order without telling me because it was out of stock

#

and they kept my money in the store's "wallet" rather than actually refunding it

coarse relic
#

Wow. That sucks, but I'm glad you told us.

calm mortar
#

And now you're asking yourself "Why, Oh Why buy from there?" 😉

coarse relic
#

Yeah, I think I'll stick with Bhiner.

#

I guess you could dispute the charge with your credit card company (if you used a credit card for it) – credit card companies dislike chargebacks, so vendors that get too many find their transaction fees go up.

normal kestrel
#

I just reordered with the "wallet"

coarse relic
#

Hoping it will be back in stock?

normal kestrel
#

Yeah it looks like it is

sand gyro
#

Wait we have a risc v channel?
cool.

#

I grabbed the m5stack ai cam

#

Exciting so far.

wanton sphinx
#

that reminds me, I placed an order for the sipeed longan nano back on august 31. still shows as pre-order, an october 9 estimated availability date on my order, october 31 on the product page. good thing I would not have time to play with it anyway

coarse relic
#

Seeedstudio just sent an email about availability

sand gyro
#

The m5Stick AI cam.

And the problems so far.

Holding the power button 6 seconds to try turn it off.
It keeps powering back on right away.

Mic is broken due to a flaw and and it looks like he wont continue with it as he is busy with v2 with wifi

  1. if you make a basic firmware, make sure the off button actually does what the manual says.
  2. the manual covers less than some terrible products.
  3. manual.. please actually describe your workings.. like how the off button works...

i can't even understand it's quirks.. connecting via serial reboots it??
Then serial monitor is lost searching.

Starting to think i made a huge mistake.
such a awesome device.. so much potential.

#

I think this product is dead before it flew

#

Other than that.
It works

#

but acts like a untamed child

burnt glen
#

M5Stack products always turn right back on when a power supply is connected. You can also turn it off by double tapping the power button

sand gyro
#

Idk why after purging all serial drivers and reflashing it now works

coarse relic
#

Beats not working, I suppose.

sand gyro
#

Problem has returned.
☹

#

🤷

coarse relic
#

Sounds like an intermittent connection. Might be worth eyeballing it with a good magnifier, or pressing gently in various places and/or heating or cooling it.

sand gyro
#

letting the battery run flat fixed it.

#

O_o

#

i think this may be the firmware.
or the AXP192.
gona let it charge and see what happens

coarse relic
#

Could be the power-up doesn't go correctly sometimes (many circuits misbehave if the voltage goes low but not to zero, or rises too slowly).

sand gyro
#

But so far i am just loving this device.
i have been prodding at it the entire day.

sand gyro
#

M5stack's developers verified my problem and will be releasing firmware fixes next week.

📎 unknown.png
coarse relic
#

Nicely done!

normal kestrel
#

I got my longan nano

coarse relic
#

Yay! Hopefully you'll have cool stuff to share!

normal kestrel
#

yeah if I can get a flashing toolchain going

#

I tried openocd and it doesn't recognize the flash type or something, and dfu-util requires a fancy dfuse file

#

or a raw bin

#

and I'm working with an elf

#

and I don't really wanna find the right binutils to convert it

#

looks like I have to compile a special version of openocd

#

well the blinky someone else wrote is busted but it's flashed and running some rust code 🙂

#

it lights but doesn't blink lol

normal kestrel
#

it's trickier to port stm32 code than I hoped

#

they renamed many registers

sand gyro
#

i'm excited to see v2 of the m5stackV

#

i believe this one will use the kendryte K233

sand gyro
#

So far working way better

wanton sphinx
#

It will enter dfu mode, that's all I know so far

coarse relic
tender mirage
#

@coarse relic Really nice find! Those are some long videos too. I've had stuff like this in my head a lot lately. Alas what's interesting to me right now is the instruction controller which is in part 6, many hours of viewing away. 😟

coarse relic
#

Yeah, I'm more interested in the actual guts of it than registers and such.

normal kestrel
#

I really enjoyed that series

#

watched it a few months ago

lofty ether
#

As soon as I saw the silkscreen on these connectors, I knew he was gonna have a hard time

📎 unknown.png
coarse relic
#

The nonstandard numbering, or the notch?

#

I've had issues in the past with DIP switches with 1-based labelling, and most software using 0-based numbering.

lofty ether
#

When you number pins on a 2 row zig-zag style, odds better all be on one row

#

So 1 on one end and 30 on the other, it doesn't compute

coarse relic
#

Ouch, didn't catch that!

sand gyro
#

it's so weird that risc was such a underground piece of hardware for years.

"The RISC architecture will change everything". 1995, Angelina Jolie, Hackers.

native willow
stark seal
#

Macs used PowerPC from 1994-2006

coarse relic
#

RISC is a loosely-defined set of characteristics generally including a register-rich, load and store memory model, fixed length fairly orthogonal instructions, execution in a small number of clock cycles, etc. Some early CPUs, such as the PDP-8, RCA 1802 (and, to a lesser extent, the Motorola 6800) displayed a lot of these characteristics.

#

A lot of the RISC architectures mikerenfro mentioned (as well as some others, such as MIPS) have fallen by the wayside. These days, the major RISC player is ARM, but IBM's PowerPC is still being developed (the current Power9 architecture is being used by Google among others), RISC-V is getting a lot of interest, and the MIPS ISA is going open source, but we have yet to see if it gets any traction.

#

Intel and AMD have some powerful RISC cores that are hidden inside their X86 chips, running the X86 ISA as some very involved microcode. I thought they should have released their RISC cores separately as a compact, low-power CPU, in an environment (such as Arduino) where X86 wasn't already entrenched, but Intel decided to attempt to sell X86 in the Arduino world, where it foundered and was quickly abandoned.

tender mirage
#

The U in ARM stands for underground. 😛

#

Also, the MIPS architecture is still widely used for embedded applications, especially in routers and networking. The most popular platforms for the OpenWrt firmware project are MIPS based.

lofty ether
#

ARMs have been replacing MIPS in the SOHO router space pretty quickly

#

Big install base out there for sure though

tender mirage
#

@lofty ether Not too surprising I suppose. I did want to point out that MIPS hadn't entirely gone away. I could see RISC-V really catching on in that area though since binary compatibility isn't a thing.

lime seal
#

Hey, could anyone help me with risc-v?

tender mirage
#

@lime seal We can try. What's your question?

past orbit
#

Hey all, there was a great keynote at SuperCon this year on RISC-V and the idea of open ISAs by Megan Wachs, the VP of Engineering at SiFive, the company founded by the creators of the RISC-V instruction-set architecture (ISA). I'm trying and failing to find a video to post it here, but if anyone beats me to it, please do!

coarse relic
#

I didn't see the keynote but I think it's the way to go, and it's good to see the RISC-V, MIPS, and PowerPC ISAs being open-sourced.

wanton sphinx
#

suppose I want a riscv gcc toolchain on debian stable, without involving arduino or other IDE. where do I want to start? https://github.com/riscv/riscv-gnu-toolchain maybe? I guess there's no reason I can't build it m'self

GitHub
riscv/riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC. Contribute to riscv/riscv-gnu-toolchain development by creating an account on GitHub.

tender mirage
#

@wanton sphinx That sounds like a fun way to spend a weekend. 😉

wanton sphinx
#

.. I still have not touched the sipeed longan nano which I over a month ago 😦

tender mirage
#

We're all amateur curators of private dev board museums.

#

But I remain a fan of the "steal the cross toolchain out of the Arduino support package" approach.

coarse relic
wanton sphinx
#

hum their build process is .. not in alignment with my expectations. make failed with ```mkdir: cannot create directory ‘/usr/local/share/gdb’: Permission denied

# 
gcc version 9.2.0 (GCC) 
``` okay that is fine
wanton sphinx
#

detoured and built a blink example with platformio. That was actually relatively painless and commandline oriented. Too bad I always get an error from the dfu utility: ```File downloaded successfully
dfu-util: dfuse_download: libusb_control_transfer returned -4
*** [upload] Error 74
========================== [FAILED] Took 2.24 seconds ==========================

coarse relic
#

Hmm, I wonder if that's EINTR

wanton sphinx
# 
Nov 20 13:26:39 localhost kernel: [   21.670173] usb 1-3: Manufacturer: GDMicroelectronics
Nov 20 13:26:39 localhost kernel: [   21.670174] usb 1-3: SerialNumber: 䌳䩂

I wonder what the serial number "means". The first character might be "a kind of unrefined or unpolished silken textiles" and the second "to come to the front, to take the lead, to bear responsibility" according to wiktionary. It could be poetic, or maybe it's all misinterpretation by an uninformed person who doesn't have any familiarity with the language.

#

@coarse relic probably LIBUSB_ERROR_NO_DEVICE = -4

coarse relic
#

Hmm, that's more likely

wanton sphinx
#

looks like maybe it uploads the firmware, implicitly resets (leaving DFU mode), and then tries to something the fuses (download them?)

#
  • This implements the ST Microsystems DFU extensions (DfuSe)
#

or maybe it's doing something totally inappropriate for the target

normal kestrel
#

yeah I couldn't get the dfu to work and wound up using jtag

#

apparently other people have got it to work though

#

are you putting it in dfu mode by pressing the button on boot?

#

@wanton sphinx

wanton sphinx
#

@normal kestrel DFU does "work" for me. With the device plugged in to USB, I hold the BOOT button and tap the RESET button. Some internet notes tell me that it's important to use a modified dfu-util, which platformio has automatically picked up. Other people, well, they never seem to have much luck.

normal kestrel
#

oh I thought it wasn't working

wanton sphinx
#

The error doesn't seem to mean anything, as long as it prints "file downloaded successfully" immediately before

normal kestrel
#

I see

normal kestrel
#

I just tried again on my longan nano and got it to work, and didn't see that error

#

maybe something is amiss with your usb

#

one of my friends in the rust community got a spi driver going, and since rust-embedded abstracts things like spi, we got a display driver for free https://twitter.com/d1sasm/status/1192203372163731457

Disasm (@d1sasm)

More @rustlang on @SipeedIO Longan Nano board! In @rustembedded you can just implement SPI driver for your MCU and get all SPI display drivers for free. Write once, run everywhere!

Twitter
normal kestrel
#

by "abstracts things like spi", what I mean is any spi-based device driver will run on any device with a HAL that supports spi

#

so long as both conform to the standards

#

it's super cool

#

I wrote and tested this st7735 driver on my metro m4 arm device, and here it is running on risc-v!

#

excuse my nerding out

coarse relic
#

Since SPI generally boils down to a single transfer() call, it's not hard to abstract.

wanton sphinx
#

@normal kestrel nice

normal kestrel
wanton sphinx
#

I wouldn't mind moving to Switzerland, it seemed nice when I visited...

tender mirage
#

I changed planes in Geneva once. Maybe that doesn't count. But the chocolate is really good and Roger Federer seems like a decent fellow.

sand gyro
#

linux for the k210

tender mirage
#

Nice work there!

sand gyro
#

already testing on other boards

coarse relic
sand gyro
#

Alright i need to get a RISC V based board and do programming on it using assembly or C++

half zodiac
#

Sorry for being late to the party, but is there a specific development board the Adafruit team is using?

young tusk
#

@half zodiac we're not actively doing any risc-v stuff

half zodiac
#

Awww @young tusk everyone seemed so excited a while back....

young tusk
#

just waiting for the right mcu to come along 🙂 I did do some basic work for the risc-v soft core on the fomu fpga board

half zodiac
#

That's kind of what I was thinking (waiting on the MCU). I had hoped maybe you'd picked one. 😉

young tusk
#

I did snag one of the GD ones but it's only 16k RAM 😕

half zodiac
#

Huh. There seem to be a few vendors, but everyone seems to still be figuring things out....

young tusk
#

ya, still early days

wintry fulcrum
potent echo
coarse relic
#

Elektor magazine has a nice "First Steps with RISC-V" article in their January/February 2020 issue. https://www.elektormagazine.com/magazine/elektor-139/57019/

Elektor
First Steps with RISC-V

After ARM, RISC-V could be the next big thing on the processor market. The instruction set architecture driven by a large consortium [1] is license-free and suitable for both embedded and computer processors. However, there are still only a few microcontrollers and boards to ...

normal kestrel
#

Gotta register to read 😩

coarse relic
#

True. I'm a subscriber, so I have access. They generally unlock articles for general access after a while.

neon holly
#

Hey, nice group.... Was just planning to get through RISC-V from scratch. Found an interesting example on arty board. I am new to this though I have designed VLIW architecture processor on a FPGA for DSP applications and applied some filters etc. My question is what would you suggest me to do to get more practical experience in this domain of open source world! Should I continue on Arty as a starter?

normal kestrel
lime seal
#

Hey

#

can someone help me with shifting bits?

#

I'm stuck on the last part of my project and I can't figure it out. I need to shift 12 bits for each iteration

#

so I can't just do a shift of 3 (2^3)+4

#

This has been driving me nuts 😦

coarse relic
#

You should be able to do something like ```c
x <<= 12;

lime seal
#

But

#

I'm iterating thru an array

#

So how would I be able to say shift 12 then 24 then 36 with a limited amt of registers?

coarse relic
#

In C? Assembler? Something else? I'm not sure where the array comes in either.

lime seal
#

In C

#

We're converting C to Risc V

#

So like

#

Each array element is this

#

One name which is 8 char so 8 bytes. Then a score <100 which is a word of 4 bytes

#

so basically, to access the next (ith) element, i need to shift my memory over by 12 bytes

coarse relic
#

Ah, byte shifting instead of bit shifting. Normally that's done with indirection.

lime seal
#

Lemme google that rq

#

My professor skimmed over bit manipulation and just focused on other things

#

so I'm pretty lost on it

coarse relic
#

The way I usually do stuff like that is with type punning: ```c
unsigned char * array;

struct entry {
char name[8];
int score;
};

struct entry * entryptr = (struct entry *) array;

process(entryptr->name, entryptr->score); // first entry
++entryptr;
process(entryptr->name, entryptr->score); // second entry

#

However, you can also do it with byte pointers: ```c
unsigned char * array;

process((char *) array, (int) *(array + 8)); // first entry
array += 12;
process((char *) array, (int) *(array + 8)); // second entry

#

The two code fragments do the same thing, they're just expressed differently.

lime seal
#

But like

#

How would I write in in risc v?

coarse relic
#

What language?

lime seal
#

risc-v assembly language

#

let me give you an example code

coarse relic
#

Ah, that's why I asked what language earlier.

#

I wondered why you mentioned register usage.

lime seal
#

slli x6 x21 3 #x6 = k * 8

#

the # is like a comment

#

yeah my bad bro. I kinda am freakin out

#

i been stuck on this for like 4 houts

coarse relic
#

Typically, you'd use a register containing the address of the array, and use it directly to access the name like "load [r0],0" and the score at an offset of 8 like "load [r0],8". Then increment it by 12 to point to the next entry like "add r0,12,r0", re-using the same register.

#

That's ARM-like syntax, as I'm not very familiar with RISC-V syntax, but I assume it offers equivalent operations.

lime seal
#

Ok I’ll try to figure it out thanks tho

#

Cuz the problem is the iterator

#

So it could be 12 24 36 bytes shifted over

coarse relic
#

Luckily, you won't have to deal with unaligned fetches, since you incrementing by a multiple of 4. In short, you don't need any shift (I'm guessing "slli" is something like "shift left logical immediate") operations, just "add" and indirection.

lime seal
#

But what if iterator is like 10

#

Then we need 10 add 4s

coarse relic
#

Not really, just add 12 (or 10, for the other case) to the register holding your array address (aside from aligned fetch issues which won't be a problem with the name, but could be a problem with the score, if your stride isn't a multiple of 4 bytes)

#

I darkly suspect you're making this harder than it is.

lime seal
#

No it’s like each iteration is 12 away

#

We only have a limited ant of resistors

#

We have like 8 ppl here stuck on it 😦

coarse relic
#

When you say "each iteration is 12 away", I read that as "each entry in the array is 12 bytes away from the previous entry". Is that wrong?

lime seal
#

That’s true

#

But we’re not reading them all at once

coarse relic
#

It looks to me like you only need one register for the address of the current entry, and possibly another one to load stuff like the name and score into (depending on what you're doing with them).

lime seal
#

It’s just whenever the swap function is called

#

Honestly we might be able to use another ur right

coarse relic
#

Ah, swap: I didn't know about that part. To swap 2 entries, you'll need another register or two.

lime seal
#

Yeah man so were working on limited supply

#

You say add 12 but what if we need like the 4th element so like 48

#

Maybe we set up a loop actually

#

Oops

coarse relic
#

While it's tempting to have a loop to swap entries, you can fit the entire entry in 3 32-bit transactions, so it makes sense to "unroll" the loop and just crank through them longhand.

lime seal
#

No a loop to just get the value for the entries

#

So like increment 12 until a certain number is matched

coarse relic
#

So you'll need 3 registers. Either one for each address to be swapped, and a temporary register, or one for the base address and one for an offset, and a temporary register.

lime seal
#

Ok lemme try. Thanks for stimulating my brain😤

#

I worked too hard to go out like this

coarse relic
#

I think you have the right idea, and remember: you can make a register do double duty as the address you're working on, as well as the value to compare to, to see if you've reached the end of the loop.

lime seal
#

Oh yup

#

Only thing I hate about risc v

#

Not enough online like examples

#

I think that’s how I learn best

coarse relic
#

Yeah, it's early days yet, so it's wandering around in a dark forest a lot.

lime seal
#

Appreciate the help man

#

You west or east coast?

#

I go to UC Davis

coarse relic
#

East coast, it's after midnight here.

lime seal
#

Yup brb ill report back if it works

#

x10 is our address of beginning of array

x11 is j (our iterator to move us up and down)

swap:
add x6 x10 x0 #*x6 = x10
addi x28 x0 0 #a == 0 (a is an iterator that acts as a mulitplicant)
Loop:
beq x28 x11 Exit ##if
addi x6 x6 12 #NumOfStudent << 12
addi x28 x28 1
beq x0 x0 Loop
Exit:
lw x5 0(x6) #(temp) x5 = v[k]
lw x7 8(x6) #x7 = v[k+1]
sw x7 0(x6) #v[k] = reg x7
sw x5 8(x6) #v[k+1] = reg x5

#

about to test it out rn

#

oops

#

put x10 should be t0 for testing rn

#

I think it works

#

God bless ❤️

coarse relic
#

You can probably factor out x28, and use beq x6 x11 instead (by adjusting x11 appropriately), saving a register, if I'm reading that correctly (I may not be!)

lime seal
#

x11 is function argument register

#

so i think we dont wanna touch it

#

using another temp should be fine tho

#

we're not using the temps outside

lime seal
#

Lets goooooooooooooooooooooooooo

#

I love you bro

#

❤️

#

Ima be coming back here a lot for risc v

#

this is only the first project

coarse relic
#

This article is interesting: https://hackaday.com/2019/11/12/risc-v-why-the-isa-battles-arent-over-yet/ The part that sticks out for me is the lack of branch prediction. The article keeps insisting that this will cause performance degradation, but it also means that it's immune to Spectre/Meltdown type issues. And the article does mention in passing that the compiler will have to generate separate code paths, which I don't think is entirely correct. If/else will still work (so code doesn't have to be larger), it's just that the processor won't attempt to "guess" how to fill the pipeline. However, in many cases, the compiler will have a better "big picture" view than the CPU can, and can better optimize for the likely branch directly. Once compilers can do this reasonably well, the touted performance disadvantage dwindles.

tender mirage
#

@coarse relic I did a moderately deep dive after reading that article back when it was posted. From https://en.wikipedia.org/wiki/RISC-V#Subroutine_calls,_jumps,_and_branches: "RISC-V has no condition code register or carry bit. The designers believed that condition codes make fast CPUs more complex by forcing interactions between instructions in different stages of execution. [...] As a result, predication (the conditional execution of instructions) is not supported. The designers claim that very fast, out-of-order CPU designs do predication anyway, by doing the comparison branch and conditional code in parallel, then discarding the unused path's effects. They also claim that even in simpler CPUs, predication is less valuable than branch prediction, which can prevent most stalls associated with conditional branches."

RISC-V

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.
Unlike other academic designs which are optimized only for simplicity of exposition, the designers state that...

#

Something important that I didn't notice for a while: "predicAtion" vs "prediction".

#

I've been hearing the "compilers these days are so smart" vs "silicon these days is so cheap" debates since the early 90s. If experience hasn't shown one path or the other to be the clear winner, my guess is that it doesn't matter so very much.

coarse relic
#

I largely agree. I figure a lot of this prediction logic eats up silicon area which could be used for more registers or better signal routing, but it's not a big deal.

#

I'm unclear on the difference between "prediction" and "branch prediction" (I thought they were the same thing).

#

However, I am interested in freedom from Spectre, Meltdown, and indeterminancy.

#

I do remember the earlier pentium chips did a fairly brain-dead "branch prediction" by simply alternating whether they prefetched for branch or no-branch.

#

Oh, you said "predication", not "prediction" and I didn't catch it even though you emphasized the difference. Oops. Hmm. That's a new one on me.

#

I did learn while programming the Cell/BBE that sacrificing everything for maximum performance yielded the ability to do insanely fast processing, but at the cost of more difficult development. That chip didn't even have MMU capabilities, so you'd have to explicitly code in DMA calls to start fetching the data you'd need later. On the upside, I managed some code that had 81 instructions in-flight at once and maxed out 8 of the 9 CPUs on the chip in a sustained fashion.

tender mirage
#

Motorola/Freescale DSP56k processors have conditional execution based on status bits for operations other than branching instructions to avoid having to change the control path. That's a long way from a RISC architecture, and the model there was based on very speed-critical, hand coded, carefully tuned, short routines. Especially with the simple instruction schedulers on those chips, there were gains to be had that way.

#

But I have a feeling that, as much as anything, minimizing binary code size is generally a good thing. The speed-and-cost-vs-size memory hierarchy isn't going away, and fitting more instructions in level 1 cache instead of level 2, or in core memory instead of swap, is always a win. And how much do we care about whether or not this one more module can be squeezed into CircuitPython on a certain board?

#

Leaving a lot of extra conditional bits in the instruction set on the chance that compilers might use them in a smart way might not be so great in that respect.

coarse relic
#

Most RISC CPUs have 32-bit instructions in which many of the bits are not used, so that may not make as much difference as imagined. Even the ones where the bitfields are fairly full, there aren't 4 trillion different instructions, so there's room to add variants for "expect branch" and "don't expect branch". Even that's not strictly necessary for optimization, as code can generally be rearranged to make "don't expect branch" the usual default.

#

Of course, one way to minimize binary code size is to go back to CISC, but I don't think that's the way forward. 🙂

#

Remember CPUs with instructions like "convert to decimal" and "sort array"?

tender mirage
#

I do indeed remember CISC instruction sets with all that stuff. I used to program VAXes. 😄

#

Another good way to reduce binary code size is to leave more bits in the 32-bit instructions for immediate operands and branch offsets.

coarse relic
#

I didn't do much assembly on VAXen, but the Univac 1104 had a surprising variety of machine instructions too.

#

Ah yes, the ARM ISA did a lot of creative things to use all those bits in various ways. I became quite fond of the "set condition flags" bit.

tender mirage
#

When you're using a teletype with a roll of paper to write your programs, reducing the number of assembly instructions was a really attractive thing.

coarse relic
#

Heh, I've been there! Similar when you had to wait in line for a card punch.

#

Now I have the pointless urge to add a card reader to a RISC-V machine.

tender mirage
#

Being able to edit a program by rearranging the cards in the deck is really kinda cool. And you can copy and paste by running cards through a duplicating punch, although that thing was fussy to use. I remember having more trouble than success with it.

sour night
#

mechanical or optical punch card reader? array of photo diodes or CCD?

coarse relic
#

The Univac had an optical punch card reader. It was FAST. It ran the cards through with rollers under a surprising amount of pressure. One time, one of the professors spilled coffee on his deck, and decided to run it through while it was still damp. The cards shot out of the other side of the reader a little larger and flatter than they started, and then wadded up into mush. It could read through a whole box (a little over half a meter of cards) in 20 seconds or so.

sour night
#

was there ever a verified case of somebody getting strangled by getting their tie into the card feeding mechanism?

#

That Univac sounds like it would pop their head clean off

burnt glen
#

Does anyone have experience with the GD32VF103 chip?

#

It is the first RISC-V microcontroller that I have seen that actually has analog i/o

#

It is made by GigaDevice, one of those obscure chinese manufacturers

#

Previously they released pin-compatible stm32 chips

feral dock
#

I haven't worked with the chip myself, but it looks pretty decent, and a few people have done dev boards for it. GigaDevice isn't that obscure, though they're mostly known for memory... they're on Digi-Key, and I've seen them at U.S. trade shows.

burnt glen
#

Their microcontrollers are really obscure, they sell a gd32f103c8t6, what is almost the stm32f103c8t6.
The microcontrollers are not sold outside probably because of legal issues

#

It is apparently software compatible as well. That is really sketchy

#

Probably a political effort from the Chinese government to become less dependable on the united states

tender mirage
#

@burnt glen There's been a decent amount of chat here about gd32vf chips, and lots of news coverage when they first appeared. I didn't get one of the SiPeed Longan Nano RISC-V boards (not yet anyway) but I remember a few others doing so.

lime seal
#

I'm a risc-v noob. Had a few questions if anyone had the time

#

What is the relation between physical and logical registers?

#

is a logical register some thing like (rs1, rd1) like the registers in the instruction field?

#

Whereas a physical register would just be x0-x31, any of the registers we have for use?

lime seal
#

? sorry if it's a dumb question

burnt glen
#

Not really, I think the best part in understanding the relation between physical registers and logical registers is the reason they exist.

Basically a physical register is an actual place where data is stored. Logical registers is a register you right in a program.

#

A advanced CPU doesn't have to execute the assembly in the order that is given to it

#

The cpu can reverse the order of execution. This would lead to problems if actual physical registers were used

lime seal
#

So a logical register would be the registers in something like addi x12,x0,1

#

so the logicals are x12, x0.

#

But by the end of the program or procedure, the actual registers are implemented with the values ?

burnt glen
#

It is basically like giving your clothing to the dry cleaner. You get a number. The drycleaner stores it somewhere. You come back and give the person your number and it gets your item

#

The physical register is the place where the drycleaner stores the clothing. The logical register is the number you give to the drycleaner

#

No wait, it is like the drycleaner gives it a different number that they only use internally. When you get back and present your number it translates your number to what they use internally.

lime seal
#

Ohhh makes sense now

#

I had another question if you had time?

burnt glen
#

Virtual register might be a better word.
Ok sure!

lime seal
#

.data
k: .word 0x00000064
val: .word 0x456789AB
.text
lw x6, k

x6 contains 64

lw x10, val
sw x10, 0(x6) # this initializes Memory[00000064]=456789AB
lw x5, 0(x6)
lb x7, 2(x6)
lbu x8, 2(x6)
lh x9, 2(x6)
addi x10, x0, -5
sb x10, 0(x6)
lw x5, 0(x6)

#

sorry wrong one.

#

.data
k: .word 0x00000064
val: .word 0x456789AB
.text
lw x6, k

x6 contains 64

lw x10, val
sw x10, 0(x6) # this initializes Memory[00000064]=456789AB
lw x5, 0(x6)
lb x7, 2(x6)
lbu x8, 2(x6)
lh x9, 2(x6)
addi x10, x0, -5
sb x10, 0(x6)

#

This is code we were given. At the end, my professor says that memory[00000064] should be fb896745

#

to me, it should be 457689FB. Am I wrong or what?

#

Also for risc-v instruction formats, does imm[11;0] mean that we have a constant that can be a max of 11 bits?

feral dock
#

12 bits, I think, though often it's a signed value, so the maximum positive value is effectively 11 bits.

#

I think both you and your professor are right, though. The bytes at memory address 0064 are FB 89 67 45, which would be interpreted as the integer value 0x456789FB.

normal kestrel
#

@burnt glen I have a gd32vf103 what do you want to know?

burnt glen
#

Does it work well? Have you also used it for RISC-V itself? @normal kestrel

normal kestrel
#

It's pretty good. Like all things it has a couple silicon bugs. I haven't done any risc-v assembly if that's what you mean.

burnt glen
#

What do you mean with silicon bugs?

#

Silicon bug can mean a lot of things

normal kestrel
#

I'm not sure exactly but I heard there are some problems with some of the risc-v registers

#

I'll check with the person that mentioned them to me previously

normal kestrel
coarse relic
#

I suppose bugs in FPGA implementations can be patched by loading an updated bitstream.

burnt glen
#

This is not an FPGA implementation @coarse relic

potent echo
#

Anyone testing or have working the linux port for the Maix boards?

#

I can flash them and the kernel boots up, but in the case of the Maix Go, it does not transition to userspace properly so it gives a kernel panic.

#

@crisp saddle Please let me know if you got it working.

crisp saddle
#

Sure. I'll be trying it later tonight

crisp saddle
# 
[    0.276874] kernel BUG at arch/riscv/kernel/irq.c:43!
burnt glen
crisp saddle
#

Not yet, I was just hoping the prebuilt would work before I went through all the build steps

#

@potent echo I just posted here

potent echo
crisp saddle
#

I will give the build instructions a try

potent echo
#

Nice.

crisp saddle
#

The really weird thing is... the first time I flashed it, i opened the serial port and found a root prompt

#

i typed uname and it worked

#

then I typed in exit to see if login prompt would come up

#

and it kernel panic'd

#

and I've thus far not been able to get back to the kernel prompt

#

reflashing does not help

#

very odd... I didn't take any screenshots of the first time

#

almost makes it feel like my imagination 🙂

potent echo
#

That could be by design, mini-distros sometimes will just use a shell, instead of init. But after a reboot everything should be ok.

crisp saddle
#

yeah... weird that I can not reproduce

#

the only thing I can reproduce is

potent echo
#

I also tried one time, flashing Maixpy in between just to try, but nothing here.

crisp saddle
# 
[    0.242148] This architecture does not have kernel memory protection.
[    0.248562] Run /sbin/init as init process
[    0.252755] Run /etc/init as init process
[    0.256935] Run /bin/init as init process

----------------[    0.266674] unexpected interrupt cause 0x8000000000000009
[    0.266686] ------------[ cut here ]------------
[    0.276658] kernel BUG at arch/riscv/kernel/irq.c:43!
[    0.281693] Kernel BUG [#1]
[    0.284480] CPU: 1 PID: 1 Comm: sh Not tainted 5.6.0-rc1-g9dbcd412b #5
#

oh

#

I could flash Maixpy and then try again

burnt glen
#

I am going to try as well

#

I also got the error on my MaixDuino

# 
[    0.265385] unexpected interrupt cause 0x8000000000000009
[    0.265394] ------------[ cut here ]------------
[    0.265413] kernel BUG at arch/riscv/kernel/irq.c:43!
[    0.270024] ------------[ cut here ]------------
[    0.275408] Kernel BUG [#1]
[    0.280011] kernel BUG at arch/riscv/kernel/irq.c:43!
[    0.285053] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.6.0-rc1-g9dbcd412b #5
#

Why do you get CPU: 1 PID: 1 while I get CPU: 0 PID: 0 ?

burnt glen
#

Sipeed also has a telegram where you can ask questions

lime seal
#

Could someone help me with floating numbers?

#

More specifically, bfloat16

burnt glen
#

I would just ask the question about bfloat16

crisp saddle
#

@potent echo very interesting! I flashed Python and then Linux again... and now there is a root shell

burnt glen
#

What python version did you flash?

crisp saddle
#

maixpy_v0.4.0_20_g06ed455.bin

#

the latest I found on their github releases

burnt glen
#

Yeah, is not working for me

#

I am using the k-flash gui though, the commandline doesnt work for some reason

crisp saddle
burnt glen
#

Ok, wierd that kflash.py doesnt detect my maixduino

#

But kflash gui is able to find it

potent echo
#

@burnt glen "-B model" should be used in kflash.py to specify the board if it doesn't detect it. Maybe you could try with some of the models. (with --help it shows a couple of models)

#

@crisp saddle I'll try again with my boards...

burnt glen
#

Yeah I just figered that out! I removed the -B model entirely

#

But thanks!

potent echo
#

Warning: the guide from github (https://github.com/vowstar/k210-linux-nommu) has a "make -j" in the kernel compilation, so beware if you don't have a huge box. It's better to add "-j4" or something like that with the amount of cores you have awailable.

potent echo
#

@crisp saddle No luck. I've just finished the guide from vowstar on github, works fine, does create a .bin file, but I still get the same results as before.

#

I even tried uploading maixpy 0.5, and then the images, and no luck yet.

#

Which BTW, I didn't notices that kflash.py has a "-t" argument, so that it gives you a terminal as soon as it reboots.

potent echo
#

The tutorial from cnx-software is basically the same thing (with the same make -j warning...), so I'm stuck here.

potent echo
#

Hey, I just tried it on a "new" Maix bit, and now I have the busybox sh. ❤️

potent echo
#

I'm guessing my Maix' Bit and Go are a first revision with something different. And this "new" Bit I gave to a student is the same as what you guys have...

burnt glen
#

Seems like I have the old ones as well! @potent echo

#

I wonder if it is just an old bootloader

potent echo
#

I don't see how or where to update it. An old tutorial mentions using uPyLoader to try to remove a frequency.conf file, which I'm guessing controls overclocking or serial stuff, but no luck with such file.

burnt glen
#

Haven't found it either, I assume that the way it communicates with the flash tool is in software somewhere

#

But havent found anything that could update that software

#

It must be software since sipeed included the board type in the chip....

potent echo
#

Yeah, there are two versions. "CH340 was changed to CH552".

#

And with a jewler's magnifier I can confirm that the old (552) version is the one that doesn't work, and 340 does.

#

@crisp saddle Can you please confirm that you have a new bit.

burnt glen
#

The new has one 552

#

The old version has CH340

#

You really need a jewlers magnifier for that xD @potent echo

#

They started using the CH552t because it has two serial connections

#

They added this to flash the new extension esp32 modules

potent echo
#

Yeah, said it backwards. New is 552, old is 340.

burnt glen
#

The old ones are the ones that work?

potent echo
#

The new ones work.

burnt glen
#

I have a maixduino with 552 and that one doesn't work.
They never released that one with the 340 though

potent echo
#

Let me try again... (/me needs coffee)

#

So, the old version I have, has a CH552T chip, this nano doesn't work with linux.

#

The new version, has a CH340C chip, and this one works, with -B bit, with -b 3000000, and also with the linux port.

burnt glen
#

My maixduino with CH552T works fine under linux

potent echo
#

Oh, and I just noticed they have dates at the bottom. So CH340C has a date of 03/01/19, and CH552T has 19/06/28.

burnt glen
#

Yeah, the CH552 is newer

potent echo
#

So new/old descriptions before are wrong. Yes, 552 is newer.

burnt glen
#

You just went from CH340 is old CH552 is new to the opposite, then back, then back again, now you are again at that the CH552 is the new one

#

Everyone has one of those days sometime

potent echo
#

Part of my confusion is that I got the 340 board way after I got the 552 board. My fault for buying from Amazon, so I probably got an old stock. Which is my I mixed them up.

burnt glen
#

The CH552t is also a bit weird that it uses the FTDI drivers

crisp saddle
#

just an update, I ran through the tutorial and was able to load and boot the new build on BiT:
https://twitter.com/pdp7/status/1229537919100162051

Drew Fustini 🐧 (@pdp7)

Fresh @RISC_V Linux kernel on @SipeedIO MAix BiT board thanks to excellent tutorial by vowstar!
🐧✨
And thanks so much to @olofj for giving me the board, and also Damien Le Moal and Christopher Helwig for working on NOMMU support to make this all possible!

Twitter
burnt glen
#

Yeah you have the CH340

crisp saddle
#

This BiT was given to me in september

#

[951458.709923] usb 1-4: ch341-uart converter now attached to ttyUSB0

#

yes

burnt glen
#

The CH552t is a bit smaller

crisp saddle
#

I have a GO on the way from Mouser. Will see what chip that one has.

#

This BiT is weird in that it has a wire mod

burnt glen
#

lol

lime seal
#

Hey!

#

I could use some help with floating point numbers with risc-v.

#

If anyone doesen't mind! I'd appreciate the help

sand gyro
#

@lime seal Not sure what you mean.

#

Implementing floating point math is a non-trivial programming job. ;)

#

Many Forth implementations do not implement Floating Point, if it's not already native to the hardware.

lime seal
#

It's a project i have to do in risc-v, we use bfloat16

#

basically, my question is how would you normalize the answer after you add/subtract the mantissas

#

like, if i do 6-5 = 1, the exponent is still 129 but the normalized form for 1 has an exponent of 127

#

I know that just from my brain, but how can i detect that thru my code?

coarse relic
#

I think you examine the mantissa and look for leading zeros.

lime seal
#

Yeah i figured it out

#

Yeah it was the leading ones

#

then shift based off the carry

#

and if there is no leading 1, then shift left

coarse relic
#

Expressif joins the RISC-V fray quietly by including a RISC-V coprocessor core in their new ESP32-S2 chip.

feral dock
#

Neat, didn't realize that! Now if only they'd add dual-band WiFi...

burnt glen
#

Seems like I am missing a part of the conversation

burnt glen
#

@feral dock I rather have Wifi-6 or Bluetooth-5 for low-power networking!

lime seal
#

Hey

#

Anyone here familiar with L1 caches/L2 caches?

#

I could use some pointers/guidance on the topic if anyone was free

#

Like yeah i dont get it

#

so do we implement an L1/l2 in both of them

#

and then the first code you do you make the l1 have a high miss rate by calling a bunch of random things not in l2?

#

and the 2nd code you just keep calling things already in l1?

#

is your homie doing this as well?

feral dock
#

I'm not understanding your context. Code should be agnostic to the cache structure for the most part.

sand gyro
sand gyro
#

^^ C java wrapper with a low foot print.
i'm guessing this will run

sand gyro
#

it Does!

pallid coral
#

hi, I'm trying to understand what exactly riscv-pk does and why it's needed, anyone aware of any writeup or something about this? Can't understand much from the README and from the "Environment Call and Breakpoints" section of the ISA

pallid coral
#

okay, looks like i need to see the "riscv privileged architecture description"

gray apex
#

This RISC architecture can't run 3/4 of the programs required right now for anything

sand gyro
#

Well i got zdoom to compile on my kendryte.

#

added yolo v4.

#

i'm going to teach it to play doom

boreal marten
#

Compiling and flashing works but no flashing LED

#

But using the latest code which is different.. it wouldn't allow me to change to led5 as the instructions suggest

#

Cutting and pasting in their example leads to lots of deprecation errors

#

So I'd like to get the latest version running if possible

#

Okay changed it to "#define PIN 5 // DT_GPIO_PIN(LED0_NODE, gpios)" and it works 🙂

boreal marten
#

I read this in a comment on the RED-V store page on SparkFun "If you are an early purchaser, your RED-V may have a wrong R8 value; SparkFun has provided an updated RED-V to correct this, as well as directions on how to re-work R8 on your first RED-V. The impact of incorrect R8 is the PLL clock will not run - but the board defaults to 16MHz crystal oscillator so this may not be a problem."

#

I've tried looking up the issue and the only reference I can find to it is "Hardware is SparkFun Red-V with R8 corrected to 100 ohms (power supply filter for PLLVDD)."

#

How can I check my RED-V to make sure it is a corrected R8 version of the board?

#

Okay I found it in the schematic. So according to this REV v10 has this fixed which is what I have

📎 RISC-V-R8.png
potent echo
fringe girder
#

I saw that the linux kernel is about to support the Kendryte K210 which is exciting but it lacks a MMU

#

Will we need to compile each applications for the usage of a MCU? I am struggling to understand how linux will manage memory excluding the heap for an application.

#

Testing the +4k cores riscv cpu.
Oh I saw that on twitter when that was being built up, super cool I wish I followed his account.

narrow solar
#

I think it's ucLinux, which is a version of Linux designed to run on MMU-less computers.

#

@fringe girder

fringe girder
#

The current linux version is @narrow solar but from what I read it's getting mainline support in either 5.6 or 5.7

#

I could be mistaken, but I googled it again and it says mainline

#

Maybe I misunderstand the current version of linux. Idk. Could you answer my question about the no MMU linux version that is current available if you have used it?

narrow solar
#

👀 . I hadn't seen that it's getting mainline support. That's actually really neat.

I've only used ucLinux a few times (for the Nintendo DS), so I don't have a ton of first-hand experience.

fringe girder
#

Wait, I can run ucLinux on a DS? That sounds awesome. What did you run on it?

narrow solar
#

I tried to run the PIXIL desktop/web browser (full color, optimized for low-memory systems), but unfortunately I didn't have any SLOT-2 (GBA slot, if you've ever used the DS) SRAM. Even worse, I lost my first flash card, and replaced it with a cheapo Games N' Music card which lacked proper DLDI, which meant that I couldn't patch Linux to run it. That basically killed my interest in it. That's the only program I remember trying to run. There may've been more, but most of the DSLinux applications were boring proof-of-concept text-based applications, which I didn't find very interesting.

Also, it was always a pretty novelty thing. I'd put it right up there with Linux on Palm Tungsten. It was eclipsed by actual DS homebrew, like Quake.

fringe girder
#

Ah, got it. I assumed there wasnt much for it and it was a bit of a headache but Im just into niche and weird linux installs 😜 or any os for that matter with a Windows exception

sand gyro
#

i like this

potent echo
restive ice
#

Oh wow

potent echo
#

Can't find any technical documentation on the riscv part of the chip. There's a tutorial on how to load a MI-V on it.

restive ice
#

I like the ambition of it, especially related to risc-v

#

I’m not sure I’ll be buying it anytime soon

feral dock
#

Finally. It's been a long time since the SmartFusion 2, so I've been looking forward to a next-gen SoC from Microsemi...

potent echo
#

It's in spanish, but Andrés Sabas from Electronics Cats is showing a very nice riscv chip the BL602, that it's kind of a ESP alternative.

acoustic wind
south pivot
#

I am very much looking forward to these boards

#

Its worth noting that the vector extensions they implement are based on the older 0.7.1 specification (IIRC) so there may be some compatibility issues down the road

acoustic wind
#

Good point, but the full specification isn't even out yet AFAIK (so beats nothing). 😅

south pivot
#

Very true 🙂

hearty pier
potent echo
#

Noup, very cool to know.

#

I showed this chips on tannewt's show on friday, and the people from electricats made a (spanish) video of live installing a board they got from CN.

potent echo
#

When it rains...

fringe girder
#

Oh that is amazing, I need to get that part ASAP Ive been waiting for something similar

feral dock
#

Neat. I'm unfamiliar with the chip-maker, though. Are they generally well-regarded (having dev kits and documentation) and carried by distributors?

acoustic wind
wanton sphinx
feral dock
#

Excellent, thanks! Looks like they are indeed making a version with 4MB flash incorporated into the chip package too.

young tusk
#

ooooh, c3 has USB device

#

tlsr9 says usb as well

cold umbra
#

Oooh fr****ck, just visited espressif website, and this is what I saw:

📎 image0.jpg
harsh light
potent echo
wild oyster
#

Is there any fun or cool use of riscv for hobbyists?

feral dock
#

Same as any other microcontroller or embedded processor, pretty much. The specifics of the ISA usually doesn't come up in most projects. The neatest RISC-V chip I know of is the GreenWaves GAP8, if you want to play with one that's a little different than normal.

sand gyro
#

Any chance for a 128 core risc v soc in the near future? And whats going on with that micro magic's core running @5ghz

fringe girder
sand gyro
#

@fringe girder thanks thats what i wanted to hear 😆. Seriously??

feral dock
fringe girder
potent echo
lunar coral
#

pine has a bunch of cool stuff

burnt glen
#

Would be nice to see the performance of this board

potent echo
#

@burnt glen It has the same cores as the hifive unleashed, but only two. Some twice the ram, half the core count.

#

I already got myself in line to get one, so I can continue building the slackware-riscv project.

restive ice
#

Has anyone received their ESP32-C3 yet?

feral dock
#

Nope. I am on the list, but no update since December.

restive ice
#

Same

cold umbra
#

Bitluni received some, so they are shipping

#

You just need to wait...

restive ice
#

I figured, I just wasn’t sure who had them yet 🙂

cinder sierra
#

I guess you could say that it always was a bit of a RISC-y proposition.

restive ice
#

Exactly

potent echo
#

Drew got his BeagleV <3.

restive ice
#

Ahhh yisssss

fringe girder
#

Has anyone gotten hands on ESP32-C3 silicon yet? If so, where from

restive ice
#

Not yet

fringe girder
#

Darn, trying to make a oil tank sensor

#

Really wanna give it a spin

restive ice
#

I’m excited for whenever they send them

potent echo
#

Andreas Spiess' next video is going to be about the esp32-c3 ❤️

#

(I hope he doesn't start chewing fondue... like some other people do when showing their c3s 🙂 )

fringe girder
#

Nice, Ill look forward to that. Im going to need to harvest some from a dev board it looks like unless they start selling chips soon 😆

restive ice
#

Might have my C3 this week or weekend

#

There’s a DHL package in my informed delivery app for the post office so fingers crossed

potent echo
#

@fringe girder I say that somebody got a board, and a couple of chips on the package. Let's hope that's the norm and not the exception.

restive ice
#

Hopefully I’ll get mine tomorrow

potent echo
#

Yum, that'll be nice. I'm getting my pine pencil which has a riscv cpu in it, but no c3 yet.

restive ice
#

So all along I thought the DHL package that’s been expected to come would be my C3 dev boards, turns out maybe not. I just got an email in the middle of the night from Espressif that they just sent my C3 board

potent echo
#

Yey, I got tracking as well. (In my case, they are going to Miami first, and then to Costa Rica, so I'll have about a week delay into this party 😦 )

restive ice
#

Did anyone else get a second email from Espressif?

#

It’s says a dev kit so maybe some chip samples 🙂

restive ice
#

It’s the same tracking number, just a different description from the first

cinder sierra
#

I didn't get the attached document in the previous mail.

restive ice
#

Same

#

I thought it would be more but it’s just two pages

young tusk
#

I got a second email. I assume they are only sending one package

restive ice
#

It’s only one package, but I’m wondering if they are sending more than just the dev board or a few chips as well. Like @potent echo mentioned above

cinder sierra
#

Well, mine's supposed to show up today.

young tusk
#

mine comes today 🙂

cinder sierra
restive ice
#

Mine is supposed to be here today as well

#

Looks like tomorrow it is then 🙂

#

It just left Cincinnati, OH an hour and a half ago

#

Which is a solid days trip for me

cinder sierra
#

Cincinnati, OH; a cursed town.

#

Yah, so you get one cute lil' matchbox containing a cute lil' board and the PDF that the second email had but printed out

tropic cosmos
#

Mine's supposed to be here today, but it's below 32F in Dallas. It might be a week since everyone's going to lose their minds

potent echo
#

Did somebody started a C3 PR already? :þ

#

Nice box on the C3.

#

plays the jingle "he has the box" from JHS pedals :)

cinder sierra
#

YEAH! I really like the box.

#

Obv I also like things inexpensive so I can't suggest that Adafruit ought to be sending their boards in matchboxes, but it's still nice.

restive ice
#

We’re there any esp32-C3 chips in the box @cinder sierra ? Or just the dev board?

young tusk
#

@potent echo not that I know of. I'm not planning on doing it anytime soon

cinder sierra
#

Just one dev board.

restive ice
#

Bummer

#

Probably not that big of a deal for you, slight bummer for me

tropic cosmos
#

Though for your sake, I'm sure just a "does my board work?" proof would be good

restive ice
#

Yeah that’s what I’m hoping for

young tusk
restive ice
#

Wow nice

potent echo
#

Mine is in Ohio for some reason... I'll get here. (one hopes)

restive ice
#

Mine was supposed to be delivered yesterday

#

It’s currently sitting in Greensboro NC doing nothing

tropic cosmos
#

I think something got flubbed in my DHL number or something. I haven't been able to track it, and the tracking number seems short at 10 digits :/

#

And now it finds it as a waybill number. 🤷 Apparently it's in Cincinnati now.
"With God as I my witness, I swear I thought turkeys could fly"

restive ice
#

😂

restive ice
#

Yay 😁

fringe girder
#

Woo hoo! Harvesting chips looks like its going to be fun, I got two on the way as well

restive ice
#

Oh nice. The mini module is kind of adorable

restive ice
#

Do we know if an Arduino core has been developed for the C3?

#

I was going to play around with my C3 this weekend

#

Get a familiar with the ESP-IDF

potent echo
#

@restive ice According to the developers, a code that works on S2 should work on C3 just by changing the platform to C3.
(it does not have all the peripherals the S2 has so a cpy port won't be as transparent)