fpga

[ionic spoke]

Reading an #encoder with #fpga. Spanish spoken but English subtitles! I hope you enjoy it.

https://youtu.be/Q1L9VwJKJSo

[plucky helm]

@stark trench what fpga are you using?

[stark trench]

Ice5lp4k, it’s too small to do any 32bit soft cores

[plucky helm]

👍

[stark trench]

I think the smallest 32bit soft core is 8000lut

[plucky helm]

generally the cores aren't the problem because the risc-v compiler handles that bit. its the peripherals that are tougher to support

[stark trench]

There’s also no substantial native usb IP core as far as I am aware for the ICE5LP line

[plucky helm]

I bet it is too small

[stark trench]

Yeah, just 3520LUT

[plucky helm]

I always wanted to treat those smaller lut fpgas as stemma qt devices

I have a mach xo2 board for that

[stark trench]

The hardened I2C makes it a pretty cool candidate

And harden SPI as well

[plucky helm]

yup yup

dual hardened I2C iirc so you can have one be the "bootloader" and other be the user code one

[stark trench]

Yup, pretty nifty all things considered

I’m working on this feather right now

The version I’m waiting for boards for has SPI flash which means it could be a pretty valuable stack up with circuitpython devices if I can develop enough useful examples

[wise roost]

Do you have an i2c peripheral template or going from scratch?

[stark trench]

Lattice provides an I2C template

[stark trench]

I’m looking To gauge interest in the my fpga feather, so I set up a web page to collect interest: https://oakdev.tech

[soft mauve]

@stark trenchIf you wanted a RISC-V core, I believe this one might fit. 🙂 Looks like under 1200 LUTs (but probably not a lot of RAM available, but might be fun). https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md

[west salmon]

Hey folks. I'm still chipping away at learning FPGA and digital circuit design, in between work, renovations, and other projects. I have a few questions for anyone who feels like sharing thoughts:

1. One of my goals is to create some FOSH I3C Basic v1.1.1 (and possibly other protocol) modules that can be mixed and matched to suit an implementation's needs (ex. I3C Target w/ ADC, I3C Controller with SPI<->I3C bridge). As I continue to learn, it's becoming clear that many of the components are pretty simple. The one that I'm not too certain about yet is a command look-up-table for I3C Common Command Codes. I'm mainly a software/Linux guy so, trying to figure out what would be the right "primitive" for such a component. It should be immutable, so, a form of ROM. A bunch of logic gates seems like it might suffer from undue levels of complexity both for implementation and physical creation. What would be the go-to structure for such a thing in the FPGA/ASIC/IC world?

2. I know that it can be a bit of a sensitive topic in some FPGA-centric venues but, what are your thoughts on mature, useable High-Level Synthesis libraries/implementations that are licensed in a friendly manner (actual HLS, not new-school RTL like Amaranth or Chisel? FPGAs have been available on PCI-E cards for the server market for years and even in smartphones. For hobbyists, makers, and small manufacturers, FPGAs for function acceleration seems like a good, low-cost way to extend the functionality and performance for MCUs and SBCs.

3. Talking about Amaranth and Chisel, any thoughts on pros/cons? To me Amaranth being a Python library is a pro but, the fact that must of the UCB RISC-V implementations are in Chisel makes me contemplate diving on there.

[silk verge]

Since FPGAs are often built out of units containing look-up tables, it's not hard to provide ROM-like functionality. It's often more compact and easier to read as well. I went to the trouble of implementing a 7-segment decoder as logic functions, but a ROM-based version would have been short and easy to read. I somewhat suspect (but haven't verified) that the resulting fuse map would be the same either way.

[pallid rain]

This is cool, @stark trench! It would be interesting to compare notes (or war stories) sometime! 🙂

[stark trench]

For sure! I really need to get a blog post together about it

[pallid rain]

Anytime. We did a Feather-format FPGA board a couple of years ago that has done pretty well. SAMD51 and MAX 10 scarcity has made them challenging to manufacture the last 1.5 years. However, we are still able to keep building small lots of them.

[stark trench]

Samd51 is a great companion for the max 10

[glossy void]

Does anyone have experience with efinix fpgas? They’re pretty well stocked and seem to be pretty cost effective.

[stark trench]

I’ve not used them but I’ve heard good things

[karmic forge]

how realistic would it be to have a board in the same kind of footprint and cost as cheaper micro controller, but for a smaller FPGA instead?

[stark trench]

Like an Itsy Bitsy/Pro Micro size board?

[karmic forge]

I was thinking feather, pi zero, stick on a breadboard size

[stark trench]

Oh gotcha

This is an fpga feather I’m making

Has a small 3520 LUT lattice ICE5LP4K on it

Is that like what you’re thinking?

[karmic forge]

yeah, that conversation was part of why I asked, can't remember where on the price list that chip is though

I know there are a bunch of ICE chips in the sub $20 range though

[stark trench]

The ice5lp4k is in the $8 single range

There is a 1K variant that is ~$6 for a single

https://www.mouser.com/ProductDetail/842-ICE5LP4K-SG48ITR

[karmic forge]

yay, reasonable price ... I know the $50-$100 dev boards are reasonably priced for what they are, I just don't want to throw that much at testing the viability of testing the viability of an idea lol

[stark trench]

For this it would be simple enough to set this up with a flash chip that you could program with an off board ft232h programmer

Since ft232h bare chips are back ordered until mar/April next year

[karmic forge]

ooh, it's a not bga lol

[stark trench]

Yeah, QFN is super nice to work with

[karmic forge]

I saw some really cute 4x4 bga chips in the listings

[stark trench]

Yeah, the WLCSP chips are very small and compact

A little bit tricky to work with

[karmic forge]

I bet they'd work brilliantly for making replacement boards for stuff that's impossible to get hold of anymore, like some of the more niche 74 logic chips ... well, maybe not in voltage levels though

[stark trench]

Voltage level translators could help with that

[karmic forge]

yup

[vast moat]

The Tang Nano boards are another option for cheap FPGAs development.

Those use Gowin chips.

[glossy void]

https://www.crowdsupply.com/jungle-elec/fireant is $38 and feather-sized. Not exactly the best FPGA around, either, but these are actually not unobtainium these days, which is rare for FPGAs...

[stark trench]

I was also reminded recent of FoMu which Adafruit has in stock. Not a ton of GPIO but great for getting started

[long bridge]

https://techcrunch.com/2022/09/20/jitx-wants-to-change-the-way-engineers-design-circuit-boards-using-code/

[stark trench]

Making a small test board for trying to do an fpga dev board with an FT2232D as the SPI flash programmer

Still have a bunch of things to put on but so far so good

[stark trench]

progress

[long bridge]

would this scale to high speed applications? Like 32 bytes per clock

[stark trench]

It might, just depends on how good your initial synthesis is and whatnot

[light quarry]

Hey guys I am a rookie . I am interested in fpga .

Any resources pls.

To get start with.

[stark trench]

Highly suggest checking out Shawn Hymel’s Introduction to FPGA videos

ICE Stick or IceBreaker FPGA boards are great entry points

[silk verge]

IceStudio is a fairly good way to get started. Also look at the 8bitplayground web site

oops, misremembered, it's 8bitworkshop.com and offers a nice FPGA simulator

[stark trench]

Oh and EDAPlayground.com as well

[silk verge]

Oh, I didn't know about that one, thanks!

[plucky helm]

there are some feather ice40 up5k in production from @wet planknick on twitter: https://twitter.com/whatnick/status/1588769414895534080

Tisham Dhar (@whatnick)

40 ice40 Feathers are now in the over at @PCBWayOfficial , looking forward to them being available on the store. #fpga #Electronics

Twitter · Nov 5, 2022, 5:45 AM

[stark trench]

The UP5K can host that risc-v soft usb core like the FoMu can, right?

[plucky helm]

it can but this feather design doesn't connect the usb lines to the fpga afaik

[stark trench]

Ah okay, just uses a flash chip for storing the program i imagine

[plucky helm]

¯_(ツ)_/¯

[stark trench]

Putting my SystemVerilog pants back on to write a test bench for my 8-bit CPU. Brings back good memories

[gloomy kettle]

Definitely way beyond my skills, but an interesting book.

[molten hemlock]

Wow. I haven't done chip design in something like 30 years (back when we used stone knives and bear skins😄). I can only imagine the learning curve I'd need to catch up with the latest tech.

[stark trench]

You should look at the next TinyTapeOut. You can design a chip with the Wokwi drag and drop editor or use an HDL.

https://tinytapeout.com/

[molten hemlock]

I'm definitely more comfortable with schematics than HDL. Been ages since I used VHDL. I'll check it out. Thanks!

[stark trench]

There’s also a discord with help channels. You can do VHDL, Verilog, Chisel, Amaranth(spelling might be off on this).

[sand finch]

How much does getting custom silicon made cost?

[mellow socket]

i dont know about a custom design, but according to what i've been told at university you can buy some FPGA test boards for ~200$, and you can "program" them with your VHDL designs.... as many times as you want (?)

for complex designs it's most likely a pain, but i actually enjoyed making basic stuff with VHDL
we also used a software(was it Vivado HLS?) that took your C function and convert it to a hardware design to implement it, and you didnt have to make almost anything, just setting a couple of options if you wanted to, i cant even begin to imagine how hard coding that tool has been

[stark trench]

These open source eFabless shuttles are paid for by Google

And other sponsors. Tiny TapeOut is $100

Pretty low barrier

[sand finch]

Oh wow

[zealous veldt]

Do you think someone could implement https://imihajlov.tk/blog/posts/eth-to-spi/ in an FPGA or GF180MCU/SKY130?

[stark trench]

Probably on GF180 or SKY130

There’s probably a better Ethernet implementation for FPGA

[tropic cipher]

are there any SoCs like the Zynq that are accessible to hobbyists?

[glossy void]

Not at the moment, most hobbyist projects I know of tend to pair an fpga with a microcontroller separately, kinda like spartan edge accelerator? Zynq is probably as accessible as you can get, as a Cora z7 dev board is around 150

For smaller projects, a soft core processor might be the way to go?

[vast moat]

On the smaller scale there's the QuickLogic EOS S3, which is available in a Feather form factor. It's similar to a Zynq in that it's a MCU plus FPGA fabric in one chip, plus some extra DSP stuff.

[stark trench]

I thought the Zynq was an A7 CPU not an MCU?

You can run Debian on a Zynq chip

The quicklogic chip is a good suggestion though. I’ve always wanted to try one

[vast moat]

Yes, you're correct, I meant "similar" in terms of being a hard processor plus FPGA, but if you're looking for a Linux system FPGA SoC, the Zynq is about the lowest end you can get already.

[stark trench]

Yeah, at $150 you’re lucky to get an A9 (thought it was an A7)

I wish there were more low end MCU+FPGA options

I had an idea for an M0+ and a lattice ice40 board. I got the PCBs but never assembled them

[vast moat]

Same. Others I'm aware of include the SmartFusion 2 and one of the GOWIN variants.

[stark trench]

I might try to mix the RP2040 and an Ice40 and set up the RP2040 to do parallel data bus capabilities with the fpga

Do some serious off chip DSP stuff

[tropic cipher]

fwiw at least the one I’ve used has a couple R5s too. But yeah running Linux + FPGA is the part I find most interesting

[stark trench]

Yeah, the MPSoC and RFSoC have small RF controllers

Getting into the $1000+ ultrascale SoCs

[vast moat]

Those are fun chips. I used them on a previous project (for work, not personal).

[glossy void]

Minimal Linux builds could run on FPGA soft cores IIRC

Even Linux feels like it comes in tiers these days.

[stark trench]

We use MPSoC where I work. Nothing like not wanting to break the FPGA dev board that costs almost a years salary 🙂

[tropic cipher]

Yeah we use MPSoCs too. I usually do software stuff but I thought I’d branch out and try and learn enough of Vivado to make the SFP+s show up in Linux

[stark trench]

But yeah, an RP2040 with a small <10k LUT FPGA would be fun

Especially with PIO on the RP2040.

[tropic cipher]

How many LUTs does it take to implement a Linux capable soft core

[stark trench]

3000

You can run muLinux on a M4

[glossy void]

I’m surprised nobody’s built tiny fpga feather wings or something. Spartan edge accelerator looked pretty cool…

[glossy void]

Depends on whose LUTs we’re talking. Different FPGAs use different size LUTs haha

[stark trench]

I made a feather

[glossy void]

Oh right, that was a thing.

[stark trench]

Still working on the final version if I could just get FT232HQ

[glossy void]

I was thinking something that stacked on an esp32 or rp2040 feather, but that’s probably still doable

[stark trench]

Oh yeah, definitely

I have one around here somewhere that I’ll eventually reorder

[glossy void]

One particular example: https://github.com/YosysHQ/picorv32

[stark trench]

this one doesn't require an FT232HQ, just needs a button, regulators, and the FPGA. and a feather to program it of course

you get, all the GPIO

is this what you were thinking @glossy void

[glossy void]

Yes

That is neat.

[stark trench]

I should order the PCB for it, it's only like $9 from OSHPark

then i just need to get up enough money to order the 1.2V and 2.5V LDOs, and the FPGA

might be able to harvest an FPGA from one of my other boards.

alrighty, ordered. thanks for helping me remember I had this board done lol

[stark trench]

if you're interest in one, I could send you one. I just need to make sure the design works first. If it does, I can let you know cost.

[glossy void]

If only I had the time to develop on it…

Maybe in the future.

[stark trench]

lol, I know that feeling

[glossy void]

Gotta get through my current FPGA coursework first haha

[stark trench]

I'm having to work OT to cover the basics right now while my wife goes to school, not to mention I'm trying to do 2 grad classes lol...

so my tinker time is limited

[glossy void]

Oh man that is tough

Hang in there

[stark trench]

Assuming this board works, I’m planning to put a few up on my Tindie shop if anyone is interested.

[stark trench]

I’ll share a link when I have a product page up

[stark trench]

I think I’m going to also make an optional programming feather board with a 2MB flash chip and an FT232H to program the flash. Maybe do a set of jumpers to either use flash or program the fpga directly.

[stark trench]

It lives!

The final prototype, it works

I am really pushing the limits on recycling chip’s between prototypes though lol

The only new parts on this are the SPI flash, the FPGA (I think I cooked the last one) and the RGB LED

[stark trench]

Now to wait until April to get more FTDI chips

[glossy void]

Phew that's not a cheap board though

[stark trench]

Yeah, cost to make it worth while with recent price increases in parts is just.. insane

Orange crab went up $60 in cost for their latest run

$159 vs the $99 it used to be

I’m trying to ease the pain with a preorder pricing but it’s still.. a lot considering if I could have got the parts 6 months ago it would have been $10-15 cheaper than the preorder pricing

[stark trench]

Just curious from your perspective, what is a comfortable price point?

[glossy void]

I haven't really done a thorough comparison of FPGA features, but I'm currently looking in the 30-50 range to start

TinyFPGA and FireAnt come to mind atm

[atomic leaf]

Hmm can you reply my question in #general-chat

[stark trench]

Gotcha.. yeah hard to compete with those prices.

My BOM is like.. $28

[glossy void]

Lol I don't think you should

[stark trench]

But I can’t buy at the quantity that one bit squared can lol

[glossy void]

I should be saving up some money to get something nice when I need it

[stark trench]

If I could buy full reels of parts, yeah, I could definitely get the BOM down to close to $15, then a $45 price point would be easier

I don’t have $15k laying around though lol..

Im considering a crowdsupply campaign though

[opal bramble]

are you planning to make this open hardware?

[stark trench]

yeah, I'm working on documentation and everything currently

[opal bramble]

cool. very nice board.

[stark trench]

thanks! It's been a long time coming with this parts shortage

[opal bramble]

The guys at vision.ai developed a board with a pico+ice40

[stark trench]

I think I may have seen that

do you mean the RP2040 or the ESP32 D4 Pico?

[opal bramble]

rp2040 + ice40up5k

same core motivation... chip shortage and a way to replace ftdi

for some specific use cases

[stark trench]

ah yeah, I've got a samd21 SoF (System on a feather) with an ICE5LP4K as well I need to circle back to

ICE5LP4K can be programmed over SPI so it's a prime candidate for any micro that can open an SD card and push hex files.

I might make one with an RP2040 too for the feather format too

[opal bramble]

i have several feathers ("master" boards) so your board could have several applications.

[stark trench]

I have an ICE Featherwing too with all the GPIO broken out in the works

waiting on PCB currently

designed to be a cheap way to add an FPGA to your setup

[opal bramble]

cool, all i can say a lot of people have though about this (1% inspiration) and 99% transpiration (routing it , going to all the fab process or getting a stinky blink LED to glow).

nice work.

[stark trench]

thanks, I thoroughly enjoy the process

[opal bramble]

i will buy one...

[stark trench]

someone did an RP2040 and a UP5K game system

https://github.com/Wren6991/PicoStation3D

[opal bramble]

I've seen some.

with different use cases.

[stark trench]

it's pretty cool to see all the different options

[opal bramble]

but when it's a open hardware there more options to customize it and contribute back.

https://github.com/tinyvision-ai-inc/pico-ice

again... that might not fit all use cases.

I'm a newbie

[stark trench]

yeah, thankfully there's lots of options coming out

I'm using the FTDI chip because i'm attempting to maintain compatibility with the Lattice tools for programming, but I am exploring more low cost options like SAMD21 which are coming back in stock and also the RP2040 due to it's prolific availability and large FLASH storage options

and the featherwing of course to be the cheapest option.

[opal bramble]

if we could only emulate MPSSE (FT232H emulation) in a mcu

without all the legal stuff

[stark trench]

there is some emulation being explored on WCH chips

[opal bramble]

yep

[stark trench]

but at the moment it's dubious

[opal bramble]

i think that's being done for the icebraker

[stark trench]

I also am hesitant to use WCH chips because i'm just not sure if WCH will be around long term. the industry already struggles to have enough people to run the industry that we have.

[opal bramble]

i think that basic emulation is done for CH32V307

[stark trench]

yeah, I had seen that

I may try it out on a test run

the biggest thing that I don't care for with the FT232H is that it's huge. it and it's components take up half the space on a feather.

I've slimmed down as many components on it as I can and still allow it to function reliably

but it's still a lot

the whole IcyBlue feather is done on two layers too which is kind of a miracle some days.

[opal bramble]

yeah. I PM you... as all of this might be adding noise to the fgpa channel

[stark trench]

nah, it's on topic

plus this channel is lightly trafficked so it's not an issue. mostly just me posting stuff lol

[mellow socket]

and people like me can still read the conv and just maybe learn a little bit

[stark trench]

I’m glad you’ve been able to learn even just a little. My desire is to always help as much as I can and hopefully learn myself along the way

[mellow socket]

i've even made some basic FPGA things at university, but i didn't know (some) they can be configured over SPI, i thought a MCU+FPGA PCB would need a computer hooked into it

i guess it doesnt make much of a difference as you still need some tooling on the PC to generate the binary(or whatever it is) file to program it, but having a specialized piece of hardware is always a cool thing

last thing i made was a module to compute inverse square root of a 3D vector, but it was "cheating" as we used a Vivado tool that made the FPGA design based on some C code (definitely an amazing piece of engineering)

the hardest i've written myself was a state machine iirc

[stark trench]

My thought was you always needed expensive tools but developing this board has show that isn’t the case. Hoping to be one of the small voices in the crowd moving open hardware forward

My digital systems design class was all vhdl based, I didn’t even know Vivado could convert C code into a bitstream

[mellow socket]

if im not mistaken, a classmate bought a similar board to the one we were using for like 60€ with buttons and LEDs and some other stuff to test
but to be honest, i dont recall if it was a FPGA-based thing or a weird-MCU-based for a subject where we wrote some assembly

[stark trench]

Probably a Spartan or Atrix7 based board

[mellow socket]

im pretty sure we had spartans at class, Zynq7 something could it be?

[stark trench]

Which honestly, I think they use FT232H based programming too

Actually looks like Diligent makes their own USB-JTAG interface (likely another FPGA) to program the Artix7

Digilent Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users https://a.co/d/9XEO2zj

Like this one?

[mellow socket]

i laughed a lot on the 1st class, teacher is a great guy
he proceeds to give an almost 2 hour explanation on how to use Vivado HLS to convert C into a hardware design, load the design into the board, and write some code to use the peripheral we just made from the main CPU, then he says something like "now you can gladly tell your parents you made an LED blink" 🤣

[mellow socket]

i honestly dont remember

[stark trench]

hahaha, nice

[opal bramble]

the "good" aspect of FTDI is their throughput. Based on my understanding, a current MCU implementation cannot fast enough (right now)

[stark trench]

yeah, like 2 seconds to program the SPI flash on the IcyBlue for the FTDI chip

[stark trench]

The first feather wing for the IcyBlue FPGA

A play on the classic digital design lab of making a traffic light controller.

I wanted it to kind of look like a road

ah whoops forgot some labels

much better 🙂

[silk verge]

Encouraging early results in my notion of implementing DDS in an FPGA using fractional division. fctr is the fractional division counter, you can see how it has one more clock occasionally like on the right, bctr is an ordinary binary counter (for comparison). fled is the fractional counter LED output and bled is the binary counter LED output.

[silk verge]

Adding a sine lookup table (a quarter of the wave, the rest is built by mirroring that piece in various axes), the idea is to take the constructed value ("wave" in this picture) and squirt it out an SPI port to an outboard DAC chip

[plucky helm]

@silk verge what produced that output visualization?

[silk verge]

8bitworkshop.com has a nice FPGA simulator that also does a variety of useful visualizations

[stark trench]

The IcyBlue feather first round is finished in assembly, smoke testing, and programming testing. Five only going to early supporters!

[sand finch]

Glad all of the first batch works!

[stark trench]

Curious if anyone would be interested in an open source core developer board. It would have a good bit of SPI flash (8MB more than likely), 32KB (256kbit) SRAM, some status LEDs, RGB LED for fun, some status LEDs for output and probably a second USB port.

[sand finch]

I have theoretical interest, but FPGAs are currently far from my reach

[stark trench]

https://tenor.com/view/near-far-wherever-you-are-emma-heesters-my-heart-will-go-on-song-everywhere-you-are-anywhere-you-are-gif-18621629

[sand finch]

heh

[jaunty bone]

Does icy40 integrate hard processor on it?

[stark trench]

no, but there are soft cores available that can run on them

[jaunty bone]

Aww

[stark trench]

1BitSquared is working on an Itsy Bitsy FPGA that runs a small RISC-V soft core

it has the slight upgrade UP5K to do that.

and the UP5K is pin compatible with the ICE5LP4K I'm using which means just a simple change to the silk and there's a bigger FPGA available without really any major changes.

[jaunty bone]

My idea was if it was hard processor + FPGA fabric it could have really nice accelerator applications

[stark trench]

I am working on a board that combines the RP2040 and an ICE40

[jaunty bone]

Idk if there is any hls software yet but that might be good for edge ai or sth

[stark trench]

in the feather format too

it's a bit rough right now, i've got to change some pin assignments around

[jaunty bone]

My idea was to use strength of both words with tight integration

Maybe open up possibilities for open source hls applications

[stark trench]

I see the RP2040 as a great companion because of the PIO capabilities. you could have near real time transfer between the FPGA and the RP2040

[jaunty bone]

By tight integration i meant like custom instructions or custom inputs to instruction alu or data injection to data path

[stark trench]

I’ve also got this featherwing FPGA

[jaunty bone]

Maybe those probably done easier and more efficiently with soft core

[stark trench]

Perhaps, there’s some applications to come as microcontrollers are getting more featured

[jaunty bone]

Good luck on your journey. I wanted to share my thoughts and see your vision

[stark trench]

I want to make them more accessible so people can see the potential of FPGA in their projects

I am attempting to highlight those capabilities in this CrowdSupply campaign. Emphasizing things like off chip integer DSP which can be particularly fast on FPGA

[jaunty bone]

I own a very powerful FPGA but still unable to find anything to use it with

[stark trench]

Build an SDR

Hack together a satellite communication hub

[jaunty bone]

Other than replicate my digital lecture projects which was the most fun and enthusiastic thing I've done for a long time

[stark trench]

The blank canvas of FPGA make them hard

[jaunty bone]

You can make everything, but what do you do that can't be done otherwise?

[stark trench]

We live in a world where we expect electronics to just be one thing. When you tell someone they can make something do most anything they can think of, it breaks them.

[jaunty bone]

Can't really answer this question.

I hope I can some day soon because next year is my thesis 😅

[stark trench]

Well, the point of doing it ourselves is because there’s a chance we could it better

But actually realizing what we want on an fpga can be difficult

I’m hoping to make it easier

Well, not easier but more accessible

Easier is a misnomer

[sand finch]

Is CrowdSupply kinda like Kickstarter, where people fund you and then get one of the thing? And is this FPGA Feather something that I can use with 0 FPGA experience? Lol

[stark trench]

CrowdSupply is like kickstarter though I think you can commit to more than one if you want. This feather will be hopefully accessible to people with 0 experience

I’ll be working on tutorials, videos, examples, etc..

[sand finch]

I’ve known about FPGAs and the fact they can be super flexible… but never had a project where someone said “you should consider an FPGA instead of an MCU”. And I don’t want to have one just for the sake of having one XD I have enough things I bought without a reason

[stark trench]

They’re worth knowing how to use in the very least. There’s some good niche applications for them where microcontrollers are not as well suited.

One add on feather wing I’m working on is a traffic light control board which will help with teaching state machines and sequential logic design, and such.

[sand finch]

They can do certain specific tasks much much more quickly than an MCU, right? Kinda like how a GPU has limited instruction sets compared to a CPU but can do some operations much faster since it had many more cores/pipelines?

[stark trench]

Right, you can do integer DSP work for instance

[sand finch]

Ohhh, nice

[stark trench]

And doing it off chip makes it so you can utilize your MCU more fully for the tasks that it’s suited for like data collection

Integer DSP will be a more advanced example that I’ll be working on

[sand finch]

Wait, what’s integer DSP? My brain for some reason thought you meant Deep Packet Inspection

[stark trench]

Digital Signal Processing

The ICE5LP4K has 4 DSP blocks

16bit multiplication with 32Bit accumulators

[sand finch]

Ah

[stark trench]

Only downside of the 4K model is it doesn’t have an embedded PWM IP

So you have to make your own PWM IP

[stark trench]

And now we have examples to run on the iCE5LP4K FPGA 😄 https://github.com/skerr92/ice5lp4k_examples

forked from an iCE40HX8K examples repository and modified to build for the iCE5LP4k 🙂

[hollow jacinth]

an FPGA can do things in parallel and because they are arrays of gates, you can essentially emulate chips, if your FPGA is big enough

oops I meant to respond to the one above that, sorry

[glossy void]

I guess it’s probably simpler to think of a microcontroller being used to represent a sequence of instructions, while an fpga is used to represent a physical logic circuit. There is a lot of overlap as microcontrollers get faster and fpgas get increased access to digital peripherals, but traditionally that’s the distinction between the two.

[scenic marsh]

I have really been getting into understanding system architecture. I was thinking about building out a limited 286 computer. I want to use a physical 286 processor and implement the rest in an FPGA. Is there anything that would make this unreasonably hard for a newcomer?

[stark trench]

There’s a slight learning curve for HDL languages, has your learning path had you do anything with Verilog or VHDL?

[scenic marsh]

I am a 100% noob as far as HDL languages go. I have good beginners level understanding of digital circuits. I have been researching which (verilog or VHDL) to start with.

[stark trench]

If you’re familiar with C/C++, Verilog tends to be a good place to start

You might start with a small FPGA and work through some examples or free courses to build up confidence and knowledge

Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute https://a.co/d/8NzaYAl

This book has come highly recommended to me in the past

A little pricy, but springer published books tend to be very thorough

[scenic marsh]

Ok, that makes sense. Is verilog compatible across diffren FPGAs?

[stark trench]

Yeah

Lattice, AMD/Xilinx, Cyclone, and Intel FPGA all support it

[scenic marsh]

Awesome

[stark trench]

Along with other brands too

[scenic marsh]

Yea I think verilog will be a good start for me as even though I do not use C a lot I understand it pretty well

Thank you for the info.

[stark trench]

Best of luck 🙂 I’m looking forward to seeing your progress

[stark trench]

oldie but goodie

[gloomy kettle]

There's another that seems well recommended.

Not much use to me though, well above my skills. Lol

[stark trench]

some people (like myself) do well with going about things the absolute hardest way lol

[gloomy kettle]

I can get the principles of it, just not the practical.. I don't have a codey-braining thing.

[silk verge]

You have given me an evil idea. The grandaddy of all the X86 CPUs is the Intel 8008, which was crammed into an 18-pin package, so it multiplexes its address, data, and I/O buses on the same pins. I had been musing on how best to unpack that information, and an FPGA would be a one-chip solution.

[scenic marsh]

I've had some very similar thoughts about my 8088.

Making the sockets for the 286s is kind of a PITA

[wise ingot]

Hello! I just realized this channel is a thing!

[wise ingot]

https://hdlbits.01xz.net/ is pretty good as far as verilog tutorials go

[silk verge]

i8008 socket is pretty easy.

This isn't the original, it's the 8008-1, which can manage 800kHz

[scenic marsh]

That is impressively small.

I'm looking at these breakout boards on ebay I'm leaning towards the Cyclonell as I need 40ish IO pins for the processor and then some more for external components.

[silk verge]

I was never able to get Quartus to run, so I've pretty much overlooked Xilinx chips

[scenic marsh]

I might just stay on brand with something that has some support with https://www.adafruit.com/product/451

[glossy void]

Isn't Quartus Altera? Xilinx uses Vivado.

[silk verge]

I never got Vivado to work either.

[glossy void]

Oh, rip.

It's a real hefty suite.

[silk verge]

It was a pleasant surprise when tannewt pointed me to modern open source FPGA tools. Installing IceStudio/fomu/apio is easy and quick, and supports modern operating systems.

[wise ingot]

FYI, That's what I do before running the installer to get vivado to install on debian-based systems: https://support.xilinx.com/s/article/63794?language=en_US

I know you've found something that works, but I just wanted to let you know in case you need, for some reason, to try this again in the future

[silk verge]

That article came out after I gave up on the Vivado Linux port as a bad job. Previously, it had tried (and failed) to support a big complicated GUI interface that apparently only worked with one particular graphics configuration which I didn't have. Seeing ncurses in the prerequisites implies they may have moved to a CLI version which would be a much simpler approach.

[wise ingot]

It is possible to interface with it both via the GUI, and via a CLI. However, the primary interface mode remains GUI-based.

https://docs.xilinx.com/r/en-US/ug911-vivado-migration/Equivalent-Makefile-Used-in-the-Vivado-Design-Suite ... shows how to interface with it using Makefiles

I have no idea if they've done something weird that prevents it from working if it can't instantiate the GUI though

...Hang on, I can actually test that

Yeah, it works just fine from an ssh shell w/o X forwarding, so it shouldn't need the GUI

[scenic marsh]

Are there any distinct drawbacks to using the Altera Cyclone IV for someone that is new to FPGA? As far as modern tooling and support? I understand it's a bit older.

[stark trench]

I don’t believe so. A majority of Verilog and VHDL is the same as it was back when the IV came out.

Most anything you do on it should work on most other platforms

[wise ingot]

As long as it's supported by the latest versions of the tooling, you should be fine

(and even be able to use the latest systemverilog/vhdl features supported by said tooling, if you want to do so!)

[stark trench]

But even then, using old tooling is still very plausible

I wish yosys supported SV 😦

[wise ingot]

It does, as long as you pay

[stark trench]

?

[wise ingot]

https://www.yosyshq.com/tabby-cad-datasheet

The subscription would only be attractive to engineering companies, but, worth knowing it's an option

(and probably cheaper than many commercial EDA suites, especially if you want to do formal)

[stark trench]

Yeah

I guess they have to financially support their efforts

Which makes sense since the world doesn’t run on high fives and ramen bowls

Would be cooler if it did though

[wise ingot]

They also have to license an external front-end for this

(verific)

[stark trench]

Yeah

https://github.com/antmicro/yosys-systemverilog

I did find this

[wise ingot]

huh. I wonder how well it supports SVA

[stark trench]

🤷‍♂️

[wise ingot]

FYI, vanilla yosys does support a small subset of SV. And this project seems to get at least some use within the community:
https://github.com/zachjs/sv2v

I also found this press release regarding the project you linked to
https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/

[stark trench]

Interesting

[wise ingot]

Which SV features do you most frequently use?

[stark trench]

Personally, I like interfaces and logic data types

[wise ingot]

Who doesn't? (Especially logic datatypes)

I like SVA because formal verification and would like to look into the more OOP stuff to use with UVM (systematic functional verification)

[stark trench]

Yup

[wise ingot]

Vivado seems to have precompiled UVM, so it's a matter of finding a decent book/tutorial/whatever

Though admittedly I'm probably one of the few people working with FPGAs who are obsessed enough with verification to want to learn formal

(outside of probably medical applications or designs that will eventually be ported to ASIC-land)

[wise ingot]

So, I've got this Cmod a7-35t. Their sample XDC does not include any input/output delay constraints (set_output_delay/set_input_delay). I have no knowledge or access to their board designs. Am I out of luck, or are there any sensible values I could input?

(say, 20% of the clock cycle available for IO, which is the default for openlane)

I guess I could contact digilent about this. Any suggestions?

I essentially only care about the UART

[wise ingot]

The board uses the FT2232H UART. I've been trying to find the timing characteristics for the TXD and RXD pins in the datasheet, but, unless I've been missing something obvious, I haven't found anything!

https://eu.mouser.com/datasheet/2/163/DS_FT2232H-1621240.pdf this is the datasheet I'm using

[vast moat]

I'm not really sure what information you're looking for. Are you concerned about rise/fall times on the UART lines?

[wise ingot]

I'm looking for the setup and hold times of the lines, as well as their output delays

[vast moat]

So I don't reeeeeally understand. UART is asynchronous, not clocked, so there's not really any edge that you'd be able to measure setup and hold times against. And output delays would be also kind of meaningless... the delay between receiving a USB packet and the pin changing?

[wise ingot]

You know what? You're actually right.

I managed to completely forget about this 🙃

Thanks!

[vast moat]

LOL, cool...

[wise ingot]

Yeah, I got some tunnel vision while specifying the timing constraints

[wise roost]

https://youtube.com/live/pt7NDWvfDv0

[scenic marsh]

It's so little!! STEP-MX02

[glad bough]

thoughts on the arty s7 50 spartan 7?

[left steeple]

I see is available in china only? How'd you procure it?

[stark trench]

Aliexpress?

Oh wait Tindie says it’ll ship to the US https://www.tindie.com/products/evoinmotion/fpga-development-board-step-mxo2/

[scenic marsh]

https://www.ebay.com/itm/143781552483

[left steeple]

Thanks 😄

[wise ingot]

@gloomy kettle I flicked through the preview of this in google books, and it felt genuinely fresh and engaging. I encourage you to take a look at it if you're ever interested in FPGAs:

http://pages.hmc.edu/harris/ddca/ddcarv.html

(this stray ping courtesy of you sharing your ancient FPGA book the other month, and my random memory for these kinds of things)

[gloomy kettle]

I would be interested, but there's something of a skill issue involved. 😅

[wise ingot]

I still encourage you to take a look :)

[gloomy kettle]

Certainly.

Just got a lot on my plate right now, including trying to get into Kubernetes.

[wise ingot]

Sadly, I don't have anything to recommend for that

[gloomy kettle]

Just going to throw Rancher Harvester on my server box and see where that leads me. 🙂

[wise ingot]

Yeah, trial by fire is probably the only way when it comes to kube thing

*things, but "kube thing" is a hilarious typo and I'm keeping it

[gloomy kettle]

Checks out. 😁 👍

But, yeah... I'm not doing anything serious with it.
I'll just get Nginx/PHP + SQL running.. Host my own WordPress site. 🙂

[oblique rivet]

Kubernetes is awesome when it works and infuriating when it doesn’t. I swear its error messages are some of the most unhelpful things around

[gloomy kettle]

It's ok... I've worked on Windows. 😛

[wise ingot]

Kube is massive overkill for that ;P

[gloomy kettle]

For sure, but it's also something of an industry standard...
What I'm hosting on it doesn't matter so much, just learning how to build it all.

[wise ingot]

Makes sense

We need a help-with-kubernetes channel so that you can share your little adventure

Or you could setup a good old block. I miss reading those

[gloomy kettle]

Video blog on YT. 🙂

[wise ingot]

Honestly, I miss written blogs

[gloomy kettle]

Yeah, but I'd need a website to put it on. 😛

[wise ingot]

I mean, blogspot (!) is still a thing

[gloomy kettle]

Ohh, I don't do 3rd party hosting. 😄

[wise ingot]

That totally makes sense. I'm still surprised *.blogspot.com URLs resolve after all those years

[gloomy kettle]

lol

I used to have a blog on Geocities and Netfirms, way back when...

Back when I could be bothered to write really bad HTML. 😛

[wise ingot]

these days you can write markdown and have a static site generator do all the heavy lifting

[gloomy kettle]

I think WordPress will be better for me.

Having a prebuilt site allows me to focus on the SysAdmin things instead.

[wise ingot]

wordpress is more of a netsec minefield than serving a bunch of static html though

[gloomy kettle]

All the more fun. 🤪

I still have my old docs and cheatsheets, full of tricks.

[wise ingot]

I hope you'll enjoy the project! Feel free to share updates over at #general-chat

[wise ingot]

https://www.colognechip.com/programmable-logic/gatemate/ 🤔

[stark trench]

Looks like a nice chip

I wonder if the tool chain is open source

[wise ingot]

IIRC partially so. I think the par is closed-source

[stark trench]

Ah

0.8mm BGA is a solid 6L design

Especially with ddr support

[wise ingot]

Yeah, looks like toolchain is yosys except for the pnr which is their own design
https://www.colognechip.com/docs/ug1002-toolchain-install-latest.pdf

[stark trench]

Oh nice

[wise ingot]

6L = 6 Layers, right

?

[stark trench]

Yeah

[wise ingot]

Apparently olimex is building a devboard

[stark trench]

👀

[wise ingot]

https://twitter.com/Olimex/status/1653315891876986884

OLIMEX Ltd (@Olimex)

Guess what new OSHW board is cooking at Olimex? CologneMateA1 is 20K CPE and 5Gbps SerDes and Spartan7 like performance, but comes with completely open source toolchain #fpga #colognematea1 #oshw

Likes

147

Twitter · May 2, 2023, 8:30 AM

[stark trench]

I want to do things the hard way and make my own dev board lol

[wise ingot]

I don't have The Skills[TM]

Though starting with a 6-layer design would be very on-brand for me xD

Jokes aside, I'd get a devboard if it were inexpensive enough

Mainly for the curiosity factor, plus, y'know, European chip (design, dunno where their fab is)

[stark trench]

Yeah, definitely understand the curiosity point

[wise ingot]

got any ideas for whenever the next openmpw lottery comes?

[stark trench]

Trying to finish up my CPU design testing

[wise ingot]

I'm still learning uvm. It's kinda hard to do it at a satisfactory pace, given how I've got rl obligations to fulfill 😅

kinda irrelevant for openmpw though, because systemverilog

[stark trench]

Totally understand the obligations part lol

My schedule changed up so now I have to commute 😥

[wise ingot]

Hope it at least means better opportunities for ya

[umbral seal]

Got myself a Step FPGA board too. Dunno when I'll tinker with it but I'm excited. Also came with tons of headers. Lol.

[wise ingot]

Enjoy! To be able to get started with FPGAs, you'll need to know some fundamentals of digital design and a hardware description language. As far as fundamentals of digital design go, the textbooks are quite expensive, so I'd recommend going to your local library and checking out whichever introductory one they have. Anything is fine, since these days the internet can help answer a lot of questions. If you need to buy, I recommend going on google books and checking out previews to see which one better fits your learning style. You will also need to learn a hardware description language to be able to express your circuits in code. Many digital design textbooks cover both, and I personally recommend verilog; https://hdlbits.01xz.net/wiki/Step_one is a good tutorial.

Most people learn both at the same time

[umbral seal]

Thanks for the pointers. Lurking here finally got me to give FPGAs a shot, though getting started on learning materials does seem harder at a glance. I've seen verilog in quite a lot of places I checked and the language is easy to follow so I'll start with that.

[wise ingot]

Although I haven't checked it out myself, many people have sang the praises of https://www.nand2tetris.org/ for learning digital design. Another good resource is https://nandland.com/.

[silk verge]

The book "Designing Game Hardware in Verilog" is pretty accessible, and the 8bitworkshop.com website it points to has a nice FPGA simulator, and is free to use.

[wise ingot]

Thinking about it now, getting started with FPGAs is kind of non-trivial, isn't it...?

(And I feel "kind of non-trivial" may be an understatement)

[glossy void]

It is not at all trivial. Most general programming lessons start with your typical “hello world” but it doesn’t really apply in the context of fpgas.

[wise ingot]

Yeah, it's easy to forget when it's been some time. I am not going to claim to even remotely be an expert, but I literally had nothing to suggest here aside from "learn digital design first"

Perhaps high-level synthesis (or some of the newer HDLs, like amaranth or spinalhdl) makes it easier? I wouldn't know, I have never used it.

(If anyone has, feel free to chime in! I'm curious too)

[wise ingot]

There's also this course by the linux foundation, but it teaches the (admittedly non-standard) translation-level verilog:
https://training.linuxfoundation.org/training/building-a-riscv-cpu-core-lfd111x/

[stark trench]

While we don’t get hello world, we certainly get blink 🙂 which is equally as inspiring

[wise ingot]

Blink is the hello world for most microcontroller things

But, unlike in MCU-land, understanding why your blink did what it did requires more effort

Though TBF this is because it requires one to consider a level of abstraction below that of a CPU running code

@stark trench , I think an FPGA blink tutorial that actually explains the underlying elements (flip-flop, adder, comparator) at a high level, would be a nice pack-in with your FPGA boards

[stark trench]

I was talking about button input triggers led to light up

But yeah, a good breakdown would end up being helpful

[wise ingot]

Yeah, that's definitely easier to understand

[silk verge]

I remember my first FPGA blink. 25MHz clock in, a whole string of dividers, output to LED pin.

[wise ingot]

In mine, I had just used a large enough counter and changed the LED status when it overflowed

I think my clock in was about 25MHz too EDIT: Checked it, my board at the time had a 32MHz clock, which, for the purposes of blink, I had just piped into my design

[bleak osprey]

what's interesting with that FPGA is they specifically call out it is able to use on a 4 layer board

[wise ingot]

No worries, I can't do a 4-layer board either :P

[bleak osprey]

It is cheaper to have mistakes : D

[wise ingot]

That's certainly right :P

[silk verge]

That's kind of impressive for a BGA package. I've done 4-layer boards before, they're not that big a deal.

There were ... other reasons it was expensive to have mistakes with those boards.

[stark trench]

Lattice Avant-E chips are available for order on Digi-Key and the cheapest on is $200 🙂

https://www.digikey.com/en/products/detail/LAV-AT-200E-1LBG484C/18997128

Supports even DDR5!

Wow, really cool.

https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/FPGA-DS-02107-0-73-Avant-Platform-DataSheet-Overview.ashx?document_id=53699

That’s the advanced datasheet

(Advanced being that released ahead of launch I guess?)

One cool feature I’m seeing is the HPIO (High Performance I/O) and being able to configure for a bunch of different RF front ends.

[vast moat]

Nice, thanks for the info! 25G serdes, sweet...

[bleak osprey]

good luck trying to use those their high speed IO that you need to purchase their IP for a couple thousand to use it.

[stark trench]

Yeah… until Yosys reverse engineers it and includes it in their oss-cad-suite lol

[stark trench]

It is a midscale commercial FPGA so it’s kind of expected that things would be license locked

Until someone reverse engineers it of course

[silk verge]

That just doesn't make sense to me - do they want to sell chips or not?

[stark trench]

Lattice seems to be far more open to individual use licensing though

[wise ingot]

Xilinx is too, as long as you want to pay the $3k :>

[stark trench]

They want to sell to deep pocketed companies

[wise ingot]

The prices of the latest high-end FPGAs are dizzying

[silk verge]

As I'm fond of pointing out (and doing), hobbyists often spec orders for large companies

[wise ingot]

It seems they want to target defense and aerospace only

I mean, I agree

[stark trench]

And telecom

[silk verge]

Also networking

[wise ingot]

And high-speed trading

Or whatever the term was

*high-frequency

[stark trench]

They have a huge part of the Avant FPGA focused around 5G/edge acceleration

[wise ingot]

700-1800 DSP blocks is nice

(Looking at the avant datasheet)

[stark trench]

I’m interested in the RF front end parts of it

I hope they have some ISM IP front ends available

Like LoRa stuff

[wise ingot]

I mean, at that point, you could write your own IP core

[stark trench]

I’d have to spend money on the books for RF synthesis in my Amazon cart right now lol

Like $300 worth of books

[bleak osprey]

exactly

[wise ingot]

You can get xilinx's https://www.rfsocbook.com/ for the low low price of your PII

[silk verge]

I guess that's why it's spelled like "Facebook"

[wise ingot]

I mean, it's "only" name/email/org name, but, ... yeah

[silk verge]

I do have a genuine corporate email address for such purposes

But I'm not a fan of Xilinx

[stark trench]

Because they want to mill every dollar?

[wise ingot]

Their latest update weighs 100GB

[stark trench]

At least icecube2 is like 2GB

But it won’t start on my system anymore.. which is fine because I have been using yosys lately

[wise ingot]

TIL intel FPGAs have hard floating-point DSP blocks

[stark trench]

Yeah, fancy stuff in the new chips

They can do 400G routing through the fabric

Which is bonkers to me

[wise ingot]

That... probably isn't cheap :P

[stark trench]

Oh no, not at all

https://www.intel.com/content/www/us/en/products/details/fpga/agilex/7/item.html

[wise ingot]

It's funny how one of the applications of intel FPGAs are "soft" gaming consoles

[stark trench]

They have some demos of 400G and 800G NICs

[wise ingot]

The MiSTer thing is altera-based

[stark trench]

https://www.mouser.com/ProductDetail/Intel/DK-DEV-AGI027RBES?qs=Znm5pLBrcAJXZKmE76ma9A%3D%3D

Only $11k for their I Series that does 400GbE lol

And you even get a one year license of their Quartus Prime Pro software

[wise ingot]

One whole year!

So generous! :P

[stark trench]

I mean, why would anyone buy eval hardware without access to the software to develop on it 🙂

[wise ingot]

they could at least bundle a part-locked version

[wise ingot]

obligatory tang nano 20k announcement link
https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html

Certainly competitive for the price, but not sure about the toolchain

[wise ingot]

Huh.. There appears to be some form of native yosys support
https://github.com/YosysHQ/apicula
https://github.com/YosysHQ/nextpnr#nextpnr-gowin

[stark trench]

Oh I forgot to share this the other day, thanks for reminding me that this happened

[wise ingot]

No problem!

[mellow socket]

looking for recommendations on a cheap(ish) board to play around with FPGA whose tools aren't a pain to install and/or use
not sure if they all use same languages.... but i do have some experience manually writing VHDL and using the pain in the *** Vivado HLS -or whatever it was called- to convert C into a hardware definition (amazing tool, terrible interface)

[heavy arrow]

https://tenor.com/view/thats-the-neat-part-you-dont-invincible-gif-27194608

All of the FPGA tools are pretty painful.

As far as cheap-ish boards are concerned, there are definitely ones out there under $100. Digilent does Xilinx, TerasIC does Intel, and there are some open source Lattice boards.

You might want to take a look at YosysHQ if you want to try out an open FPGA toolchain.

[opal bramble]

it depends what you consider cheap and not a pain to get the tools.

this board

https://pico-ice.tinyvision.ai/

it's $35usd.... open source ( hardwared and software)... uses a raspberry rp2040 and fpga ice40

[heavy arrow]

One note: iCE40 is on the small end for FPGAs. Lattice also makes the ECP5 family which IIRC is also supported by yosis.

Also, I don't think yosis supports VHDL without doing a paid license.

[mellow socket]

that sounds nice, lets read the link ^^

[wise ingot]

Also look at https://blog.yosyshq.com/p/colorlight-part-1/

[heavy arrow]

lol

[wise ingot]

Let's hope the bot lets me post this time

https://github.com/ghdl/ghdl-yosys-plugin

[heavy arrow]

It exists, but they themselves say it is experimental. I wouldn't expect it to work without taking a serious deep dive.

[plucky helm]

OrangeCrab looks neat for adafruit feather form factor

its a bit pricier

[wise ingot]

It seems their official distribution includes the ghdl plugin

https://github.com/YosysHQ/oss-cad-suite-build

Never noticed because I don't use VHDL

[heavy arrow]

hmm

I need to ask aki about that again.

[wise ingot]

aki?

[heavy arrow]

(she works for YosysHQ)

[wise ingot]

Ah

If you try it, let me know how it worked out for you, so that I know what to tell people

(I don't know a word of VHDL)

[silk verge]

I find the open source tools pretty easy to install and use. You can install IceStudio if you want the whole graphical experience, or Fomu or apio if the command line version will do. There's a range of nice boards available from the TinyFPGA BX to boards with built-in buttons and lights like the Nandland Go and the 1BitSquared iCEBreaker

[silk verge]

They don't all use the same language, the main ones are Verilog and VHDL.

[wise ingot]

Oh btw, if you hate traditional hdls, feel free to look at some alternatives, such as
https://github.com/amaranth-lang/amaranth
or
https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

https://github.com/JulianKemmerer/PipelineC is another option

[glad bough]

big +1 for amaranth. it backs onto yosys and makes getting your gateware onto a variety of FPGAs extremely easy.

[wise ingot]

I've never used amaranth. Would you mind elaborating a bit on the benefits compared to writing (system)verilog? Does it make metaprogramming your design easier?

[glad bough]

Yes — vastly, since you're just writing Python, so "metaprogramming" is just programming. (And to be clear, Python isn't something I've used in earnest for many years, but it was extremely worth getting back into it for Amaranth.) I find a lot of the design decisions made in it make a bit more sense/aren't done that way because of a decision made in the 80's; it feels a bit easier to decompose and integrate into wider tooling (for me!). All this to be taken with a grain of salt — I'm relatively novice.

[wise ingot]

Thanks for the input! My main concern with writing in something like amaranth is "debugging" the design; Since it's all transpiled to verilog anyway, I feel trying to understand what the tool did with your code, and then what the synthesizer did with that code, would add an additional layer of complexity compared to directly writing in verilog. Of course, the same argument could be made (and I'm sure it was made, when they were a new development) for writing code in compiled higher-level languages versus directly writing in assembly :)

I will definitely take a look at amaranth sometime in the future though

[glad bough]

Yeah, that's a very understandable concern! (But I think you make a good point at the assembly vs. HLL comparison, too.)

[deft river]

I've used the GoWin IDE a little bit and like it. They will give you a free license, but you do have to have to ask to renew it each year. I did get one marketing phone call after I renewed, but it wasn't pushy. You can get a Tang Nano for about $10 from AlliExpress or a Tang Nano 9k for $15... The only thing that is a bit clunky is I had to use openFPGALoader instead of uploading from the IDE.

[vast moat]

The Tang Nano 20k was just released too.

[silk verge]

The site doesn't give system requirements, which is often code for "DOS only"

[wise ingot]

FYI, there is at least some support for gowin fpgas in yosys/nextpnr

[wise ingot]

Do you think a place-and-route flow could run in a dos box? :P

[heavy arrow]

PLD/GAL and some CPLD software did exactly that.

[silk verge]

I don't think I'm qualified to answer that

[deft river]

Was that about GoWin IDE? It supports both Windows and Linux... I've only used the Linux version

[silk verge]

Yeah, I was asking about the GoWin IDE. They don't seem to have a page that gives the system resources, and I was unwilling to create an account just to see what the download options might be.

[deft river]

One really nice thing is the Schematic Viewer... It lets you explode the design down to the individual gates/wires...

[wise ingot]

I think most FPGA solutions should be able to do that. With yosys, look into show or write_json and https://github.com/nturley/netlistsvg

[deft river]

I guess the difference is a lot of cmd line tools vs a integrated package. cmd line tools great for automation, but I find the IDE easier for learning...

[wise ingot]

Seriously, whatever works for you -- I'm not going to get into a holy war about whether a Bosch drill is better than a Makita :)

[deft river]

Not trying to convert you either... Just giving my personal experience... Opensource tools are great...

[wise ingot]

didn't take it that way, and I'm no oss purist -- I use xilinx vivado

[stark trench]

ryobi for people like me who are cheap lol

[wise ingot]

Yeah, those were just the first two brands that came to mind at the time of writing that comment :P

[stark trench]

I like to occasionally prod ChatGPT for how it handles requests for Verilog, here’s a decent one. Not great but it’s not terrible either.

[wise ingot]

Semi-related: efabless are running an AI competition. I'm really curious to see the results

[stark trench]

Oh same, I saw some cool posts about chips being fabbed from it

[wise ingot]

More related: https://www.youtube.com/watch?v=6vC3t_soJok + , of course, the original paper

[wise ingot]

I don't think the competition has been judged yet

though I haven't been following too closely

[stark trench]

I’m talking about ones that have been submitted already. Not that they’ve actually been fabbed

[wise ingot]

As I said, I haven't been following too closely

😅

[wise ingot]

@stark trench , the list of submissions has been released
https://mailchi.mp/efabless/community-poll-ai-generated-open-source-silicon-design-challenge

[frozen flower]

My Advanced Digital System Design grad course just had it's midterm, kudos to you folks that do this 😭

[stark trench]

We’re you able to do any practice on the IcyBlue feather?

[frozen flower]

Not yet, it's been tough with the intensity and schedule of summer classes. I have a couple days this week so hoping to soon. At the very least I will in a couple weeks when the class is done!

[wise ingot]

I hope you'll be able to enjoy FPGAs regardless.

[frozen flower]

Phew, other than the exam I'm free! Any good ideas for beginner friendly projects to use an FPGA for? I looked into strengths vs MCs but am struggling to find an application that fits what I would realistically do.

Bonus if it's for that sweet sweet IcyBlue Feather!

[stark trench]

I have some examples put together that I’m slowly adding to: https://github.com/skerr92/ice5lp4k_examples

Might give you a jumping point. I’m working on a CPU that can be fed instructions from an external microcontroller or device

[wise ingot]

Why feed it instructions off an external device when the FPGA is full of BRAMs that can be used for that purpose?
(Then you can have a controller to allow the user to externally rewrite the BRAM)

[stark trench]

It’s more of a practice in writing byte code

But there will be a version that will be able to be programmed into BRAM blocks. I just need more pins exposed

[wise ingot]

More... pins? But the block RAMs are internal, so any potential problems would be in the routing, not in the exposed pins. Unless you're making a tinytapeout thing, in which case, yeah, 8 pins aren't enough 😅

(I have probably misunderstood something)

[stark trench]

well, actually thinking about it. if I remove the frame from being read off physical pins I could just use those pins as the write interface to put a program in memory

[glad bough]

how many pins do you use to write? :D

[wise ingot]

Yeah, having an internal program BRAM and exposing an SPI/AXI/I2C/whatever programming interface sounds like a better plan

[stark trench]

currently, the frame is like... 16 bits wide?

so I could really free up pins writing to BRAM chunks

[glad bough]

right, i see!

yeah! and like ningen suggested, you can use a handful of pins for the interface and have a lot freed up too

even for just receiving them directly without involving RAM, doing a UART-like thing is very low-friction and frees up heaps

[stark trench]

Indeed

There’s a SPI example too in my examples repo so really I could just receive chunks of data and have a larger continuous chunk of memory

[glad bough]

oh! incidentally. i decided to start publishing my notes as i've been learning fpga stuff. here is the most recent: https://notes.hrzn.ee/posts/0002-untangling-cycles/ maybe the things i write will be helpful to someone!

[wise ingot]

Nice! It's... not trivial to get into FPGAs, so the more write-ups the better

[glad bough]

yes, that's been my feeling about it too!

[wise ingot]

If you don't mind me asking, which FPGA manufacturer are you using?

[glad bough]

i do my prototyping with an icebreaker and an orangecrab! so both lattice.

[wise ingot]

I presume you're using the opensource toolchain?

[glad bough]

yes! the first note actually is the one that covers this ^_^ https://notes.hrzn.ee/posts/0001-hdl-toolchain-source/

recently had cause to do it a LOT

[wise ingot]

Are you using the DDR on the orangecrab?

[glad bough]

it's what i'm planning to look at trying next week!!

i've just finished around with a lot of messing around with BRAM (and SPRAM on iCE40)

[wise ingot]

I'm wondering how you'd do it with the opensource tools. Normally, you need to instantiate a closed-source & encrypted IP to interface with it

"Normally"

[glad bough]

hmm, interesting! i'm looking at the moment at the pins it's mapped to on the orangecrab—it's a much bigger interface than i've dealt with before! i guess my plan was just to start there and see if i can get it to do anything at all. then probably look for others' experiences/success reports/etc., if i'm not getting far with datasheets or so.

ah, here we are

https://github.com/enjoy-digital/litedram

[wise ingot]

Please don't directly interface with the DDR

Yeah, find some IP, like the one above :P

[glad bough]

:D

that's using litex, which is not what i'm using, but it's enough of a start.

ah yeah

https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py

there's quite a bit there, but not beyond porting >_>

[wise ingot]

Just find some core that is written in, say, verilog, and interfaces the DDR to some known protocol, say, wishbone or AXI

Then write to the "bus" from amaranth and just instantiate the core

[glad bough]

hm, yeah. ^_^ that's easy!

[wise ingot]

It seems this IP core you linked fits the bill

It says it has an AXI-Memory Mapped or Wishbone interface

[glad bough]

right :3 the reason i talk about porting is because i'm using amaranth, which has a shared parent with litex, so it's not out of the question to get it such that i could instantiate it directly. but i think i will probably do as you say first, at least to quickly get it going (and e.g. make sure that my board's DDR is actually fine!)

[wise ingot]

It looks like litedram has been used with this board
https://github.com/orangecrab-fpga/orangecrab-hardware/issues/19

[glad bough]

yes, that's actually how i found the link

[wise ingot]

Ooh nice

[glad bough]

(googled 'ddr3 orangecrab' and that came up — this is the "look for others' experiences/success reports/etc." step!)

[wise ingot]

Looking forward to hearing that you got it to work!

[glad bough]

^_^ will report back!

[silk verge]

I think the last time I installed FPGA tools, I did it with pip install apio

[glad bough]

:3 yes. (I should mention that too!) My guide is targeted at those wanting builds from source to enable getting the exact versions you want, and to make debugging the tools themselves easier—to learn how they work, or to work on them.

[stark trench]

I feel pretty good with Verilog but sometimes when making a large design, something isn’t right where it will just not synthesize any of the design. I’m picking up this book to brush up on Verilog to design better Verilog by Example: A Concise Introduction for FPGA Design https://a.co/d/7hINOXJ

[wise ingot]

What helped me in the beginning was to go through the (back then it was ISE, this link goes to the vivado one though) synthesis manual, and look at the suggested code templates for each element https://docs.xilinx.com/viewer/book-attachment/jNBGJlxHewT1x7uxXwxN3A/~J0TB6toqCtuDOA05rWmrg . Then, it's a matter of sketching out the design's constituent parts before writing the HDL, and writing the "right" invocations to get the "components" you want

Also http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf

[stark trench]

Yeah, that’s fine. I want a physical book

[wise ingot]

That's valid

I just pointed them out in case you need something to supplement it with

[stark trench]

I appreciate it

Yosys and nextpnr are not always clear as to why something gets optimized out and what gets made which is a little bit frustrating to me

[wise ingot]

Sometimes you'll get that with other tools too, with the post-synth simulation not matching the behavioral one w/o any warnings

[stark trench]

I’m planning on breaking out my SystemVerilog test bench book too because I need to brush up on

[wise ingot]

yosys doesn't support sv iirc though

Unless you compile that addon

[stark trench]

No, it doesn’t

[wise ingot]

Which I have no idea whether it supports abv

[stark trench]

But I have an EDA Playground account and access to Synopsis

[wise ingot]

ooh yeah that'll do it :P

vivado also supports uvm if you're interested in that

and want something local for (xilinx) fpgas

[stark trench]

Yeah, I don’t have any Xilinx fpga unfortunately

I’d love to have one on hand but it just isn’t feasible at the moment

[silk verge]

What helped me in the beginning (back in the PAL days) was the fuse maps showing what each of the 5892 bits did.

[wise ingot]

I completely understand 🍻
Re: yosys, I've found that sometimes this helps: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/debug.html

(you prolly know, but I'm pointing it out just in case)

[wise ingot]

Were there HDLs back then, or did you manually specify which fuses to blow?

[stark trench]

Yeah, I really should spend more time going through it

Just need to find more time

[silk verge]

There were HDLs, so you had a choice. They were wonky DOS-only command line tools (PALASM, in my case) that I ended up running under windows for workgroups 3.1.3 under WINE on a SparcStation 1. My distaste for DOS tools existed then too, but the spectre of hand-deriving the equations for a few thousand fuses provided sufficient motivation to use the wretched PALASM so I could use an HDL. Still, knowing what was going on under the hood was useful for learning how to express my logic in a way that would fit in the device.

TIL that MMI had released the PALASM source code (in ForTran!) in the 1980s! How I wish I'd known that then! However, now that I do, I can compile PALASM to run on a modern OS. http://www.brouhaha.com/~eric/retrocomputing/mmi/palasm/palasm24.for

AMD produced an enhanced follow-on to PAL (their "V" series) in 1983 with the 22V10. They then acquired MMI in 1987, and then spun off the business as Vantis in 1996, which in turn was acquired by Lattice in 1999.

[wise ingot]

Oof, that's quite the house of cards of tools. Has your distaste for DOS tools carried over to CLI tools in general, or did it just stay there?

[silk verge]

No, I have no issues with CLI tools, I use them a lot.

[wise ingot]

Yeah, the DOS shell was/is its special brand of evil

[stark trench]

Info: Device utilisation:
Info:              ICESTORM_LC:   687/ 3520    19%
Info:             ICESTORM_RAM:    12/   20    60%
Info:                    SB_IO:    20/   96    20%
Info:                    SB_GB:     4/    8    50%
Info:             ICESTORM_PLL:     0/    1     0%
Info:              SB_WARMBOOT:     0/    1     0%
Info:             ICESTORM_DSP:     0/    4     0%
Info:           ICESTORM_HFOSC:     0/    1     0%
Info:           ICESTORM_LFOSC:     1/    1   100%
Info:                   SMCCLK:     0/    1     0%
Info:                   SB_I2C:     0/    2     0%
Info:                   SB_SPI:     0/    2     0%
Info:           SB_LED_DRV_CUR:     0/    1     0%
Info:               SB_RGB_DRV:     0/    1     0%``` latest statistics on a CPU design

called the DungV

It’ll be available on GitHub probably this weekend

[stark trench]

https://github.com/skerr92/DungV/

[wise ingot]

Nice! I hope you enjoyed making it!

[stark trench]

It’s still a WIP and it was nice to see the logic cell count grow as I added each feature 🙂

[wise ingot]

How's the timing?

[stark trench]

I still need to evaluate in sim

I have two more math operations to add (multiplication and division) which will round out ALU operations.

I probably need to add some flexibility for determining memory size. Maybe also make the memory dual port rather than single port.

[wise ingot]

It's not pipelined, right?

[stark trench]

Yeah, it’s single cycle

[wise ingot]

Well, at least it's not multi-cycle sequential

[stark trench]

It won’t be terribly great at fast speeds, so if I want a faster core it will need to be pipelined

[wise ingot]

The first CPU I built was pretty similar, but it was not RISC-V

[stark trench]

Mine doesn’t necessarily follow RISC-V

It’s a 17 instruction set that will hopefully be the basis for OASIS

[wise ingot]

DungV made me think it was RISC-V. I haven't looked at the RISC-V ISA (yeah, I know, it's, like, 10 years old at this point, but...... yeeeeah), so I did not take notice

I did give your design a quick read though

[stark trench]

Thanks! 🙂

I took some notes from my new book to really get a good design together

[wise ingot]

Oh it arrived already?

Nice!

[stark trench]

Yeah, Amazon next day

Building at 681 cells for what I pushed up, femtoV is under 1000 cells for integer only so it makes me think I’m in a good ballpark

Anyway, need me some sleep 🙂

[wise ingot]

Nite!

(I wanted to ask why you're using ===, since that'd only be used when comparing w/. X or Z which is not synthesizeable anyway, so == is fine, feel free to tell me when you wake up and have time)

[silk verge]

Division seems like the difficult one to me.

[stark trench]

Yeah, division is hard if you don’t want to just do by 2 division which is just bit shifting to the right.

[stark trench]

adding multiplication and division just increased my design by 2 lol

well, more than than

681 cell up to 1601

no DSP blocks used surprisingly

[wise ingot]

Can you use DSP blocks?

Ah, took it right out of my mouth :P

[stark trench]

I can technically

i'd have to specify them

which wouldn't be terribly hard

Info: Device utilisation:
Info:              ICESTORM_LC:  1601/ 3520    45%
Info:             ICESTORM_RAM:    12/   20    60%
Info:                    SB_IO:    20/   96    20%
Info:                    SB_GB:     6/    8    75%
Info:             ICESTORM_PLL:     0/    1     0%
Info:              SB_WARMBOOT:     0/    1     0%
Info:             ICESTORM_DSP:     0/    4     0%
Info:           ICESTORM_HFOSC:     0/    1     0%
Info:           ICESTORM_LFOSC:     1/    1   100%
Info:                   SMCCLK:     0/    1     0%
Info:                   SB_I2C:     0/    2     0%
Info:                   SB_SPI:     0/    2     0%
Info:           SB_LED_DRV_CUR:     0/    1     0%
Info:               SB_RGB_DRV:     0/    1     0%```

there's the statistics

[wise ingot]

I think you can do synth_ice40 -dsp

[stark trench]

Info: Device utilisation:
Info:              ICESTORM_LC:  1295/ 3520    36%
Info:             ICESTORM_RAM:    12/   20    60%
Info:                    SB_IO:    20/   96    20%
Info:                    SB_GB:     6/    8    75%
Info:             ICESTORM_PLL:     0/    1     0%
Info:              SB_WARMBOOT:     0/    1     0%
Info:             ICESTORM_DSP:     1/    4    25%
Info:           ICESTORM_HFOSC:     0/    1     0%
Info:           ICESTORM_LFOSC:     1/    1   100%
Info:                   SMCCLK:     0/    1     0%
Info:                   SB_I2C:     0/    2     0%
Info:                   SB_SPI:     0/    2     0%
Info:           SB_LED_DRV_CUR:     0/    1     0%
Info:               SB_RGB_DRV:     0/    1     0%```

there we go

1 DSP block

and 300 less LC

[wise ingot]

It's 16bit, so not that surprising if it's 18x18

[stark trench]

Yeah, I’d gather at least that

This design would probably use more cells if I switched to high speed osc

[wise ingot]

you'd have to pipeline it, so, yeah

How's the timing now?

[stark trench]

Oh, the timing analysis from the build?

[wise ingot]

yeah

[stark trench]

Info: Max frequency for clock 'clk': 4.14 MHz (PASS at 0.01 MHz)

Info: Max delay <async>     -> posedge clk: 7.47 ns
Info: Max delay posedge clk -> <async>    : 5.73 ns```

4.14MHz

Using a 10kHz clock

This feels pretty good tbh

[wise ingot]

That was quite... a pessimistic SDC :P

If you try increasing your frequency constraint, it might make the pnr algo work harder and give you better timings

[stark trench]

I specified the LF OSC in the design, it only supports up to 48MHz for the HF OSC. I’d probably get better results building for a faster FPGA

[wise ingot]

It's slower than spartan3?

(I started on spartan3, hence the comparison :P)

[stark trench]

Probably?

50MHz for spartan3 I guess?

[wise ingot]

The CPU I made at the time went up to 50MHz on the spartan3

But I remember simpler designs could go up to 100-something MHz

[stark trench]

Yeah, low processing routing can do up to 100MHz

48MHz for me though 🙂

That’s what you get with an $8 FPGA

Vs a $25 one

Spartan3 chip is $20+

Anyway, I’m very happy my design builds and uses a reasonable number of cells

[wise ingot]

yup, that's the spirit! You don't have a jump or conditional jump instruction, right?

that'd be the next thing to add imo

[stark trench]

Not yet, but it’s in the docket

[wise ingot]

nice! :D

does riscv have guarded instruction exec, or cmp etc instrs?

[stark trench]

I think it might? I’m not super familiar

[wise ingot]

Me neither

In the second CPU I designed, I made every instruction capable of being executed conditionally by adding a guard and condition field to the instructions

[stark trench]

Nice! I have one more flag state I could expand

Well, technically 2

[wise ingot]

I'm thinking of getting a mango pi (1) for the novelty of a pink PCB (I've never seen one in person, only green, black, red and white), and (2) to have an excuse to learn more about risc-v

Or this little more affordable board: https://www.aliexpress.com/item/1005004895791296.html

[stark trench]

Yeah, would be a great opportunity to learn it

[wise ingot]

(I remember WCH having some equally affordable ones that also did USB host, they probably decided to increase the price for them)

Ah, the ones that do USB host go for EUR14. Fairly reasonable

[stark trench]

Yeah, not too bad

[stark trench]

Turns out it was as easy as doing q <= operandA / operandB;

Lol

[wise ingot]

O_O Yosys can synthesize a divider?

[stark trench]

Apparently

[wise ingot]

I somehow doubt the gatelevel sim is gonna work

[stark trench]

Verilog and system Verilog support division

[wise ingot]

Yeah, but I'm not sure the operator is synthesizable

[stark trench]

Let me put my Mac on charge and I’ll tell you for certain if commenting it out changes design size

[wise ingot]

(If you want to make sure it actually synthesizes, you can write_verilog after the synth pass, and do gatelevel sim with your testbench and the written verilog file, by passing techlibs/ice40/cells_sim.v to icarus verilog)

[stark trench]

commenting it out reduced design size from 1295 to 700

so.. I imagine it just takes a lot of cells to do it.

[wise ingot]

hmmm... Does it work if the divisor isn't a power of 2?

[stark trench]

from the yosys docs

it's integer division and won't return more than the floor of the operation

[stark trench]

do you have an example of this usage?

build:
    yosys -p "synth_ice40 -dsp -top top -json $(filename).json" $(filename).v
    nextpnr-ice40 --u4k --package sg48 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc
    icepack $(filename).asc $(filename).bin

this is my current build command.

I need to write the test bench still

[wise ingot]

FYI, I tested division using that, it worked O_O. yosys is mad science :P

Here's my flow:

read_verilog div.v
synth_ice40 -top div
write_verilog div_synth.v```
And then, in bash:
```bash
iverilog -g2012 ~/oss-cad-suite/share/yosys/ice40/cells_sim.v div_synth.v div_tb.v

...This does a simulation of the synthesized design at the FPGA logic cell level

FYI, contents of div.v

module div (input [7:0] a, b,
            output reg [7:0] c);
    always @(*)
        c = a/b;
endmodule

div_tb.v

module div_tb();
    reg [7:0] a, b;
    wire [7:0] c;
    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, div_tb);
        #1;
        a = 8'd120;
        b = 8'd30;
        #1;
        a = 8'd90;
        b = 8'd20;
        #1;
        a = 8'd100;
        b = 8'd3;
        #1;
        $finish();
    end
    div div0(a, b, c);
endmodule

[stark trench]

wild, huh?

after getting basic test benches up and working, I want to start working on making an MPW submission

but I also want more features too, so no timeline 😛

[wise ingot]

You know what's wilder? Starting from 2022.1, vivado supports synthesizing combinational division for any divisor

[stark trench]

😮

FPGA are awesome

and verilog

and HDLs in general

they're a pain to learn, but once you know them.. wow can you do some cool stuff

[wise ingot]

TBF, I would not use whatever / infers in a production design. It'd probably be best to design a pipelined division for obvious reasons

[stark trench]

probably fine for an FPGA though

[wise ingot]

Probably not if you want to push the timings

[stark trench]

i'm not terribly concerned about it being super fast given that the FPGA itself isn't that fast.

[heavy arrow]

Verilog is... painful. SystemVerilog is much better, but still more C-like than I prefer. For synthesis I've had the best experience with VHDL.

[wise ingot]

SV contains significant QOL improvements, yeah

[stark trench]

VHDL will give you back what you put in. Right, Wrong, or Indifferent

[wise ingot]

I've never used VHDL. Would you mind elaborating how it's better for synthesis?

[stark trench]

if you specify something wrong, it'll synth it. and you won't know why it doesn't work.

verilog/SV likely will just optimize it out

I do appreciate VHDL for letting you just do whatever.

or, this has been my experience with VHDL anyway

Verilog has been more frustrating to me because what flies in VHDL doesn't necessarily fly in Verilog...

[heavy arrow]

I disagree here. It's actually the opposite. (System)Verilog will allow you to do pretty much whatever, and there are usually 3 or 4 ways to do things that can introduce a number of ambiguities. VHDL is very verbose, but it also forces you to be much more explicit.

You don't want any ambiguities in a hardware design.

[stark trench]

I’ve tried to design in Verilog how I design in VHDL and often end up with 1 cell designs

I learned VHDL first

[heavy arrow]

Again, I've found this to be the opposite. Verilog implies a lot of things that VHDL forces you to specify explicitly.

[wise ingot]

IME verilog is an exercise in satisfying the synthesizer's pattern-matching to get the thing you need

[stark trench]

Different experiences yield different perspectives

[wise ingot]

I have not tried VHDL, so I don't have an opinion one way or the other

[heavy arrow]

Just like C with an optimizing compiler.

[stark trench]

I don’t really think we are saying anything different at the core. I don’t disagree with what you’re saying. Just the perspective on it is a little different

[wise ingot]

The comparison is apt

(If you don't mind me asking, are you manually ticking off the "turn pinging off" option every time you write a reply, or is there an option somewhere I could set?)

[heavy arrow]

And that is also one of the biggest pitfalls of verilog: people tend to write it as if it were C or C++. But an HDL is not a programming language. There are procedural elements in both, but that is for testbench design.

Another big difference is that Verilog is weakly typed.

While implicit conversions are often convenient, they can also result in issues that are extremely difficult to track down.

[wise ingot]

(Also automatic bit width expansions/truncations)

Thankfully, most synthesis programs will spit a warning for that

.....most of the time

[stark trench]

Yosys does, lots of warnings lol..

Anyway, with my design.. the next thing I’ll be doing is writing a python script that will generate a random program that will pull from a list of commands, registers, memory locations, etc.. and do stuff

[silk verge]

Interesting. I've been building fractional frequency dividers in FPGAs, now I'm wondering if I can leverage that functionality. Not that it's a big change, the frequency dividers are only a few lines of code.

[stark trench]

Have that build with the design via an initialization

A reverse decade counter is technically a frequency divider 🙂

Or any counter really

[wise ingot]

you could integrate it with cocotb and do a full instrumented constrained random verification

[stark trench]

True, very true

[stark trench]

https://github.com/YosysHQ/yosys/blob/master/techlibs/common/techmap.v#L307

It’s combinatorial

Someone in the 1bitsquared discord mentioned that 16 bit division would use 256 intermediary wires 😬

ABC would also not optimize to route efficient, but route fast so you lose some speed in execution and take a penalty on space

I’ll probably switch to sequential division

[wise ingot]

Nice job looking that up! Switching to sequential division sounds like a good idea, even for the learning experience

[stark trench]

Yeah, all you’re really doing is a for loop and subtracting until you’re at zero or less than

[heavy arrow]

You want a pipelined state machine, not a for loop.

[stark trench]

True

I was just saying in general you can achieve division by subtracting till you can’t anymore 😛

Not that it’s an efficient design

[heavy arrow]

Even then you wouldn't write that as a for loop. It's just a couple of registers, a subtractor, a counter, and some control logic.

[wise ingot]

for loops are not synthesizable outside generate blocks

And even then the purpose is different

[heavy arrow]

That's exactly my point.

[stark trench]

I’m referring to in software, you can achieve division. I’m not suggesting using a for loop on hardware.

I’ll probably just do software division and save the speed penalty on hardware

[wise ingot]

The main point is that you're designing and implementing stuff, and that you're enjoying yourself while doing it. The worst thing that would have happened even if you, or anyone else reading this, were to write a for loop, would be that the end result would not work in hardware (and in the post-synth sim), in which case you would simply find out why after some amount of looking up

Also, sorry for the misunderstanding! :)

[stark trench]

I know this, I probably should have been more clear from the start that I was in no way suggesting doing division on hardware with a for loop.

[heavy arrow]

If you are wanting to see how to implement division in software, there are a variety of ways to do it. Unless you are dealing with bignums (i.e. massive variable length integers) you probably don't need a for loop.

[stark trench]

removing division and enabling ABC9, we get up to 44.11MHz but fails on the HS OSC:

Info: Max frequency for clock 'clk': 44.11 MHz (FAIL at 48.00 MHz)

Info: Max delay <async>     -> posedge clk: 6.11 ns
Info: Max delay posedge clk -> <async>    : 6.39 ns```

and this is about as close as I can get it with the PLL:

Info: Max frequency for clock 'clk_$glb_clk': 43.81 MHz (PASS at 43.52 MHz)

Info: Max delay <async>              -> posedge clk_$glb_clk: 6.81 ns
Info: Max delay posedge clk_$glb_clk -> <async>             : 6.18 ns```

[wise ingot]

Nice!

[stark trench]

changed the counter that drives the RGB (because every processor needs RGB) to a 32 bit counter, so it slowed down a few MHz. so I decided to go with a safe 24MHz

[wise ingot]

You know what? I'm actually laughing atm in front of my computer, because of the prospect of a literal RGB CPU

[stark trench]

Not super fast, but faster than most 8 bit microcontrollers.

[wise ingot]

GAMER VERILOG

[stark trench]

I just need to add some jmp instructions and it should be a nicely rounded instruction set and CPU 🙂

[heavy arrow]

[wise ingot]

Sorry! Blame the RGB

[stark trench]

then all that's left is a programming interface (probably SPI), GPIO controller, maybe a PWM peripheral. I2C

[plucky gull]

can you make the colour depend on clock speed? Like literally red = faster? 😆

[wise ingot]

https://tenor.com/view/hypnotoad-futurama-gif-20673964

[stark trench]

I've got about 2770 cells to use

lol

red means fast

blue is chill mode

[plucky gull]

exactly!

green = low power sleep

[wise ingot]

Oh, speaking of sleep, I wonder if you can fit ✨ ＩＮＴＥＲＲＵＰＴＳ✨

[stark trench]

possibly?

I'd need to find a good example

I've technically already have a counter, so it might not be hard.

at least for software interrupts or even hardware interrupts might not be hard.

[wise ingot]

I mean, the simplest way would be to jump to the memory location specified in a fixed location (say, fff0 or something) when an interrupt signal arrives

The programmer would have to set up the pointers to a valid interrupt service routine

Also an instruction to turn interrupts on or off, and a Non-Maskable Interrupt that can't be ignored

6502-style :P

[stark trench]

that might work

or probably would work

[silk verge]

256 intermediary wires/signals sounds like a lot, but they’re mainly notional and don’t necessarily take up physical resources (depending on the FPGA, its implementation, and what the router comes up with).

[stark trench]

It just ends up meaning on the fpga that we’re going to use about 2x the wires in cells which is basically what happened

[glad bough]

o/ ^_^

[wise ingot]

https://tenor.com/view/dont-cross-the-streams-egon-ghostbusters-bill-murray-gif-14907508

[stark trench]

@wise ingot you would be happy to know that I have added jump instructions to the DungV core 🙂

I'm making a version that uses the wishbone bus and going to write a test suite around it

and also, make it submittable for MPW shuttles

super exciting 🙂

[wise ingot]

Exciting indeed!

Do you think it could fit in a tt mux slot?

[stark trench]

Maybe a 4x2 if I don’t use wishbone

Biggest issue I see if DFF ram

Okay, probably wouldn’t work directly on TT

I have a hankering to make a crosslink dev board

There’s some open source support for it too

Probably this one: https://www.digikey.com/en/products/detail/LIF-MD6000-6JMG80I/6173869

[wise ingot]

how many layers would that need?

[stark trench]

Probably 6

Especially for routing the MIPI interface

[wise ingot]

oof.

[stark trench]

Fanout shouldn’t be terrible

I’m going to through some external parallel SRAM on it

Luckily it’s only 80 BGA on a 6.5x6.5mm package

[wise ingot]

hmmm... Isn't MIPI super-NDA'd?

[stark trench]

Nah, just export controlled I believe

[wise ingot]

I might be confusing it with another protocol, then

[stark trench]

https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/ipcore/ipcores04/bytetopixelconverter

Here’s one IP core type you can use

[wise ingot]

I could, if I had a lattice devboard

I see that Xilinx has mipi IP too, though

[stark trench]

Yeah

[wise ingot]

So, I guess that in theory I could do things with MIPI, if I cared and if I had the proper board.

:P

[stark trench]

I’m thinking of making a dev board for that crosslink. I think it’d be fun

[wise ingot]

Why don't you ship the icyblue feather first?

Sounds like a good way to get funding to build the second devboard to me

[stark trench]

IcyBlue is nearing launch

I’d be making the CrossLink for me personally. No plans to sell it

[wise ingot]

Ah, cool.

[wise ingot]

Crosslink sounds like something a fancy gym would offer :P

[stark trench]

Yeah, kind of funny to me

[wise ingot]

Also cross-linking is what formaldehyde does

[stark trench]

I’m interested in it because of the price, and fabric speed

1.2G across the fpga fabric

6Gbps for camera interface

[wise ingot]

EUR14 / IC, and available

I wonder why there is no devboard

[stark trench]

There is

$212

https://www.digikey.com/en/products/detail/LIF-MD6000-ML-EVN/6036270

[wise ingot]

I'm not surprised. High-speed signaling devboards command $$$

[stark trench]

Yup!

6L with a 4 wire kelvin test from JLC should be sufficient

My dev costs will probably be like.. probably $80-100

For parts and stuff

[wise ingot]

funny story, kelvin test makes me think of somebody submerging the board in a hot water bath for some reason