#ARISA

26 messages · Page 1 of 1 (latest)

real ibex
real ibex
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I should probably share a screenshot of what I have so far.

image.png
hollow island
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What are the 4 instructions that you've listed?

real ibex
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Which 4 instructions?

hollow island
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readcr, writecr, syscall, eret

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Also, very organized wiring, well done

real ibex
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readcr and writecr are used to access CPU control registers which allow you to get or set the CPU state depending on the situation. For example, it can control where interrupts are handled or tell you how big the cache is (neither are implemented atm though). syscall and eret are used for software interrupts and returning from interrupt handlers. Take a look at #etc-architecture for how they could be implemented/used

hollow island
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Noted, thanks!

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Hold on, why would you need control registers?

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Other than the counter and some address related hardware, why else would you need control registers?

real ibex
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For settings things like the interrupt handler address, page table address, etc.

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Could also be used in a multi-core system to control other cores

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Basically anything related to CPU status + control

real ibex
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I have now combined the instruction and data address spaces. It's very simple right now with 2 dual_ram components. Both are set to 65536 bytes, but the first is repeated over the entire address space except the last 65536 bytes. The second is in the last 65536 bytes of the address space. I also now initialize the instruction pointer to start executing at address 0xFFFF_FFFF_FFFF_0000 which corresponds to the beginning of the second dual_ram component. The second one also does not have it's write line connected to anything since it's supposed to be read-only. Along with this, I've also added the required hardware to inject nop instructions which aside from being needed for first tick initialization, will also be needed when I add pipelining to it.

image.png
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The test program you see just writes a program to memory which sets all 32 registers to there own number and then halts. After writing that program to RAM, it executes the program which is why you see all the registers set to their own value. r0 is not displayed or written to because it's hardwired to always be 0

real ibex
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Updated spec. Main changes are the addition of conditional ALU operations and stcnd and ldlck instructions to allow for locks to be implemented. While they're not useful now, it will allow for multi-threaded programs once interrupts are added

📎 ARISA_Spec.txt
frigid stirrup
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why did you choose the name ARISA?

true salmon
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A Really cool ISA 😄

warped summit
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ARISe(n) Architecture 🤔

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Another Reduced Instruction Set Architecture 🤔

real ibex
real ibex
real ibex
real ibex
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Just updated the hardware to only invalidate the ldlck state when an stcnd occurs or when a store or push occur at the same address as the last ldlck if you ignore the 3 lowest bits of the address or the address 8 bytes above that. stcnd will also fail if it's not in one of the same addresses as above. This means that each synchronized section of memory should have at least 16 bytes between the start of them.

real ibex
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This prevents the issue of ldlck at address A, a write occurring at address A by another piece of code, ldlck at address B, and then the original code performing an stcnd to address A.

A: ldlck address A
-- context switch --
B: ldlck address A
B: stcnd address A
-- context switch --
C: ldlck address B
-- context switch --
A: stcnd address A

As long as |(B & ~7) - (A & ~7)| >= 16, there will be no issues with these changes. I chose to use adjacent 8 byte sections for this since unaligned 8 byte writes will never be outside of these 16 bytes. At some point in the future, this might be adjusted to adjacent cache lines.

real ibex
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Just adjusted it so that if you use a memory address and operation size which stays within an 8 byte aligned chunk of memory, you can use a reduced separation of 8 bytes instead of 16 bytes.