Variable-size components

[autumn forum]

It would be nice to have some "variable-size" components. It could help speed up the simulation (using an "hard-coded" component instead of a self-created one) and have a better visual appearance.

It would also reflect some real components (in the 74XX series) like 7420 (4-input NAND) and 7030 (8-input NAND)

it could apply to :

AND/NAND/OR/NOR/XOR/XNOR : 2 to 8 inputs versions

MUX N:1 : having selection of 2:1, 4:1, 8:1 16:1 with 1/2/3/4 bit selector

n-MUX 2:1 : MUX allowing switching 1/2/3/4 bit of data at the same time. (either changing number of input or of selection bits to keep it or reasonnable size)

n-bit SWITCH : allowing to set to Hi-Z a n-bit value (1/2/3/4 bits)

n-bit Priority encoder : 2/4/8 input, 1/2/3 output, can be a reward from a quest asking to create it

Decoder : (right now, we have 1/2/3 to 2/4/8 decoder but 74159 is 4 to 16 decoder)

[gleaming mountain]

Are you on the development branch? Because basically all components are variable size now.
Unless I'm misunderstanding what you're saying.

[autumn forum]

Well, just checked the "very alpha" branch and it's not what I meant.

Very alpha allows to change word-size. which is not what I was talking about.

For example, NAND you've components (real life) which do 2-input NAND, 3-input NAND, 4-input NAND and 8-input NAND.

It's not about a "word size" but about the number of separate terms being NANDed.

For the MUX, it's about the number of selection input (first option) or about separate signals (for example, 3-bit register selection).

The second option could easily be replaced by n separate muxes but having one single component with 2*n inputs and n outputs would lead to cleaner schematics and could allow a better optimisation of the processing.

Priority encoder is not present. Decoders are separate components for the 1 bit DEC, 2 bit DEC and 3 bit DEC (4-bit is not available while it's a 74HC159 in real electronics)

[potent spindle]

You can just make your own 8-input NAND

[autumn forum]

I know... But

• A real 8-input NAND has the same delay than a 2-input NAND. A custom component one would have several time that delay (3 times the delay).
• Simulation-wise, it'd require the processing of 6 AND + 1 NAND instead of the processing of one component (+ the extra processing of one custom component)
• It'd be a rectangulat box with 8 inputs and one output and the word 8-NAND on it instead of the normal NAND icon.

I do know that what I'm asking could be made with custom components (1BIT MUX is not present in the 1BIT library by the way). As I said, it's mostly for visual aspect (like the NAND example) and simulation speed.

[potent spindle]

A real 8-input NAND has the same delay than a 2-input NAND
That's not true though?
It doesn't have 3 times the delay (I think), but it's not the same

Simulation-wise, it'd require the processing of 6 AND + 1 NAND instead of the processing of one component
No, because each component is turned into a CPU instruction (or a few). You don't have an 8-input NAND instruction in any CPU supported by Turing Complete (and I don't think there's any supporting that at all)

[raven patio]

Oh, you mean variable input components. (I guess everyone already figured that out. 🤦🏽‍♀️ )

[delicate storm]

While it's true that no CPU directly supports that instruction literally. You can pretty easily calculate nand, and, nor, and or with n bits of input by packing them into an n-bit word and performing an equality check with 0 or -1. They would be != -1, == -1, == 0, and != 0 respectively

[potent spindle]

Hmm that's true.
I still do not think there is much use for that, as it would be more work than just calculating the operation tree

I mean that packing the inputs into one word would be more work than just doing the 2-input stuff

[delicate storm]

The second option could easily be replaced by n separate muxes but having one single component with 2*n inputs and n outputs would lead to cleaner schematics and could allow a better optimisation of the processing.
You could also use a custom component which uses an n-bit decoder and 2^n switches

[delicate storm]

Yeah, I don't think it would be efficient at all, but it CAN be done. I think having a 3 and 4 input version of them would be nice though

[raven patio]

I have on a number of cases found myself wishing I had a better != == with -1 and 0. Though, I guess not == 0 since that’s just EQ with an empty argument. But snaking a -1 component from somewhere else can be pretty hard what with the size of the constant component.

Maybe a component that simply takes an input named something like ALL/NONE SET/CLEAR? Then people can bundle the wires themselves? We already have a 2/4/8 part maker?

[potent spindle]

Why hard? You can just use a static evaluator with (1 << width) - 1

[delicate storm]

I actually have custom components for == 0 and != 0 for both component size and because I uses switches to get low-delay calculation of it. I'm not sure if you can make the same thing with an adjustable size in the alpha though (without using an actual equal component)

[raven patio]

Ok, I suppose that’s a bit smaller than the constant component. 🤦🏽‍♀️

[potent spindle]

Or do you mean to have a component tree to not use the equal component? Then no, you can't make that dynamic

[autumn forum]

A real 8-Input NAND has 8 lines of polysilicium (one for each input) crossing the N or P substrate putting the 8 transistor in serie. A real 2-input NAND has only 2 lines of polysilicium crossing the N or P substrate.

The delay is the same in both cases (which also happen to be the minimal delay possible)

As I said, it'd be "nice to have"

1. for the delay and gate count (much lower than using chain of 2/3 inputs gates in a custom component)
2. for the specific display (a big AND gate with 4 inputs or more instead of a "custom component box"
3. for simulation efficiency (less components, less wires and no need to read a custom component which is somewhat similar to a function call)

I'm referring to actual electronic circuits which do have 2-input, 3-input, 4-input and 8-input logic gates (and other components likewise).

The logic is similar to the 4-NAND XOR or to force the use of 3-input AND/OR in order to keep gate number low (and in the process make the simulation less CPU-hungry).

[autumn forum]

This means a comparison which has a much higher delay. Chaining AND/OR and ending with a AND/NAND OR/OR would result in the same with a lower delay than a comparison.

[raven patio]

No, you’ve misunderstood. The use of != -1 and == 0 is how it would be implemented in the backend emulation.

[autumn forum]

Ok, but for it, you need to have the backend recognizing it as an n-input logic gate... which is probably not the case when using custom components.

[raven patio]

That’s the point. We could make a 4-bit input horizontal-OR component, that is equivalent to x₁ ∨ x₂ ∨ x₃ ∨ x₄, which can be efficiently emulated as just simply != 0.

[autumn forum]

That's basically what I was suggesting (having the AND/OR/NAND/NOR with 2/3/4/.../8 input)...
in order to have a more efficient emulation than using custom circuits and in order to have "realistic" delay/gate counts (right now, 3-input AND has a delay of 4 while a real 3-input should have the same delay than the 2-input. And making a 8-input leads to a delay of 6 instead of 2).
An added bonus would be to have a "AND" image (stretched vertically to accomodate the 8 inputs) instead of a square box like you've with custom components.

AND/OR with more input can be quite useful if you intend to use the "sum of minterms" built for complex logic function (Quine Mc Clusky/Karnaugh) which would have a constant delay of 6.

[potent spindle]

Except, as I've told already, packing the variables into one value so you can do != 0 will be slower than just resolving an operation tree

And at this point you can just make your own custom component

[autumn forum]

You really don't read what I wrote !!!

Custom component leads to bigger delay (unlike on real electronics) and gate count (less important).

And a comparator (EQ) is also much slower...

Operation tree for a 8-input AND would take a delay of 6. Between 9 and 16 it would get to 8, ...

[raven patio]

I’m not sure how much we need one with multiple separate inputs. That would require a 4-bit wire to be split into 4 and then fed into the 4-input (N)AND/(N)OR. And the logic of the built-in component would require it to assemble the separate inputs into a single value in order to efficiently test against (N)EQ -1/0. Meanwhile, if it takes an n-bit wire input, then we don’t have to internally assemble the inputs, especially if we just split them apart, and we already have a 2-input, 4-input, 8-input join components as well, which means they’re more flexible, and then the user tells us which wires we should join up as how into the inputs.

[raven patio]

Hopefully, you’re aware that Delay is an arbitrary value that we use to score circuits. It is not representative of how much time it takes your computer to resolve that value.

[potent spindle]

What are the actual use-cases for having 2/4/6 less delay for multi-input and/or/n- gates?
I don't think people would use them much?
Maybe for carry-lookahead adders, and that's all?

It's a thing that only affects high scores, that's why I don't think having a set of components just for that is good

[autumn forum]

Well, my background is civil engineer in electronics... which means that I learned how to simplify complex equations using Quine Mc Clusky (for example, 5-input function with don't care reduced to something like A__B__C + A__D + B__CE + CDE, underline is "not" (no overline in discord))

This is what is used in PAL/GAL (FPGA use small lookup tables)

having all term with the same delay (regardless of the number of terms in the AND) means that all signals also end up in the output at the same time.

Unlike Karnaugh, Quine Mc Clusky is easy to do by hand up to 6-7 input and can be very easily programmed (even on a HP28s calculator... did it.)

[raven patio]

OK… but in TC, everything already synchs up to the outputs at the same time already… 😐 Like, the component won’t calculate until all the inputs have been calculated and are ready.

[autumn forum]

Also, please note that I wrote in my original post "nice to have" (I know that we can create them as custom component), and pointed that it'd allow some optimization in the simulator (like when you use the n-bit ADDER component instead of ripple chaining n FA) and would also allow better display (AND/OR/... being represented by the AND/OR/... image (stretched to accomodate the extra inputs) instead of a simple square.

I never said it was really required... The delay part is only an added bonus (as you said, it's arbitrary, best proof is that the 3-input OR has a delay of 4 while a real (74XX serie) 3-input OR has the same delay than the 2-input OR)

[potent spindle]

All people in this thread know Karnaugh and McCluskey, I think.
Still, I think it's not that important to reduce the delay in those cases in TC

[potent spindle]

N-bit adders are just simulated as X+Y

[autumn forum]

That's only possible because TC IMPLEMENTS THEM AS BUILT-IN COMPONENTS and not as custom components...

And that's precisely what I suggested to add : built-in components for various length of several key components.

Also, I'm not sure that all people using TC know about Quine-Mc Cluskey. That's what is great with TC, no real prerequisites needed (well, unless maybe for the "binary races" (signed/unsigned) where someone with no previous understanding of binary may get blocked for a while).

@raven patio probably gave the most interresting answer by pointing out that the delay is not really used in TC except for scoring.

But TC is meant to create complex circuitry... and more built-in components may help in keeping the simulation fast.

[potent spindle]

1. I didn't say that everyone using TC knows those algorithms. I said that everyone in this thread knows them (that is You, me and Kisse Mjolk mainly)

[autumn forum]

I can't presume that you know it, I don't know you personnally nor your technical background

[potent spindle]

2. Yes, Adders are simulates as addition because they're built-in. But they are built-in because it makes sense for them to be. That is, they are used in many, many other components/builds that people fo, so it doesn't make sense to simulate the internals every time.
   My position is that multi-input basic gates are not on the same level of usefullness.

3. Actually having multi-input gates will not enable simulating them faster, because the inputs will have to be put into one variable. To do that you need to bit-shift and OR them. Then you can EQ to get the output. This is O(n).
   Having a gate tree is also O(n), but the operations are more basic (you only do the operation, no shifting).

[autumn forum]

People use what they've available... not useful for YOU don't mean that noone else would find it useful.

[potent spindle]

You're misunderstanding me.
I'm saying that I have a strong reason to suspect that if you were to scan the available builds people did, you would not find an amount of gate trees that simulate multi-input basic gates, that would be enough to add dedicated components for that.

They are not that common to support adding them as built-in components

A much better suggestion would be to have the current 3-input gates have the same delay as the 2-input versions.

[autumn forum]

My list of variable-sized components was not limited to the logical gates...

[potent spindle]

What else do you want variable-sized? Adders? Multipliers?

[autumn forum]

it's another matter (my original post was not about the delay) but I agree that it's a valid suggestion

[potent spindle]

We already have n-bit switches.
You can make muxes of whatever size you want by using the decoders and switches (and it would be your pain to manage all the IO)

[autumn forum]

MUX, Decoder, Priority Encoder, multi-bits switches (using separate signals, not using "busses")

as I said, it'd allow nicer display than these "custom components boxes" and Godot's code optimisations for the simulation of these usecases.

I know that all these can be created using custom components.

[potent spindle]

We're back to point zero:

• Those things you can build yourself using current components easily
• Having two variants of an n-bit switch will be confusing
• It won't enable many more optimizations than you think it will

[potent spindle]

The simulation backend is written in Nim actually

The only argument I see here is that blocky components look ugly - but that should be a separate feature request, to have them be skinnable or smth

[autumn forum]

It won't enable many more optimizations than you think it will

I don't know the internals of TC so I can't say...

The only argument I see here is that blocky components look ugly - but that should be a separate feature request, to have them be skinnable or smth

It's a good idea even if different from what I was asking (more built-ins).

[raven patio]

I mean, I’ve regularly run into wanting a (N)EQ 0/-1. And Endershadow mentioned that he also builds at least the (N)EQ zero custom components just like I do. I do sort of hate that the fastest emulation design is just to plop down an EQ, while the most score efficient is to build a horizontal OR/NOR, when we could have both with an isZ and notZ at least.

[potent spindle]

But that's a separate issue from having N-input gates.
Having isZero and isNotZero components would be useful though.

But plopping an EQ will still be the fastest in terms of simulation (well those zero components will be the same)

[raven patio]

Except that isZero is just a horizontal NOR, and isNotZero is a horizontal OR. And thus barring the fact that the inputs aren’t separate pins, is an N-input (N)OR gate.

[delicate storm]

fwiw, vector instructions could also possibly be used for 4 input gates

[crisp flicker]

I do. Adding these builtins will barely, if at all, allow for more optimizations in runtime

The only argument you can make is to allow them for better scoring

And here I am against it and Stuffe is pretty much in the same mind: we want to keep scoring simple with as few magic builtins as possible

All 4 basic logic gates having the same score is a compromise because favoring either of AND or OR just isn't particularly fun for building, and really clashes with reality

The 3 input variants are scored based on your level solution

[autumn forum]

well, AND and OR have about the same timing in real world and they are a little slower than NAND and OR 😉

[crisp flicker]

I know. I have no idea what you want to communicate with this message

[crisp flicker]

Or your reaction to this message

[autumn forum]

Nothing, it's just that your comment about equal timing between AND and OR seemed so out of place... it'd have made more sense if you had compared AND and NAND.

And the 3-input variants of logical gates don't leave much choice as at that step, you don't have the switches, only logic gates

(switches could allow a delay 2 for OR instead of delay 4)

[crisp flicker]

Well, I tried to explain our logic to you 🤷

[autumn forum]

I know... OTOH, XOR has a Delay 2 while the circuit that you build has a delay of either 4 (OR, NAND, AND), or 6 (4-NAND)

[crisp flicker]

That would be a bug

[autumn forum]

Or intended in order to not favor any logic gate over the other one...

[crisp flicker]

No, that would be a bug

I know this because I decided how these components should be scored

If you are still looking at the alpha (the only relevant place for discussion future changes), notice that sll delay values got halved

[autumn forum]

OK... maybe it's because I've not revisited these since I unlocked the delay/gate counts

Well, I'm back to "development" as the alpha has screwed the saves and I intend to share my designs with a (real life) friend which is not on alpha

And Steam sync did not help... Would be nice to be able to have the two side by side but not an option with Steam...

anyway, this is getting quite away from initial topic...

A much better suggestion would be to have the current 3-input gates have the same delay as the 2-input versions.

The only argument I see here is that blocky components look ugly - but that should be a separate feature request, to have them be skinnable or smth

You made these two suggestions...

The 1st one would go against the "The 3 input variants are scored based on your level solution" but it'd still make sense as it'd be closer to real world situation.

The second is interresting... but I didn't look to see if it was already present in the feature request.

Another way is to be able to put the custom component in a bounding box (regardless of it's actual shape) and allow an arbitrary text (instead of the file name) which would allow the ISO notation (I know that US prefer the ANSI notation), AND having a "&" label in the center of the box, OR having a ">1" label and XOR a "=1" label (circles on output marking the "inverted logic" like in ANSI)

For the rest, looks like the suggestions I made are a no-go... no need to continue to go in circle.

[raven patio]

I do sometimes consider delay in my sandbox builds, though, because it interplays with how long it takes Latency RAM to respond. And sometimes, I’m disappointed that I cannot get both simulation speed, and an efficient build score to maximize latency delay simulation for some of these simplest of concepts. I don’t feel that my idea is asking for any “magic” here, since it could reasonably be worked into being implemented during the campaign, and then scored as appropriate. 🤷🏽‍♀️

[crisp flicker]

"Magic" means "a score that cannot be build normally"

[raven patio]

Then I’m definitely not asking for that.

[crisp flicker]

Ok, but OP is

[raven patio]

Yes.

[crisp flicker]

And I am going to repeat what I said before: it's unlikely that a builtin would have a significant speed advantage, even if you use switches.

(especially if Stuffe gets around to optimizing this)

[raven patio]

I’m not expecting to have a simulation speed advantage. I’m expecting the same simulation speed, just with a lower gate/delay score than an EQ block.

[crisp flicker]

Yes

[autumn forum]

if you think that something coherent with real components is "magic", many things must be magic for you (I do take offense on your words, you've been quite offensive in your answers from the start)

[potent spindle]

if you think that something coherent with real components is "magic"
But they specifically said that's not what they mean.
They mean "a score that cannot be built normally"

[autumn forum]

Can you tell my why AND is delay 2 while you've to build it using 2 NAND with an end result delay of 4 then ? it's also "magic" !!!

if you want to be coherent, AND and OR should be 4 and NOR should be 6...

having AND, OR and NOR with delay 2 is giving trhem "score that cannot be built normally"

[gleaming mountain]

I don't feel like MegaIng has been offensive at all. He's just been straight forward with why it's unlikely that your feature request will be implemented.

Now you are free to take offense, but that does not mean he was actually offensive.

[autumn forum]

well, my request was, if you read the first post, not about delays. That part came at a latter point as one possible benefit (having delays for wider logical gates similar to the one of 2-input one like it happens with real life components)

So, yes, when people focus on something which was not my initial post and keep saying I'm unreasonnable because I'm asking for something "magic" when I point that it's something similar to REALITY (and that other parts of the program are doing the same thing instead of using the "delay from the earlier mission"), it's offensive.

I just made a suggestion related to my own experience with TC... I did not ask to be patronized or called unreasonnable repeatedly.

[gleaming mountain]

where in this conversation were you called unreasonable?

I can't find any such example

Yeah, your original post was talking about simulation speed, not delay. But MegaIng was quite clear that he does know the internals of the simulation and thinks it's unlikely that it would have any effect on the simulation speed.

[crisp flicker]

Yes, it is

Which I explicitly acknowledge before

The scoring of the 4 basic logic gates is "magic"

(or well, 3 out of those 4, one is the baseline)

The point is that we don't want more magic components

[wet anchor]

Multi-input OR / NAND gates would be a lot more common in TC builds if there wasn't the Z-coerced-to-0 behavior for input pins. Right now it's "better" (delay-wise, size-wise, wiring-effort-wise) to use switches instead of OR gates for combining multiple outputs. My most used custom component is a 1-bit switch with both inputs connected to the CC input (ie the "Buffer" from the old days), for that reason

As for the scoring discussion, the game's cost and delay calculation already doesn't correspond to real-life CMOS. In the old days the scoring was strictly based on NAND cost and delay, which was also not representative of CMOS because it pessimized NOR and XOR. I think it's fine for it to not be representative of CMOS, just that it needs to be reasonable and consistent in terms of what builds it causes people to make, which it basically is

[outer kindle]

I know that this topic is dead,
but couldn't we use memory to concatenate the values?

I mean, even if the memory is extremely slow,
the state of every wire HAS to end up in memory at some point anyway;
therefore I suggest to:

• just store (perhaps a copy of) the states of up to 8 x 1-bit wire values (as bytes) in consecutive memory addresses;
• read the entirety of that value as a 64-bit value;
• mask it (since you'd have to do that anyway);
• perform the comparison;
• and so on ...

And since this game is often run on an x86 CPU (which is a bad assumption to make, I know),
one could just use the parity flag for the N input XOR gate.

[delicate storm]

That would need a lot of memory

[outer kindle]

Would it though?
These components would be used sparingly right?
I mean, how often would one need one of these gates?

[delicate storm]

You'd be surprised how many people will use something because it's convenient

[outer kindle]

I guess.

This might be faster than executing the operation tree, right?

[delicate storm]

No clue, but probably not

[outer kindle]

I mean instead of (up to) 8 loads from (up to) 8 different memory locations,
you'd need to perform 8 additional stores (at the same time as you're storing these values anyway) and then perform a single load.