spark river
if you're dealing with a stateless component, you could design it and then say "hey TC backend - if you just evaluate this GDScript/Lua/whatever function, you can simulate this component without having to deal with all those wires"
for instance, a simple ALU is a stateless component that could be simplified down to something like
-- this defines a component called "simple_ALU" that has three inputs, A B and control, and one output, "result"
function simple_ALU(a, b, control)
if(control == 0) then
output("result", a + b)
else if(control == 1) then
output("result", a - b)
else if(control == 2) then
output("result", a * b)
-- more lines here
TC's backend would then do some testing and verify that this is accurate (this is only usable if the TC engine is able to test every single combination of inputs, or if you're willing to permit possible cheating)
then, in future, whenever TC tries to simulate the logic of this component, it can simply call the function instead of running all that logic. If the component is edited, it is re-verified.
pros:
- allows experienced players to run very complex designs quickly
cons: - updates take time
- possible security concerns if poorly contained (RCE; Stormworks had a similar problem with Lua)
- doesn't actually add any new components
alternatively: just allow people to make components using verilog, and then interpret the verilog - skip the wiring altogether and calculate gate count using the verilog itself.
maiden bronze
rugged lion
fiery sundial