viscid laurel
Hello
I have this function y = B’C’ + A’C’D’ + A’B’C + ACD’ + AB’C’ and I need to make the logic circuit of it
Τhe question is:
You have reversed and logic gates of 2 inputs with costs of: 1 for the reversed ones, 2 for the reversable gates NAND and NOR and 3 for the gates AND, OR, XOR, XNOR. Design the circuit of y with cost less or equal to 12
ashen valley
There are many optimization algorithms but they are more suited to larger equations
Here, I think you should just look for expressions you can factor out.
Work on the logic expression first, then see how to make it with gates.
If you exceed the cost, go back a step or two and then repeat the process.
Do be aware that inverting certain expressions or converting them to NAND, NOR can be one way to help with the factoring stage.
viscid laurel
Here, I think you should just look for expressions you can factor out.
Do you think an answer to this problem could be this?
((A XOR C)B')'
ashen valley
Maybe, you can write a python program to verify all the cases
I would do a sanity check before submitting it
I can't verify it off the top of my head
viscid laurel
Sanity check?
viscid laurel
Do you think an answer to this problem could be this?
((A XOR C)B')'
Also how would you draw this? I really find it difficult designing the logic system
hasty turret
did you try reducing it with kmap
y = B’C’ + A’C’D’ + A’B’C + ACD’ + AB’C’
y = B’C’ + A’C’D’ + A’B’C + ACD’
y = B’(A'C + C’) + (A’C’ + AC)D’
viscid laurel
That was the reduced
I had F(A,B,C,D) =Σ(0,2,3,4,8,9,10,14)
And I had to reduce it already with a kmap
hasty turret
good
viscid laurel
Hello
I have this function y = B’C’ + A’C’D’ + A’B’C + ACD’ + AB’C’ and I need t...
Which lead to that
hasty turret
then you can use NAND, NOR, NOT, XOR, XNOR
viscid laurel
Do you think an answer to this problem could be this?
((A XOR C)B')'
That was my thought
I don't know if it's right
hasty turret
.
y = B’(A'C + C’) + (A’C’ + AC)D’
is also
y = B’(A'C + A'C’ + AC') + (A’C’ + AC)D’
y = B’(A' + AC') + (A’C’ + AC)D’
viscid laurel
I also think that if I use 7 NOT you only count it once
viscid laurel
How do you draw it?
Is it A connecting to a not then that not to XOR
Then C connecting to a not and then that not connecting to XOR?
hasty turret
there is 2 school of taught.
Total wired gates in a simple chip
and total number of gates used (ASIC)
I can try drawing in Visio but
((A XOR C)B')' is missing D' somewhere
viscid laurel
What about ((A XOR C)B'OR D')'
Maybe like this? Really don't know
hasty turret
I would use only NOT / NAND 😄
better propagation properties
Visio only has AND
so the NOT are really NAND or NOR
11 gates
If you do less chip package, then you would want to use only NAND gates and maybe a NOT chip
like SN7400 has 4x nand-2 gates
SN7404 6x NOT gate
so you would want to use 3 chips
2x 4x NAND-2
and 1x 6x NOT 😄
viscid laurel
Thanks a lot
hasty turret
try to work it out on paper 😄