If I add another bullet to TA then I gotta remove 1 from projects
#Should I keyword farm my TA position
narrow pivot
Like idk if HR people understand what I am TAing just based off the course title
yeah tbh no clue what the course content is as digital logic is a fairly large area, VHDL? what kind of designs? simulation only or actually putting on an FPGA?
wicked fable
Oh wow i think it would be good to then because i think our course is a pretty good digital logic course. We have like 8 labs most of which are synthesized and put on an FPGA for demoing. We make a 4 bit RALU, and also introduce a bit of VHDL and assembly programming on our custom ISA
narrow pivot
I’m a bit biased because of also being compe but that description is already so much cooler than what you originally had
especially because debugging and helping students on those issues (especially VHDL) is a lot more challenging
wicked fable
especially because debugging and helping students on those issues (especially VH...
Compe!!! Are you going for hardware or swe roles
Im tryna get a verification or digital design role
narrow pivot
Compe!!! Are you going for hardware or swe roles
niceeee, going for low-level embedded or distributed systems, mostly because my experience is more in that area
digital design and architecture are really neat but unfortunately I don’t have much outside of classes for it