#!process Nvidia 2
1 messages · Page 1 of 1 (latest)
ASIC Design Verification - GPU
Yeah
SystemVerilog, C/C++
damn I lwk should have focused on verilog more but my dumbass decided to do ML
idiot
yeah I mean
I learned the hard way that picking one thing to do is better than claiming to be interested in a lot of things
i.e. just do SWE at FAANG
I have a SWE and chip design resume but both are sub-optimal
uh yes many such cases I want to do "AI", boom, math
math aint even the problem, problem is I cant pass interviews and all the AI roles want PhDs (I have MS) with 10+ yoe
yeah I mean that's kind of what I mean
you need to be a math prodigy to have signal in ML
i.e. publish
you can have a BS and "do AI" if you publish
a lot of these ML PhDs are like International Math Olympiad people
right mb
perhaps
but I heard someone say that hardware requires us citizenship at most places lmaoo
semiconductor companies also have their recruiting annoyances
also dyk what nvidia process is like? I never did it
I don't know
is it just recruiter call then phone screen then vo?
both of my first rounds are/will be engineer
SRAM CAD was vibe check -> python file I/O question (majorly bombed)
idk about this one
SRAMs are designed with CAD?
defense contractors yeah
lotta fpga shit
yes the cad tool is cadence virtuoso
but that's not what CAD engineer means colloquially
what journals
ieee
CAD engineer basically means "SWE for tools/reports etc."