#target generating invalid instructions

1 messages · Page 1 of 1 (latest)

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I'm doing some exploratory development for the original playstation with zig. Everything is fine in debug builds, but when turning on ReleaseSmall I get invalid instructions, specifically teq after a divu to check for divide by zero. teq isn't valid in the mips1 ISA and it's correctly recognized as such (I get a compile error if I try to use it as inline assembly).
I guess my question here really is is this a zig bug or an llvm bug, and how exactly can I narrow it down.

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ok I think I found it, it's not a zig issue but llvm. the difference from zigs point of view was it was emitting one of those fancy mul by a large constant to do division by a constant, vs using the divu instruction. it does feel a bit weird that it's not the other way around though

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You gotta tell LLVM the CPU features you have available, as well as just the architecture

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the -cpu option is correct, it's a bug in llvm

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huh, weird

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llvm is emitting that instruction despite it not being available with your cpu options?

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that's very odd

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mips1 has divu, all the divs add trap for div/0

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welp

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llvm strikes again :)

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but fwiw mips1 support is considered "experimental"

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Might be worth reporting it to them if there's not already a bug for it

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already done 😎

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nice c:

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working on a fix, just gotta wait for llvm and zig to compile...