What is alignment ?

[rugged crown]

Cannot understand how it works . How to play with it, what tests to run to simulate situation that will show me how it works ?

[warm patio]

this seems like a nice article to explain some things: https://en.wikipedia.org/wiki/Data_structure_alignment

[rare plank]

Short version: Alignment is the largest amount that the memory address in question is divisible by.
So, a pointer is align(4) if it points to an address that is divisible by 4.
Similarly, a variable is align(4) if it is placed at an address that is divisible by 4.

Something that is align(4) is also align(2), and align(1) too - for obvious reasons; 4 is divisible by both 2 and 1.

This applies to any alignment value; align(16) is also aligned to 8, 4, 2, and 1.

Since all alignments are powers of two generally, this fact can by relied upon.

One reason alignment can be important is that CPUs generally can do things faster if a value of size N is aligned to N.
e.g: a u32 is align(4).
Certain setups will outright crash you if the value is under-aligned, instead of just doing the access a bit slower, too.

[glad perch]

Zig isn't mentioned here

[rugged crown]

thanks everyone, didn't know you responded that fast

[hidden minnow]

This hasn't been true on commodity hardware for a decade. In some cases for vectorized instructions remains true (in the sense that they can't be run when unaligned), but for non vector instrs the x86-64 achitectures, the cost for aligned and unalgined is generally the same. Above 64 bites tjhy however may not be atomic if they cross an important boundaru (eg, a cache lone, a 128 byte boundary, or a page).

You can pack your data structs and get better performance becuse of the cache savings on architectures that are lose in this regard.

[wanton bolt]

unaligned x86_64 instructions are measurably slower than aligned instructions, and using improper alignment for instructions on many other architectures (such as AMD ARM) throw exceptions

[undone ivy]

do you mean ARM ?

[wanton bolt]

yes I did, thank you

[hidden minnow]

go check the instruction tables.I'll get them lkaer not now. same cost now

[wanton bolt]

even assuming that's true, doesn't change the fact that using instructions with incorrectly aligned data throws exceptions on architectures like ARM

[hidden minnow]

intel addressing in CPU for most is byte addressable and the loads and strore to them are even atomic when unaligend for btoh AMD and INTEL up to 64 bits, there Intel keeps thatup ahd AMD starts having issues.

[opaque hedge]

kind of, it's more that if they cross cache lines there is a cost

and aligning things has an effect of keeping things in the same cacheline

[wanton bolt]

ye, makes sense

[opaque hedge]

it's just like memory operations

you can do atomic unaligned operations on x86_64

as long as it's within one cacheline

[hollow harbor]

what's more important about alignment is that different architectures have trouble with it sometimes, and Zig code is generally expected to be portable, so having well-defined alignment is useful in that context

additionally not having any notion of alignment at the language level causes things like allocators always being forced to give you max alignment for memory even when it's a waste of bytes

allocators in Zig don't do that so the alignment information is vital for making portable libraries

[opaque hedge]

very true

but this was a remark about x86_64 specifically

I won't pretend like I know anything about ppc