#mcu keychain
1 messages Β· Page 1 of 1 (latest)
why two decoupling caps on an attiny
you should put tvs on the usb
I should have had one but idk
I really should xd
iss it bad tho?
just adds an extra part for no benefit
@nimble island Did I now make you both happy? ;)_ _
upsie
there is its wired wrongly tho xD
you should use a tvs diode that's designed for usb
do you mean for the datalines?
@nimble island Tvs like esd for the datalines or?
ya
I thought for the vbus xD
power is less critical, you're already using an LDO which is probably fine
throw on a zener if you're worried about it
I will if your worried about that xD
meh
apparently there are chips that do ESD protection for the entire thing
vbus, D+ and D-
nice neat little packages
yeah found one
now I got it what do you think?
y d1
sorry forgot it now?
idk if its discord or low resolution
not necessary to slice your ground plane under everything for 3v3
well I didnt it was kicad xD
the big blue trace
uh
drc isnt set up correctly?
or you have a bunch of violations idk
Nope gnd pour
route it out of the way lol
I don't I hope
Why tho it's an ldo or because of the pour?
its running to a decoupling cap, the extra inductance is probably fine and it means you keep a mostly solid pour underneath your chip and most of your traces
The only other way would be for it to go around the headers
so?
Well should I avoid trace contact in general or only cap contact because of the inductans
Inductance
the inductance is going to be largely nbd
Not be determined because it's so small?
Then why should I move it in the first place I mean I will but idk
π€
think about the returns
Would be bad if your had flows and return at the same time?
Yeah but what is so bad about this line?
Your returns will all need to flow around that split
whereas the other way only has power flowing around
If I move it don't they still have to flow around it? Or do you not mean the distance between the line and the copper Pour?
Oh yeah but how?
Okay well I'll try
@robust raft https://embeetle.com/#blog/return-currents
notice point 2 specifically
I think I get it you don't want me to route on the bottom layer all the time only if I really have to because the return current needs to take a long way
importantly that the high speed trace return currents need to go around the split
And that's bad isn't it?
Because it's a big way around it?
honestly
for this design, it probably does not matter at all
but its a good time to practice now while the stakes are basically zero
to answer your question, yes
Yeah it is
Did you see Maddie's design? She really did go on 2 layers to route it all I mean she layer switched often
And Daniel mentioned to put gnd vias on these spots (next to)
that design uses more than 2 layers π
I know we don't have a high speed signal but could I also do this here?
Yeah but the signals are routed there
And 2 gnd layers in
Xd
yeah you can throw return vias where they fit
And that would smaller the split wouldn't it?
But it would work hopefully
@nimble island What do you think? :)_ _
Remind me in an hour
Sorry Chris I slept and Iβm in school now xd
No worries
Good morning chris xD
Morning
Good sleep?
Never π
damn so you have school today? xD
Yeh
Im already done lol
so no school? π₯²
I had all my classes already
damn your fast chris
so watcha doing now chris?
so chris :)_ _
3d printing
i can take a look at your design
@robust raft pls run DRC before review
here you chris sorry I didnt know that it had problems tbf
theres still a bunch of clearance problems
no?
This is just the silkscreen stuff and so on
because the usbb overlapps over the edge cuts
does the clearence and so on not go with the pcb file or is something wrong?
you have clearances of like 0.1mm
yeah is that bad? I mean I needed that to route out the attiny
yes
its not manufacturable
try to keep clearances at least above 0.12, ideally around 0.16-0.2
its not??
I thought it was wth are you sure you arent confusing inches and mm or mils?
where are you getting the board manufactured and how many layers?
2 jlcpcb
hhm chris seems right
outer layer should be 1oz though, unless you order 2oz
2 layer 1oz gets you 0.1mm clearances
better to be above that whenever possible though
yeah true
I ofc directly jumped into kicad to fix this and now my clearance is 0,12mm ;)_ _ even tho 0,1mm is manufacturable its always good to be above 0,16mm wasnt that possible
0.1 mm is not readily manufacturable
its right at the edge of jlc's 2 layer capability
Min. track width and spacing (1 oz)
0.10 / 0.10 mm (4 / 4 mil)
honestly this project is doable entirely with 0.2mm trace space
π€ you k ow what just because you want to I will deliver
Know
the space between the pads of the ch340x will be under 0.2mm but thats okay
I noticed you used thicker traces for some of the power lines, they may* need to neck down for some of the finer pitch ICs
yeah I noticed thats what I wanted to ask you about because the atiny has verry small pads
https://jlcpcb.com/partdetail/16204-CL05A106MQ5NUNC/C15525
yeah seems to be avaliable
π
does it need to tho?
what would that change?
yeah its way too close to your other traces
you're routing underneath it rn
not anymore ;)_ _
the tx and rx i suppose
chris what do you think now? you will see the things you mentioned in the drc
well its okay I think because I dont use many
So everything should now be alright π
yeh
Nice π what are you up to?
procrastinating atm apparently π
@nimble island look what came yesterday :)_ _
its really smol xD
Problem now only is its getting recognised in the device manager but I dont see any output in putty
@tawny otter What do you think :D_ _
@nimble island about that it doesn't work I think π€
do you have any software flashed on it?
Nope but shouldn't there be something already on it?
no why would there be
Not like anything in the uart output?
It's now filled with nothing lol
yes
the flash will be noop
you could bridge tx and rx on the ch340 to get an echo without programming it if you just want to test that part
well the ch340 works because it show up in windwos :D_ _
@nimble island - doesn't look like it needs to be double sided assembly! π
no
damn nice
Yeah it was just a general question xd
I don't even know how to write the firmware xd
problem for later π
Problem is it's now later xd
Here @torpid wraith
I hate firmware π
do you have a rpi or arduino
Yeah both
just leave some software out to harden in the sun
you can probably use either to program it
If you want the USB port up or down :)_ _
which mcu is it
ok
Should work hopefully xd
Attiny 1616 I think
Why not just use my PC?
how are you going to connect your PC to this
if it doesn't have the arduino bootloader on it (for UART programming), you need an icsp programmer
but arduinoISP exists
so you can just use your arduino
As Chris said it doesn't have anything on it atleast that's what I see in putty
there's probably something similar for a raspi
yeah, but you can program a blank chip with an icsp programmer
even if it doesn't have the bootloader on it
How do I do that? I don't think I routed them out directly. But I think I can just use some gpio pins can I?
I will just Google this tbh
no, they have to be the specific gpios
should've planned in advance
worst case is you need some bodge wires to connect to the icsp pins
Should have xd didn't think I can't program it through is p I thought I could just use the uart but sadly not π
.....:awkwardmonkey.gif:
that's the one π
You can only program an MCU through UART if it already has a UART capable bootloader on it. A blank MCU needs the native programming pins exposed
yeah idk why but I thoughtr it was already on it xD
@robust raft you'll need to bodge a wire to reset pin
to the reset pin?
Yeh
Used for programming
Could someone look over this its verry small and not much on it so it should be fast ;)_ _