#EvalynOS

1 messages · Page 34 of 1

wide mica
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"the other parts of the memcpy slow it down" wdym

hazy saddle
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Sorry my wording is ass I haven't slept all day

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Trying to reset sleep schedule to not be total BS

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The parts of the loop where it checks alignment and other things was causing the 16b part to be slower in alot of cases when not using single byte copies

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Though some other changes I made lessened that do maybe I can just swap if back to 8b?

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Probably needs more micro benchmarking I don't want to fucking do

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And when I compile with -o3 / lto eveything just shits the floor and ends up fast as fuck anyways (but not in an invalid way)

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So some of my test methods may not be fully good since it's adhoc shoved into the kernel

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I do wonder why when it should be looping and be mostly 1:1 the gap increases instead of not on there

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But on x86 it's fine it seems

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Both ran on bare metal so no scheduling bs with VMs/tcg

dark lotus
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Omg you're still on memset 😭

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@hazy saddle For memcpy, wouldn't it be faster to use ERMS? If you're not targetting a CPU older then 2012

Atleast, that's what i do for my memcpy, I'm not sure if it's faster or slower

        __asm__ volatile("rep movsb" : "+D"(Dest), "+S"(Src), "+c"(Count) : : "memory");
hazy saddle
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Just for copies larger than 2k

dark lotus
hazy saddle
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Depends on alignments

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Look at the benchmarks for things above 2k

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And look how much it can vary

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On my 5700x

dark lotus
hazy saddle
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Above 2kb most of my workloads are going to be page copies of half pages of so

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So it's on average best to use it there iirc

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ERMS also has startup overhead too

young hamlet
hazy saddle
young hamlet
hazy saddle
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What's the instruction for doing then on GPRs?

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Also I don't really wanna make it super importable and have a bunch of ifdefs

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And I wonder if that's even appropriate for a memcpy

young hamlet
young hamlet
young hamlet
coarse oasis
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are non-temporal stores safe to do if the target is in cache?

young hamlet
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It’ll still adhere to the CC policy

hazy saddle
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I'd probably want an mfence too before returning right? And I presume only normal loads too

young hamlet
coarse oasis
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the sdm says

The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into the cache hierarchy.

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loads from wc mem might be incoherent with stores still in the wc buffer

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iirc

young hamlet
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I see, if there aren’t loads coming soon after this it should be fine though nah?

hazy saddle
young hamlet
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Like you can use a fence directly after

coarse oasis
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i mean, if i understand right, this would be broken? ```
; assume [rdi] != 0
mov eax, [rdi]
xor eax, eax
movnti [rdi], eax
mov eax, [rdi]
; eax might be != 0 because the cache line remains

young hamlet
hazy saddle
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That could be an issue with the bulk copies?

young hamlet
coarse oasis
young hamlet
hazy saddle
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I can't test it yaaar

coarse oasis
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or i'm confusing something

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i tried testing it locally with ```x86asm
global main
main:
mov eax, 0x41414141
lea rdi, [rel foo]
mov [rdi], eax
xor eax, eax
movnti [rdi], eax
mov eax, [rdi]
ret

section .data

foo: dd 0x42424242

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i think i might be confusing this with wc cacheability on pages from pat

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since there reads are treated as uc and bypass any on-cpu buffers

young hamlet
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I think that if large data copying is excessive, it may be worth it to try non temporal stores at least (loads you might still not want to use non temporal operations for to allow for the cache to prefetch data you’re copying)

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If it improves performance stick with it if not just stick with what you’re using now

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But it is probably worthwhile to look into

hazy saddle
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I think il stick with my current function

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And come back and try and fix it up more

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But it's probably fineee

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And in most cases other than super tiny ops it's alot better

hazy saddle
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Il try and maybe make a more reliable bench?

coarse oasis
young hamlet
coarse oasis
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PREFETCHNTA could help maybe?

young hamlet
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True that

hazy saddle
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😭

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and neither i or clanker can figure out why tf its doing that

tender mantle
hazy saddle
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I mean it's probably fine since release builds will want to be done with LTO anyways :p

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And it's something I fully support

hazy saddle
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i wonder if on @tawny wren's clankered riscv core thats more fancy would fare better PSP1G_pspTrollar

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since this also doesnt show in x86

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and this ends up being something that the smaller CPU struggles with predicting branches etc and crap

hazy saddle
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Okay now for me to try and get the energy to review this shit

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And commit and push

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And then fuck

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What was on my list of things to do next?

wraith star
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porting bash

hazy saddle
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I think there was one other thing than timers?

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Right it was the RBtree rework

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To save 8 bytes

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I'm also thinking about stuff like LAM

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Yes it's a cool feature

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but

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It sucks ass how I can't really use it

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On 5 level paging it wouldn't give me enough bits for what id want to use it for

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Eg I don't think it can even fit a u8?

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And it's really architecture dependant

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And even CPU dependant with paging modes

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What sucks is I can't run different parts of the address space with different paging modes

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Because the kernel could get forced to a 4 level mode

wraith star
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if you are really into saving bits, you can force pointers to be aligned and have your data in the lower bits of the pointers

hazy saddle
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But even then support is not there yet for it to be viable

hazy saddle
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Since they are all 8 byte aligned

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And rbtrees only need one bit

wraith star
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and if you are always working with kernel data structures

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you can ignore the fact that you dont have lam

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you can always or the uppers bits with 0xff...

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although this will get very shitty if you have multiple arches

hazy saddle
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The point of lam is a speed one not an embedding

tender mantle
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first thing I get when I search for intel lam lol

hazy saddle
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Just sucks it's a little not feesible to use even in userspace

tender mantle
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> the Linux kernel is now disabling LAM out of security concerns.

wraith star
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Based

hazy saddle
tender mantle
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lmfao

hazy saddle
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LAM is just stupid on x86

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As long as the page walkers aren't flexible

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Since a program can't say it wants 4/5 level paging

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Atleast then the software could be somewhat portableish

tender mantle
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> When LASS is enabled, the processor hardware monitors memory access based on the current CPU privilege level (CPL):
> User Space Access: If user-mode software attempts to access an address in the upper half (kernel space), a General Protection Fault (#GP) is generated.

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INTEL

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WHY

hazy saddle
wraith star
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i suppose for guarding against meltdown

tender mantle
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welp add another random fucking reason for general protection faults to happen

tender mantle
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the problem is raising a gp

wraith star
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eh

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just kill the user task

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as with any other #gp

tender mantle
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gps can be caused by like 40 different things atp

wraith star
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the only problem is that you wont be able to send a page fault to the process

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but whatever

tender mantle
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oh it also prevents the kernel from accessing user memory

hazy saddle
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This wouldn't be an issue if FRED added GPF source reporting

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And they do have fields to allow this btw

tender mantle
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I mean it does

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it's just error code 0 means "any generic error"

hazy saddle
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That's the issue

tender mantle
wraith star
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if fred were to report the reason for #gp you would run out of bits

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lol

tender mantle
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it's a uint64_t lol

wraith star
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breathing already is a cause for #gp

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ah okay

hazy saddle
tender mantle
hazy saddle
hazy saddle
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Sorry

tender mantle
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259

  • 1 per idt entry
  • 1 for gdt errors
  • 1 for ldt errors
  • 1 for "generic error"
hazy saddle
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Too far 😭

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Damn

tender mantle
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if you wanna count 1 per segment selector as well trl

hazy saddle
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I meant I went too far

tender mantle
clear bison
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GPF due to SMP startup trl

tender mantle
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the worst one imo

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> Executing an SSE/SSE2/SSE3 instruction that attempts to access a 128-bit memory location that is not aligned on a 16-byte boundary when the instruction requires 16-byte alignment. This condition also applies to the stack segment.

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because there is LITERALLY AN EXCEPTION CALLED "ALIGNMENT CHECK"

tawny wren
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How fast are the cores in the vf2 again?

hazy saddle
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And I mostly mean some weird asf behavior with the memset at O2

tawny wren
hazy saddle
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Where small copies progressively take wayyyy longer than a naive loop despite being the same code

tawny wren
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I don't think I'll be able to get my FPGA to beat that raw performance lol

hazy saddle
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Unless you use lto

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It's mostly relative mcycle count between two algorithms I need to see

tawny wren
tender mantle
hazy saddle
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Not easy performance

hazy saddle
hazy saddle
tawny wren
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It should

hazy saddle
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That's why I tried micro benchmarking so much

tawny wren
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It's some sifive core

tender mantle
hazy saddle
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I even put a clanker on it

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And that wouldn't work with LTO memes and other crap

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Look at the benchmarks I posted up thetr

hazy saddle
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😭

tender mantle
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I'm more curious in the actual assembly difference if it's the same code

hazy saddle
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i meant the inner loop

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that should be executing

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between the two functions being benched

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for small things

tender mantle
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yeah I have no clue, I'm eepy and this isn't making any sense

hazy saddle
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feel free to look

hazy saddle
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lmao

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i think it optimized it into the korona memcpy

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Or I mean

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A similar algorithm 😭

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Just for memset instead

tawny wren
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given what i very quickly googled about the sifive core

hazy saddle
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ah lol

tawny wren
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since its in-order multi-issue the compiler will be trying to schedule the instructions in such a way that the cpu retires as many as possible

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since the cpu wont reorder them on its own

hazy saddle
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Which is also what the korona memcpy does I think? It's basically a bunch of chunks of progressively smaller copies until it does one byte and can return

tawny wren
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itll also probably implicitly know a bit more about the core and memory and shit as well, but i wouldnt be surprised if there are other ways to make the generic one do that too since it would make sense in general i think

hazy saddle
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well time to run a benchmark

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lol that fixed it

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it still has some losses with strange non word sized alignments above 8b

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but thats fine

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since its some weird af shit to have a struct thats not word size aligned AND larger than a word size

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so it ended up just being a poopy cpu that needed an mtune flag

cyan bison
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😔

hazy saddle
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It makes my code was fine

cyan bison
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oh yay

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🎉

hazy saddle
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It's also why this didn't happen on a 5700x

cyan bison
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ill be back to chip in in a few months

hazy saddle
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Because zen3 is a good uarch

tender mantle
tender mantle
hazy saddle
tender mantle
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The cpu equivalent of hydrogen bomb vs coughing baby

cyan bison
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-# would it work on an 8086 trl

hazy saddle
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i mean

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this still has some tricks

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its still multi issue

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and its not fully weak

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a coughing baby would be a super simple core that takes many cycles to execute one opcode and has no fancy tricks

tender mantle
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2 pipelines no ooo riscv64 cpu vs god knows how many pipelines, ooo & speculative x86_64 cpu

hazy saddle
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this is more like a toddler of CPUs

tender mantle
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Oh slightly better

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What’s x86_64 then?

hazy saddle
hazy saddle
hazy saddle
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i was looking back at my riscv/la64 interrupt code

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some of the comments were a little unclear imo?

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i changed it from

    bnez t1, 1f             # branch if from kernel mode
    ld t1, 0(t0)            # load current thread pointer if from user mode
    ld sp, 0(t1)            # get kernel stack pointer
    1:                      # else proceed

to

    bnez t1, 1f             # if from usermode {
    ld t1, 0(t0)                # load current thread pointer
    ld sp, 0(t1)                # get kernel stack pointer
    1:                      # }
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commit message for tomorrow

Optimize memcpy and memset

Also make risc-v and loongarch64 interrupt comments more clear
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actually

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i dont know if i should change them?

pallid vine
hazy saddle
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And I try and keep the main message under 50 characters etc

pallid vine
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yea that makes sense

hazy saddle
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another thing ive been considering is stripping nasm as a dependancy

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and redoing things into GAS + intel synax setting