EvalynOS | Operating System Development | Page 32

clear bison Jul 7, 2026, 1:05 AM

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I'm afraid no FPU is gonna be horrible

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Or maybe not

hazy saddle Jul 7, 2026, 1:05 AM

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i mean? the kernel dosnt need FPU

clear bison Jul 7, 2026, 1:05 AM

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It can do integer ops pretty fast

hazy saddle Jul 7, 2026, 1:05 AM

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an X server is about the most heavy thing id ever wana attempt

viral bison Jul 7, 2026, 1:05 AM

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https://www.digikey.com/en/products/detail/nxp-usa-inc/MC68LC060RC50/1167437 FINALLY A GOOD DATASHEET

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THANK GOD

hazy saddle Jul 7, 2026, 1:05 AM

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the horrible part may be emulating the fpu

viral bison Jul 7, 2026, 1:06 AM

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hazy saddle the horrible part may be emulating the fpu

put it in the fpga trl

hazy saddle Jul 7, 2026, 1:06 AM

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not how that works

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it triggers an exception

viral bison Jul 7, 2026, 1:06 AM

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ah, f

clear bison Jul 7, 2026, 1:06 AM

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viral bison https://www.digikey.com/en/products/detail/nxp-usa-inc/MC68LC060RC50/1167437 FIN...

Literally what i was reading just a moment ago

hazy saddle Jul 7, 2026, 1:06 AM

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viral bison https://www.digikey.com/en/products/detail/nxp-usa-inc/MC68LC060RC50/1167437 FIN...

also https://www.nxp.com/docs/en/data-sheet/MC68060UM.pdf

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ah same thing

viral bison Jul 7, 2026, 1:06 AM

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clear bison Literally what i was reading just a moment ago

For reference: https://www.nxp.com/docs/en/data-sheet/M68040UM.pdf

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this was the older one

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you cannot even search

clear bison Jul 7, 2026, 1:07 AM

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viral bison For reference: https://www.nxp.com/docs/en/data-sheet/M68040UM.pdf

💔

hazy saddle Jul 7, 2026, 1:08 AM

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The MC68LC060 is a derivative of the MC68060. The MC68LC060 has the same execution unit and MMU as the MC68060, but has no FPU. The MC68LC060 is 100% pin compatible with the MC68060. Disregard all information concerning the FPU when reading this manual. The following difference exists between the MC68LC060 and the MC68060

The MC68LC060 does not contain an FPU. When floating-point instructions are encountered, a floating-point disabled exception is taken.

Bits 31–16 of the processor configuration register contain 0000010000110001, identifying the device as an MC68LC/EC060.

viral bison Jul 7, 2026, 1:13 AM

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wish me luck 💀

hazy saddle Jul 7, 2026, 1:13 AM

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ah they do provide the code needed for this though aparently

viral bison Jul 7, 2026, 1:13 AM

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@hazy saddle can't you find this package?

hazy saddle Jul 7, 2026, 1:14 AM

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it stopped being made in 98 💀

viral bison Jul 7, 2026, 1:14 AM

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fuuuuu

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anyway, time to go to sleep, tmr i'll make the footprint 💀

hazy saddle Jul 7, 2026, 1:30 AM

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wtf is this

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https://github.com/cschlote/amiga_mc68060sp

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the repo is an utter mess

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fpsp.s dosnt even exist

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https://www.nxp.com/search?keyword=MC68060%2520Software%2520Package%2520v.%2520P1.01&start=0&category=software

Search

NXP.com search interface.

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wtf

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💀

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is the 68060 even worth it over the 68040 atp??

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archive.org dosnt even have a proper thing of this

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@urban mulch

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look at ts

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😭

tawny wren Jul 7, 2026, 1:39 AM

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m68k port?

hazy saddle Jul 7, 2026, 1:40 AM

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tawny wren m68k port?

Custom m68k PC that's cursed as shit

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But the FPU emulation code is apparently annoying as fuck to get

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Since I'm not paying 300bucks for an m68k

tawny wren Jul 7, 2026, 1:53 AM

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hazy saddle Since I'm not paying 300bucks for an m68k

no shot a m68k is that expensive

hazy saddle Jul 7, 2026, 1:53 AM

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.

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honestly

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could it be cheaper to just FPGA the m68k seperate from the sotubridge fpga 🥀

tawny wren Jul 7, 2026, 1:58 AM

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hazy saddle could it be cheaper to just FPGA the m68k seperate from the sotubridge fpga 🥀

i mean i am pretty sure someone made a m68k softcore

hazy saddle Jul 7, 2026, 2:05 AM

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http://www.apollo-core.com/index.htm?page=family&tl=7

APOLLO 68080 - High Performance Processor

Apollo Core 68080 is a cisc CPU which is code compatible with the Motorola M68K and ColdFire families.

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this also exists

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😭

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aparently

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https://github.com/AmicableComputers/wf68k30L

GitHub

GitHub - AmicableComputers/wf68k30L: A pipelined 68030 softcore in ...

A pipelined 68030 softcore in VHDL. Contribute to AmicableComputers/wf68k30L development by creating an account on GitHub.

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and this

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I do wonder if there is anything still fucking weird / old that's 32bit with an MMU/fpu

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that could be workable for this

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And not x86

clear bison Jul 7, 2026, 2:21 AM

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hazy saddle `fpsp.s` dosnt even exist

fpsp.asm does tho

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👀

hazy saddle Jul 7, 2026, 2:22 AM

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clear bison fpsp.asm does tho

Who knows how much it's been fucked with though?

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Not to mention licencing

clear bison Jul 7, 2026, 2:23 AM

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There's no licencing problems if you change the code just enough and nobody else knows trl

hazy saddle Jul 7, 2026, 2:24 AM

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clear bison There's no licencing problems if you change the code just enough and nobody else...

Look how many lines it is

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😭

clear bison Jul 7, 2026, 2:28 AM

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I think fpsp.asm is just like a weird decompiled/obfuscated version of 68060_lib/fpuemu/*

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As that seems much more readable

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Omg i found the counterpart of mpreg, fpreg

Screenshot_2026-07-06-22-30-51-858_com.github.android.jpg

hazy saddle Jul 7, 2026, 2:34 AM

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clear bison Omg i found the counterpart of mpreg, fpreg

😭

hazy saddle Jul 7, 2026, 2:35 AM

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clear bison As that seems much more readable

I guess thoes are the original files?

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I wonder how hard porting this shit is

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If we were to do the FPU less 060

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Actually

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Genuinely

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Binder may have a good option on this

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@spark fern since we are potentially building a m68k based machine should we go with the 68040 with MMU and FPU of go with the 68060 with the MMU but no FPU and use the software emulation libraries for it.
The goal is to hopefully port my kernel and run an X server or atleast bash and some basic tools.
The SBC would be using an FPGA to emulate alot of the non CPU core things like to give it 512mb of ddr2 along with UARTS display etc etc

clear bison Jul 7, 2026, 2:42 AM

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I think binder got stuck on the 6502 era of commodore

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He didn't get to touch the Amiga

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So no m68k knowledge obviously

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trl trl trl trl trl

hazy saddle Jul 7, 2026, 2:43 AM

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clear bison So no m68k knowledge obviously

He did some m68k stuff iirc

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Or atleast talked about it somewhat

hazy saddle Jul 7, 2026, 3:46 AM

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also this is cursed and bad practise af

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but iirc since i mamage the HHDM very cleanly

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eg only ram is mapped with no overage

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i could use the HHDM for MMIO

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trl

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only issue is MMIO via HHDM would need a seperate helper due to LA64 using DMW's w/ the UC HHDM at a seperate offset

hazy saddle Jul 7, 2026, 3:48 AM

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hazy saddle also this *is* cursed and bad practise af

in theory this shouldnt have any issues, other than MMIO out of bounds on the memory map etc mmLol

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i could get the PLEN and reserve all of that

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but thats wasteful

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i could also just have a seperate allocator for managing MMIO regions in the kernel that gets a large virtual allocation and bump allocates it and refills when needed

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since virtual memory (on 64bit arches) is free, and saving some memory on vmem segments could be good

magic saffron Jul 7, 2026, 5:45 AM

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I know you're interested in the hardware stuff, but qemu has an m68k system to get you started. I believe it's system emulations are reasonably accurate to the real things too.

hazy saddle Jul 7, 2026, 5:45 AM

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magic saffron I know you're interested in the hardware stuff, but qemu has an m68k system to g...

True but 32bit is less of a priority so building hardware means I get to atleast wait a bit and have it potentially line up nicely

magic saffron Jul 7, 2026, 5:46 AM

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fair enough

hazy saddle Jul 7, 2026, 5:46 AM

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I'm probably gonna try and get scheduling to work tomorrow

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If I feel good enough

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I barely could play any games today 😭

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I am making some progress on the iotel stuff thankfully

magic saffron Jul 7, 2026, 5:46 AM

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you could be the fourth person in this server (afaik, probably not realistically) to port their kernel to m68k 😛

hazy saddle Jul 7, 2026, 5:47 AM

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magic saffron you could be the fourth person in this server (afaik, probably not realistically...

Shouldn't be too bad I presume

hazy saddle Jul 7, 2026, 5:47 AM

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hazy saddle I am making some progress on the iotel stuff thankfully

https://booping.synth.download/notes/aodrp51y6dh906oy

Evalyn (@evalyn)

Hello fedi, I haven't posted here in a while but i have something interesting.
I have been investigating something that is utterly confusing and I need others to help find samples of this happening.

A certain set of intel CPUs apparently report the CPUID vendor string as GenuineIotel with the n in intel having a singular bit flipped making it an o.

This is listed on Wikipedia leading to one singular report of this and when contacting that person directly on bsky they were unable to provide more information on this. Along with me attempting to send a patch on the LKML to handle this and also maybe see if other have more info on this.

The LKML thread is a little inactive with me waiting on further instructions on how to handle it they way they wanted (halting/panicking along with a flag to bypass)

I have found a bunch of sparse reports over online separate from the one mainly cited but they are incomplete.

I need help from other nerds online to try and see if they have proce…

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Sent this to a bunch of friends

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If it gets enough traction I can hopefully get some test subjects

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PSP1G_pspTrollar

magic saffron Jul 7, 2026, 5:47 AM

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good luck, it's an interesting thread to follow

hazy saddle Jul 7, 2026, 5:48 AM

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Probably the worst part of the m68k thing on real hardware will be larping as a 90s PC bios

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😭

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Since il have to make firmware

hazy saddle Jul 7, 2026, 5:48 AM

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magic saffron good luck, it's an interesting thread to follow

The Linux kernel one?

magic saffron Jul 7, 2026, 5:48 AM

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yeah

hazy saddle Jul 7, 2026, 5:48 AM

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Ty ;3

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Hopefully I get a reply and I can make a proper v2 patch

magic saffron Jul 7, 2026, 5:49 AM

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hazy saddle Since il have to make *firmware*

you could make the most batshit insane firmware ever ultrameme

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give it AML

hazy saddle Jul 7, 2026, 5:49 AM

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magic saffron give it AML

I would but I have nothing to use it for

magic saffron Jul 7, 2026, 5:49 AM

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make it boot limine kernels natively

hazy saddle Jul 7, 2026, 5:49 AM

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But I did want to go on a somewhat UEFIish direction

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The main crazy part will be it having a bunch of modern peripherals

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Like a 16550 UART

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SD cards

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Etc

magic saffron Jul 7, 2026, 5:49 AM

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hazy saddle SD cards

lmao

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sounds like a quirky machine

hazy saddle Jul 7, 2026, 5:50 AM

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Yup

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Will be quite funny

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But it will also try and be somewhat simple for the kernel to use

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Also 512mb of ddr2 UltraSPARC

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An FPGA will be the south bridge and handle alot of this stuff

magic saffron Jul 7, 2026, 5:51 AM

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I dont know if you've come across it yet but there was a boot protocol from the era (used by a few systems it seems) called "bootinfo".

I have this in my notes:
https://github.com/vivier/qemu-m68k/blob/m68k-virt/include/standard-headers/asm-m68k/bootinfo.h

hazy saddle Jul 7, 2026, 5:52 AM

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i was thinking of just passing a dtb™

magic saffron Jul 7, 2026, 5:52 AM

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yeah that also works

hazy saddle Jul 7, 2026, 5:53 AM

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hazy saddle <@275740677168562176> since we are potentially building a m68k based machine sho...

Btw what do you think on this

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Because this would keep the m68k it's self under 100 bucks to buy

magic saffron Jul 7, 2026, 5:53 AM

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I think summoning bindage was a big move meme

hazy saddle Jul 7, 2026, 5:53 AM

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And the other parts would maybe be 300 in total

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Meaning it could be somewhat reasonable for people to built

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😭

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verses 250 bucks for the cpu

magic saffron Jul 7, 2026, 5:55 AM

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hazy saddle Btw what do you think on this

it all sounds fine to me, just a bit anachronistic, but you're not trying to be era-faithful. If you're doing to do a direct map for the kernel maybe you want less ram?

hazy saddle Jul 7, 2026, 5:56 AM

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I mean 512m is about the limit for a direct map

magic saffron Jul 7, 2026, 5:56 AM

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or if some of it is being dedicated as vram I guess that makes sense

hazy saddle Jul 7, 2026, 5:56 AM

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And I actually will try and avoid a direct map

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Il use recursive page tables for this arches paging routines

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And other uses of HHDM will get split into using temp mappings on 32bit arches

magic saffron Jul 7, 2026, 5:57 AM

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hazy saddle Meaning it could be somewhat reasonable for people to built

that's cool, I assume you'll public all the files needed for people to build it themselves too?

hazy saddle Jul 7, 2026, 5:57 AM

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Ofc

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It is many people working on it

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But il definitely be putting out all the Firmware files etc

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Oh and the protocol will load the kernel into the upper half etc with paging ofc

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Il probably make it give page tables that

map you in the upper 256m
gives 512m of direct map
has a recursive set of page tables to use aswell

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Which should fit in the upper 1g?

hazy saddle Jul 7, 2026, 5:59 AM

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magic saffron it all sounds fine to me, just a bit anachronistic, but you're not trying to be ...

The goal is to make the most capable m68k machine (without paying 250 bucks for an old ass CPU so it may have to be a 68040 if we want FPU properly without the strange emulation library)

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And to try and make it run as much software as possible and be usable

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Eg hopefully an X server and a light DE as the final goal

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it would also be funny to have a custom IRQ controller on here but also have a standard PIT timer that can do the CPU interrupt timer and the pc speaker trl

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goal is to also make a cursed board in some ways

magic saffron Jul 7, 2026, 6:04 AM

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hazy saddle The goal is to make the most capable m68k machine (without paying 250 bucks for ...

fair, imo the 68040 is fine. I think the 060 is more of an upgrade for the peripherals than the main core?

magic saffron Jul 7, 2026, 6:04 AM

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hazy saddle Eg hopefully an X server and a light DE as the final goal

that'd be cool

hazy saddle Jul 7, 2026, 6:04 AM

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magic saffron fair, imo the 68040 is fine. I think the 060 is more of an upgrade for the perip...

The 060 bumped the core up to pentium levels iirc

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With the FPU falling behind still

magic saffron Jul 7, 2026, 6:05 AM

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hmm I see

hazy saddle Jul 7, 2026, 6:05 AM

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The firmware I also want to have a menu for configuring boot and other things because it could be cool to get Linux working + a dual boot

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Since the firmware would handle ext2 natively

hazy saddle Jul 7, 2026, 6:06 AM

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hazy saddle The firmware I also want to have a menu for configuring boot and other things be...

Maybe it could also control some other system stuff / do POSTs

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Which is probably useful to do tbh on such old of a CPU

hazy saddle Jul 7, 2026, 7:27 AM

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If anyone wishes to test if they have the ioteld cpu they can simply run this command on Linux
awk -F': *' '/^vendor_id/ {print $2}' /proc/cpuinfo | sort | uniq -c | awk '{print $2 ": " $1}'

viral bison Jul 7, 2026, 11:43 AM

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hazy saddle The goal is to make the most capable m68k machine (without paying 250 bucks for ...

i would like to know which one then, lol

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bc they have different pinouts

spark fern Jul 7, 2026, 1:30 PM

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hazy saddle <@275740677168562176> since we are potentially building a m68k based machine sho...

for general purpose use? I'd do the 68060. you don't need FP for lots of things. If you know you are going to do FP then the 68040

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my first 486 did all soft float and was quite usable

spark fern Jul 7, 2026, 1:47 PM

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is this a full super scalar with multiple pipelines?

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is the fpga going to run so fast that it really doesn't matter?

viral bison Jul 7, 2026, 1:47 PM

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yes

hazy saddle Jul 7, 2026, 1:48 PM

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spark fern is the fpga going to run so fast that it really doesn't matter?

It should be able to pump enough data definitely

hazy saddle Jul 7, 2026, 1:49 PM

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spark fern for general purpose use? I'd do the 68060. you don't need FP for lots of thin...

Yeah seems like that would be the choice then, hopefully finding and integrating the FP lib routines agent too bad

spark fern Jul 7, 2026, 1:49 PM

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reference... I ran linux + xwindows in a 25mhz 486 with no fpu

spark fern Jul 7, 2026, 1:49 PM

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hazy saddle Yeah seems like that would be the choice then, hopefully finding and integrating...

https://aminet.net/package/util/libs/SoftIEEE ?

hazy saddle Jul 7, 2026, 1:51 PM

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hazy saddle https://github.com/cschlote/amiga_mc68060sp

this is what i ended up finding

spark fern Jul 7, 2026, 1:52 PM

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I wouldn't imagine they would be hard to find

hazy saddle Jul 7, 2026, 1:52 PM

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it was mentioned in the manual, was annoying to find anythibg beyond that

spark fern Jul 7, 2026, 1:53 PM

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could probably also rip them out of linux/bsd

hazy saddle Jul 7, 2026, 2:04 PM

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true, hopefuly the licencing on thoes is fine

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eded up missing some things when doing la64 exception names abd decancering them

viral bison Jul 7, 2026, 2:04 PM

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thankfully this pinout doesn't see so bad

hazy saddle Jul 7, 2026, 2:04 PM

#

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some of the names 🥀

viral bison Jul 7, 2026, 2:07 PM

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@spark fern do you think this is mirrored?

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the pinout i mean

spark fern Jul 7, 2026, 2:08 PM

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viral bison <@275740677168562176> do you think this is mirrored?

I'm the wrong person for those sorts of questions

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I wouldn't be surprised if the LLM couldn't whip up vaguely decent soft float routines

hazy saddle Jul 7, 2026, 2:09 PM

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thank you for the help btw

hazy saddle Jul 7, 2026, 2:09 PM

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spark fern I wouldn't be surprised if the LLM couldn't whip up vaguely decent soft float ro...

true , esp with the source of the other things

spark fern Jul 7, 2026, 2:09 PM

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https://github.com/ucb-bar/berkeley-softfloat-3

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pure C soft float

viral bison Jul 7, 2026, 2:10 PM

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bruh it's flipped

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why

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WHY do they do that

spark fern Jul 7, 2026, 2:10 PM

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maybe so you can 'look' at the pint while it's in the socket?

viral bison Jul 7, 2026, 2:11 PM

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normally in datasheets they show from the top only

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it makes it less confusing

spark fern Jul 7, 2026, 2:12 PM

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I haven't looked at hardware specs much

viral bison Jul 7, 2026, 2:21 PM

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oh god i hate how they placed the data pins

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thanfully we are using an fpga

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so we can mix and match the data lines

spark fern Jul 7, 2026, 2:22 PM

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have you picked the fpga yet?

viral bison Jul 7, 2026, 2:22 PM

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yes

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https://www.digikey.it/en/products/detail/efinix-inc/T35F400C3/15861258

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this one

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https://www.efinixinc.com/docs/trion20-ds-v4.3.pdf

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comes with DDR3 / LPDDR3 / LPDDR2 driver block too

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and LVDS

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and SPI

spark fern Jul 7, 2026, 2:24 PM

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not familiar with that line

viral bison Jul 7, 2026, 2:25 PM

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chose it bc of price, amount of cells, features and gpios

spark fern Jul 7, 2026, 2:25 PM

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31k LE

viral bison Jul 7, 2026, 2:25 PM

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ye

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it was the highest in this price range

spark fern Jul 7, 2026, 2:28 PM

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you writing your own HDL impl?

viral bison Jul 7, 2026, 2:28 PM

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we have to, lol

spark fern Jul 7, 2026, 2:28 PM

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why?

viral bison Jul 7, 2026, 2:29 PM

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well, i don't existing hdl code exists for this

spark fern Jul 7, 2026, 2:29 PM

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can at least start with the tg68k

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or wf68k30

viral bison Jul 7, 2026, 2:29 PM

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?

spark fern Jul 7, 2026, 2:30 PM

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there was talk about an port of apollo...

viral bison Jul 7, 2026, 2:30 PM

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we using a real cpu

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not fpga that acts as an m68k

spark fern Jul 7, 2026, 2:30 PM

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OH

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kk, that is different

hazy saddle Jul 7, 2026, 2:31 PM

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spark fern there was talk about an port of apollo...

if the softfloat stuff was not feesible maybe but it should be
the FPGA mainly is goung to be a southbrdge to a real CPU if we can

spark fern Jul 7, 2026, 2:31 PM

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https://www.apollo-computer.com/v4standalone.php

Explore the next-generation Amiga-compatible technology

We revive the Amiga with a clear roadmap. Learn more about how do we want to bring you Amiga back. Here is a complete list of our Vampire project goals. Today you can discover what matters to Amiga users around the world. We know how to make Amiga great again. Share your ideas with us and help to make that Amiga dream come true.

viral bison Jul 7, 2026, 4:25 PM

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footprint done

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gg

opaque marten Jul 7, 2026, 6:41 PM

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no.

hazy saddle Jul 7, 2026, 6:42 PM

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opaque marten no.

Too late sorry

opaque marten Jul 7, 2026, 6:42 PM

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nooo

wanton grove Jul 7, 2026, 7:55 PM

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yes

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i386

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!

clear bison Jul 7, 2026, 7:57 PM

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💀 💀 💀

hazy saddle Jul 7, 2026, 7:58 PM

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wanton grove i386

death

viral bison Jul 7, 2026, 10:25 PM

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oh god so many unknown pins

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@hazy saddle what do we use the UPA pins for?

hazy saddle Jul 7, 2026, 10:25 PM

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Idk 😭

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What do they do

viral bison Jul 7, 2026, 10:25 PM

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User-defined signals, controlled by the corresponding user attribute bits from the
address translation entry.

hazy saddle Jul 7, 2026, 10:26 PM

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I guess extra things for page tables?

viral bison Jul 7, 2026, 10:27 PM

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i'm still reading the docs, there are 20 pins i have never heard of 💀

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i'm gonna ask clanker

hazy saddle Jul 7, 2026, 10:27 PM

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These could be used to overlay MMIO ontop of normal ram right?

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And translate differently on the FPGA

viral bison Jul 7, 2026, 10:28 PM

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prob

hazy saddle Jul 7, 2026, 10:28 PM

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Eg get more than 4gb of physical address space

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Probably should wire them into the FPGA for later

viral bison Jul 7, 2026, 10:28 PM

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i'll wire them in anyway

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we have more than enough pins

hazy saddle Jul 7, 2026, 10:28 PM

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Could also be used to map a page as returning hard wired zeros?

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Or other useful things

viral bison Jul 7, 2026, 10:29 PM

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💀

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why does this even exist

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oh, prob bc you can reset from sw?

hazy saddle Jul 7, 2026, 10:29 PM

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What's the max amount of ram we could attach to the FPGA?

hazy saddle Jul 7, 2026, 10:29 PM

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viral bison oh, prob bc you can reset from sw?

Yeah

viral bison Jul 7, 2026, 10:30 PM

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hazy saddle What's the max amount of ram we could attach to the FPGA?

x16, lemme check what that means

hazy saddle Jul 7, 2026, 10:31 PM

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This is for the 68060 one right

viral bison Jul 7, 2026, 10:31 PM

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8Gbit

viral bison Jul 7, 2026, 10:31 PM

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hazy saddle This is for the 68060 one right

yes

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so 1Gbyte of ram

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we are limited to only 512MB with ddr2

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but 1GB with ddr3 / lpddr3

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and i think the best method would be to just solder the ddr3 IC

hazy saddle Jul 7, 2026, 10:33 PM

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Well we are using ddr2 anyways

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Since ddr3 is too hard to wire right

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And with only 512mb of ddr2,

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We won't need UPAs for that specifically

viral bison Jul 7, 2026, 10:34 PM

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ddr3 and ddr2 are very similar

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if i just solder the ddr3 chip it should be easier

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oh wait

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we cannot even use the full sodimm module 💀

#

we can only use a quarter

#

sticks use a 64 bit bus

#

we only have 16 bits

hazy saddle Jul 7, 2026, 10:37 PM

#

Then we need to make our own custom sockets

#

mmLol

#

And custom sticks

viral bison Jul 7, 2026, 10:37 PM

#

we could only use 2 sticks

#

or well

#

ICs srry

#

and they are 30 bucks each (if we don't steal them from sticks)

hazy saddle Jul 7, 2026, 10:37 PM

#

Can't we fit some ICs on a tiny board with a connector

viral bison Jul 7, 2026, 10:38 PM

#

i mean, we can just connect the whole sodimm and only use a quarter XD

hazy saddle Jul 7, 2026, 10:38 PM

#

But that would what a 2gb sodimm?

viral bison Jul 7, 2026, 10:38 PM

#

we can use any size i think

#

if we go like that

#

tho we would only be able to use /4 of it

hazy saddle Jul 7, 2026, 10:38 PM

#

But then we can only use a quarter?

viral bison Jul 7, 2026, 10:39 PM

#

ye

hazy saddle Jul 7, 2026, 10:39 PM

#

We would want 512m ram

#

We would also loose bandwith I presume

viral bison Jul 7, 2026, 10:39 PM

#

not really

hazy saddle Jul 7, 2026, 10:40 PM

#

https://www.newegg.com/a-tech-ddr2-laptop-memory-ram-2gb-ddr2-800-cas-latency-cl6/p/0RM-0032-004N2?item=9SIAMBVK019529

A-Tech 2GB DDR2 800MHz SODIMM PC2-6400 Non-ECC Unbuffered CL6 1.8V ...

Buy A-Tech 2GB DDR2 800MHz SODIMM PC2-6400 Non-ECC Unbuffered CL6 1.8V 200-Pin SO-DIMM Laptop Notebook Computer RAM Memory Upgrade Module with fast shipping and top-rated customer service. Once you know, you Newegg!

#

We can just use a stick like this?

viral bison Jul 7, 2026, 10:40 PM

#

ye

#

even ddr3l is possible tbh

#

it's only 200 mhz faster

hazy saddle Jul 7, 2026, 10:40 PM

#

I'd ask Emma 😭

viral bison Jul 7, 2026, 10:40 PM

#

@urban mulch

#

lol

#

tho we could reach 2GB of ram if we spend 60 bucks for the single ICs

#

or steal some from sticks

#

and it should be safer than using sodimm

hazy saddle Jul 7, 2026, 10:43 PM

#

We don't want 2gb ram though

#

Just 512m

viral bison Jul 7, 2026, 10:43 PM

#

why not use the full 2gb tho?

#

if we can get it

hazy saddle Jul 7, 2026, 10:44 PM

#

You said only a quarter could be used

#

Also thoes extra PTE pins may not work nice with the cache

viral bison Jul 7, 2026, 10:44 PM

#

extra PTE pins?

#

oh the UPAs?

hazy saddle Jul 7, 2026, 10:47 PM

#

Yes

viral bison Jul 7, 2026, 10:49 PM

#

hazy saddle Yes

well, here it is

#

x2 of these and we get 512MB

#

also, we can upgrade these later bc most ram ICs are pin to pin compatible

hazy saddle Jul 7, 2026, 11:23 PM

#

viral bison x2 of these and we get 512MB

We should probably still have a mini socket for these

viral bison Jul 7, 2026, 11:23 PM

#

hazy saddle We should probably still have a mini socket for these

that would require another pcb

hazy saddle Jul 7, 2026, 11:23 PM

#

How many pins do these need

#

PSP1G_pspTrollar

viral bison Jul 7, 2026, 11:23 PM

#

hazy saddle Jul 7, 2026, 11:24 PM

#

viral bison that would require another pcb

It could probably fit on a tiny cheap 2230 nvme right?

viral bison Jul 7, 2026, 11:24 PM

#

VDDs and VSSs can be grouped

#

NCs mean no connected

viral bison Jul 7, 2026, 11:24 PM

#

hazy saddle It could probably fit on a tiny cheap 2230 nvme right?

wdym

hazy saddle Jul 7, 2026, 11:24 PM

#

viral bison wdym

Like

#

Use that connector and form factor

#

But for socket able memory

viral bison Jul 7, 2026, 11:24 PM

#

prob yes

#

but it is more costly

#

like prob around 30 bucks for the extra pieces and pcb

hazy saddle Jul 7, 2026, 11:25 PM

#

It's both extra cursed and extra cool because it makes upgrading easier

#

And you can fit some extra things on the modules

#

To identity how much ram it has

#

The firmware could poke a register on the FPGA to check the ram size based on the modules reporting

#

Make it a little more PC like

#

mmLol

viral bison Jul 7, 2026, 11:27 PM

#

if you like the extra price sure

hazy saddle Jul 7, 2026, 11:28 PM

#

true

#

Idk

viral bison Jul 7, 2026, 11:57 PM

#

@hazy saddle for interrupts, we only have this in the cpu

#

should we get a PIC if it can be connected? trl

hazy saddle Jul 7, 2026, 11:58 PM

#

viral bison should we get a PIC if it can be connected? <:trl:829316641191886888>

FPGA PSP1G_pspTrollar

viral bison Jul 7, 2026, 11:58 PM

#

true trl

#

fuck it, every pin is going to that fpga

hazy saddle Jul 7, 2026, 11:58 PM

#

I wanted to actually make a custom really simple IRQ controller

#

But use the PIT timer

viral bison Jul 7, 2026, 11:59 PM

#

tho, would we have enougn LEs to actually make all that hardware, lol

sterile plank Jul 7, 2026, 11:59 PM

#

whatchu guys doing

viral bison Jul 7, 2026, 11:59 PM

#

hazy saddle But use the PIT timer

PIT inside fpga too?

hazy saddle Jul 7, 2026, 11:59 PM

#

hazy saddle I wanted to actually make a custom really simple IRQ controller

A register for interrupts pending
A register to ACK them
And a register to finish the current interrupt and only send another if things are pending

viral bison Jul 7, 2026, 11:59 PM

#

sterile plank whatchu guys doing

something very cursed

sterile plank Jul 7, 2026, 11:59 PM

#

which is..

viral bison Jul 7, 2026, 11:59 PM

#

viral bison Jul 7, 2026, 11:59 PM

#

sterile plank which is..

m68k + modern hardwarer

sterile plank Jul 7, 2026, 11:59 PM

#

viral bison

woow a footprint of bga

sterile plank Jul 8, 2026, 12:00 AM

#

viral bison m68k + modern hardwarer

cool

#

good luck

viral bison Jul 8, 2026, 12:00 AM

#

sterile plank woow a footprint of bga

pga

sterile plank Jul 8, 2026, 12:00 AM

#

viral bison pga

whatever I'm not electronics person

viral bison Jul 8, 2026, 12:02 AM

#

also @hazy saddle we gonna get usbc power delivery too XD

#

bc it might be the only way we can get that much power via usb

#

i could add a battery module too if you want trl

hazy saddle Jul 8, 2026, 12:25 AM

#

viral bison i could add a battery module too if you want <:trl:829316641191886888>

Nah that's too expensive 😭

#

Maybe for a v2

#

PSP1G_pspTrollar

#

V1 should try and be cheap

viral bison Jul 8, 2026, 12:26 AM

#

hazy saddle Nah that's too expensive 😭

nah, battery stuff is like a few bucks

#

batteries are expensive tho

hazy saddle Jul 8, 2026, 12:26 AM

#

Let's leave that for making it a handheld 💀

viral bison Jul 8, 2026, 12:26 AM

#

XD

clear bison Jul 8, 2026, 1:27 AM

#

Oh my god

#

https://klipy.com/gifs/higuruma-jujutsu-kaisen-1

Klipy

Higuruma Jujutsu Kaisen

▶ Play video

viral bison Jul 8, 2026, 1:31 AM

#

clear bison Oh my god

lol

#

we making it way more cursed

hazy saddle Jul 8, 2026, 1:32 AM

#

viral bison we making it way more cursed

Meh

#

I need to work on actual kernel shit anyways now

#

Tomorrow if I don't feel poopy 😭

#

Maybe we could move the talk about this bullshit elsewhere

viral bison Jul 8, 2026, 1:33 AM

#

hazy saddle Maybe we could move the talk about this bullshit elsewhere

open a new project specific thread

hazy saddle Jul 8, 2026, 1:33 AM

#

It's not project specific though

viral bison Jul 8, 2026, 1:33 AM

#

it kinda is tho

hazy saddle Jul 8, 2026, 1:33 AM

#

Atleast at this point anyways

#

We can just use osdev3

hazy saddle Jul 8, 2026, 7:11 AM

#

hazy saddle I need to work on actual kernel shit anyways now

me when i forgot to setup timers

#

PSP1G_pspTrollar

#

so i cant do sched rn

#

yaaar

#

well

#

i can make the code

#

and maybe test it ig

#

but it wont be able to preempt

hazy saddle Jul 8, 2026, 7:28 AM

#

Me when loongarch64 isn't bullshit and has a CPUID to tell you if the timer is constant and to tell you the frequency of it and setting up the timer to give interrupts isn't annoying shit

#

I mean it can still be non constant ig 💀

#

But I think I could just panic on that case?

#

Since there wouldn't be any other way to reliably get time

#

For riscv I'm gonna need more dtb shit

#

😭

#

I'm also going to have to modify CPUlocal to store a self pointer (to the fixed region)

#

That way you can lock a lock etc

hazy saddle Jul 8, 2026, 8:09 AM

#

Okay yeah I'm going to need to add helpers to get pointers that go into CPU local to handle spinlocks there

hazy saddle Jul 8, 2026, 8:28 AM

#

lmao

#

another common gcc L

#

😭

#

this only compiles via clang

#

Oh yeah I'm also gonna skip having it in the fixed CPU local

#

Interrupts are disabled here anyways

#

And for getting the current thread generically il just implement an assembly function anyways

#

I only really need the fixed CPU local for things touched by assembly that also has no temps

#

Which is only the current thread pointer

#

And not the spinlock

hazy saddle Jul 8, 2026, 8:31 AM

#

hazy saddle Which is only the current thread pointer

And this has an easy way to implement it arch generically

#

Il still need the pointer helpers though etc

hazy saddle Jul 8, 2026, 1:02 PM

#

#

Ended up reworking alot more of the CPU local

#

But scheduling works

#

And it should just work with preemption™

#

Oh also it works for all the architectures

#

PSP1G_pspTrollar

#

@tender mantle

#

If you want to steal the scheduling code too

#

You can

#

For your riscv port

hazy saddle Jul 8, 2026, 1:07 PM

#

hazy saddle

Also scheduling is init properly before any memory management because of hyena sky

#

So it will have a thread marked active etc

hazy saddle Jul 8, 2026, 2:32 PM

#

Honestly I still have more refactors I wana do on this

#

Because of some half stupid decisions

#

I'm probably gonna push this

#

Do some GDT/IDT refactors

#

And some other various things

wraith star Jul 8, 2026, 2:33 PM

#

gdt refactor ok?

hazy saddle Jul 8, 2026, 2:33 PM

#

So the GDT stuff can working On APs

hazy saddle Jul 8, 2026, 2:34 PM

#

wraith star gdt refactor ok?

gdt refactor..... pending/async task

#

Main thing is having architecture spesisifc fixed CPU local is kind of stupid

#

And at this point only serves to save 16 bytes on x86

#

At the cost of some BULLSHIT with the abstractions

#

Still partly more expensive for things outside of the fixed region

#

But that's fine for shit like the GDT

#

Or like things that aren't too much needed to be ultra fast

#

if I properly make the fixed region generic other shit would be better

signal plaza Jul 8, 2026, 3:30 PM

#

hazy saddle Also scheduling is init properly before any memory management because of hyena s...

Multithreaded hhdm construction?? troll

hazy saddle Jul 8, 2026, 3:30 PM

#

signal plaza Multithreaded hhdm construction?? <:troll:796858892985434152>

The point is so you can safely use mutexes

#

Iirc @urban vale advocates for this alot. And I think I did it right?

signal plaza Jul 8, 2026, 3:32 PM

#

hazy saddle The point is so you can safely use mutexes

Interesting

#

I'm starting to get back into osdev again so I'll certainly reference the code trl

#

Although I hope to get through task switching without needing to steal anything...

hazy saddle Jul 8, 2026, 3:39 PM

#

signal plaza Although I *hope* to get through task switching without needing to steal anythin...

I mean

#

It's really simple

#

😭

#

I would just give it to you

signal plaza Jul 8, 2026, 3:44 PM

#

Lol I'm pretty sure that the reason Serpyntyne wouldn't task switch was something dumb

#

Ideally it'll disappear when I write task switching code again

hazy saddle Jul 8, 2026, 3:46 PM

#

; rdi = pointer to store old stack pointer at
; rsi = new stack pointer
arch_thread_switch:
    push rbx
    push rbp
    push r12
    push r13
    push r14
    push r15

    ; swap stacks
    mov [rdi], rsp
    mov rsp, rsi

    ; unlock the scheduler spinlock
    mov dword [gs:rel fixed_cpu_local + 24], 0

    ; enable interrupts
    sti

    pop r15
    pop r14
    pop r13
    pop r12
    pop rbp
    pop rbx
    ret

#

plus this to setup a fresh stack to be able to get switched to

wide mica Jul 8, 2026, 3:46 PM

#

big scheduler lock 💀

hazy saddle Jul 8, 2026, 3:46 PM

#

wide mica big scheduler lock 💀

its per cpu?

#

and its RR

wide mica Jul 8, 2026, 3:47 PM

#

why do you have it

#

why not a thread lock

#

actually

#

why does the queue lock protect the thread state

hazy saddle Jul 8, 2026, 3:47 PM

#

The amount of time the thing is locked is so tiny it dosnt really matter?

wide mica Jul 8, 2026, 3:48 PM

#

I'm not sure this is right

signal plaza Jul 8, 2026, 3:48 PM

#

hazy saddle ```x86asm ; rdi = pointer to store old stack pointer at ; rsi = new stack pointe...

Literally the code I had 💀

hazy saddle Jul 8, 2026, 3:48 PM

#

wide mica I'm not sure this is right

This is what was in my old kernel

#

And it was working

#

And it's what solved several race conditions

signal plaza Jul 8, 2026, 3:48 PM

#

I suspect I was setting them to have the same stack or something

hazy saddle Jul 8, 2026, 3:48 PM

#

Wtf

hazy saddle Jul 8, 2026, 3:49 PM

#

wide mica I'm not sure this is right

Well then what would you propose

wide mica Jul 8, 2026, 3:49 PM

#

typically to protect a thread switching out from its own stack u have a per thread lock

#

that you hold when you try to run into

#

sec

#

CPU0: thread goes to sleep
CPU0: queue lock is held
CPU0: switch():
CPU0: do whatever with regs

CPU1: thread wakes back up on another CPU
CPU1: acquire queue lock
CPU1: switch():
CPU1: do whatever with regs
CPU0: queue lock released
OOPS! CPU0 and CPU1 race on thread state

#

u cant do this unless you pin a thread to a CPU I believe

hazy saddle Jul 8, 2026, 3:55 PM

#

I'm think sure that lock was mostly to prevent it interrupting it's self which was something that was helping? Also since the queue is per CPU aswell this shouldn't happen?

#

When would you want to lock and unlock the thread specifically in this sequence though

#

On a switch to and then unlock after you swap stacks?

wide mica Jul 8, 2026, 3:57 PM

#

you take a thread lock when switching to it, you release it when switching from it

wraith star Jul 8, 2026, 3:58 PM

#

^

#

you release the lock after you have switched stacks

hazy saddle Jul 8, 2026, 4:00 PM

#

Ah so unlock prev lock next

#

im gonna take a nap then change that

wraith star Jul 8, 2026, 4:02 PM

#

hmm, actually

#

does a thread lock even make sense

#

i think it will deadlock

wide mica Jul 8, 2026, 4:02 PM

#

why

hazy saddle Jul 8, 2026, 4:02 PM

#

yeah i was thinking of that too

wraith star Jul 8, 2026, 4:02 PM

#

isnt it better to lock the runqueue

#

if you want to lock, lock the information regarding blocking

wide mica Jul 8, 2026, 4:03 PM

#

can you explain the deadlock

hazy saddle Jul 8, 2026, 4:03 PM

#

wraith star isnt it better to lock the runqueue

this is what i already do mmLol

wide mica Jul 8, 2026, 4:03 PM

#

I have per-thread locks and all the blocking paths dont require some kind of dispatcher/runqueue lock

#

because I do the windows 7 thing where you have transition states for a thread

wraith star Jul 8, 2026, 4:04 PM

#

let me check what i have done and think a little bit

#

because i genuinely forgot

#

hmm, i use two locks: one lock for the runqueue, and another lock for the task state/blocking information (aka, which wait queue i am on)

#

when scheduling, lock the runqueue, pick next task, switch to it, unlock runqueue
the task lock is taken when changing the state (waking up, blocking), and when it is taken, shortly the runqueue lock is taken too for enqueuing or dequeuing

#

what do u do @wide mica ?

wide mica Jul 8, 2026, 4:17 PM

#

wraith star when scheduling, lock the runqueue, pick next task, switch to it, unlock runqueu...

when preemption is required, take the queue lock and get the current thread, release the queue lock, acquire the current thread's lock, acquire the queue lock and insert the current thread back into a queue, release the queue lock, then switch into the next thread, which drops the current thread's lock

wraith star Jul 8, 2026, 4:19 PM

#

how do you get the next thread?

wide mica Jul 8, 2026, 4:24 PM

#

wraith star how do you get the next thread?

I have a per-cpu next thread field which is set when preemption is required (on timeslice or higher priority thread arrival)

wraith star Jul 8, 2026, 4:25 PM

#

okay, but i suppose those threads are in a list or smth

wide mica Jul 8, 2026, 4:26 PM

#

yeah, the clock() function is a DPC enqueued on timeslice timer expiry which sets the cpu.next_thread field, then after DPC dispatch I check whether or not cpu.next_thread is null, if it's not then I switch to it

#

when selecting a thread to run I hold both the current thread's lock and the queue lock

#

the next thread thing is very clever, I stole it from MINTIA which stole it from NT

hazy saddle Jul 8, 2026, 4:28 PM

#

I mean mine should work since no two things should have access to the thread struct.
It will only be in one CPU run que at a time and it won't be eligible for changing CPUs if it's in a running state. And the lock is only released when it's all proper?

wraith star Jul 8, 2026, 4:28 PM

#

i just dont understand why you take task locks for scheduling

#

unless your kernel is capable of letting tasks deque other tasks which are possibly in execution

wide mica Jul 8, 2026, 4:31 PM

#

wraith star unless your kernel is capable of letting tasks deque other tasks which are possi...

not sure what that means

#

also the thread priority is updated under its lock

#

so i have to take it

hazy saddle Jul 8, 2026, 4:32 PM

#

wraith star i just dont understand why you take task locks for scheduling

I don't? I just protect the queue when things in it are in use. Bring the new current thread and the previous thread (which would probably cause issues if I don't have a way to signal it being not in use)

#

Oh yeah I do need a lock

#

I'm just too tired to know the proper spots to take and release them without deadlocking bullshit

wraith star Jul 8, 2026, 4:33 PM

#

why does recalculating the thread priority require you to lock the task?

hazy saddle Jul 8, 2026, 4:34 PM

#

If the previous thread happens to get taken by another core

#

Another core could be modifying it's state switching away from it

wraith star Jul 8, 2026, 4:34 PM

#

i guess it depends on where you recalculate the priority

wide mica Jul 8, 2026, 4:34 PM

#

wraith star why does recalculating the thread priority require you to lock the task?

the thread priority is updated under its lock

hazy saddle Jul 8, 2026, 4:34 PM

#

I need to lock the threads when I start to do the things

#

Then unlock after

urban vale Jul 8, 2026, 5:27 PM

#

wraith star why does recalculating the thread priority require you to lock the task?

You need to lock it to stop it from changing where it is right now

#

(On a queue, attached to the NextThread link, not on a queue, etc)

wide mica Jul 8, 2026, 5:28 PM

#

urban vale (On a queue, attached to the NextThread link, not on a queue, etc)

will btw i fixed a race in my scheduler and i think i found one in yours unless it's intentional

urban vale Jul 8, 2026, 5:29 PM

#

urban vale You need to lock it to stop it from changing where it is right now

Depending where it is, you might need to move it around. For example to unlink it from a priority queue and link it to the one for the new priority

urban vale Jul 8, 2026, 5:29 PM

#

wide mica will btw i fixed a race in my scheduler and i think i found one in yours unless ...

What is it

wide mica Jul 8, 2026, 5:29 PM

#

sec

wraith star Jul 8, 2026, 5:31 PM

#

well, ig what locks you have to take or not depends on your kernel

#

in mine i dont have a use yet for a task lock to be taken during scheduling, however, there is a lock that is taken when waiting on a waitqueue or waking those tasks

wide mica Jul 8, 2026, 5:36 PM

#

urban vale What is it

https://github.com/xrarch/mintia2/blob/main/OS/Executive/Ke/KeDispatch.jkl#L639-L646 you compare against prb.CurrentThread which is not protected by anything u hold here, this could happen:
load CurrentThread = T just before a switch commits, T exits, the switch releases T's lock, the reaper frees T, then the deref lands on freed memory.

#

importantly this is because prb can be remote

#

ig it would be unlikely but it is racy

urban vale Jul 8, 2026, 5:37 PM

#

The ready queue lock is held

#

of the processor

#

So there shouldn't be a race there

wide mica Jul 8, 2026, 5:38 PM

#

but you modify CurrentThread without holding the queue lock

urban vale Jul 8, 2026, 5:39 PM

#

Where

wide mica Jul 8, 2026, 5:39 PM

#

KepSwitchThread is called without the queue held no?

#

https://github.com/xrarch/mintia2/blob/main/OS/Executive/Ke/KeDispatch.jkl#L1518-L1553

#

here

#

you'd have to move the current thread update under the queue lock ig or just not load remote CPU current threads

#

what i ended up doing is only relying on the stashed atomic thread priority

#

actually the coolest way to fix this would be to make the thread zone type-stable memory

#

it's still racy but worst case is that it's stale

urban vale Jul 8, 2026, 5:56 PM

#

The right solution i think is to use the stashed current thread priority & interactivity thing

#

Not sure why I wasn't

wide mica Jul 8, 2026, 5:56 PM

#

yeah

#

I believe making thread structures type stable is useful for other stuff though, like checking if a mutex owner is running without racing on freed memory

urban vale Jul 8, 2026, 5:59 PM

#

Relying on type stability only sounds good to me for stuff that is permanent anyway like pfndb

#

Otherwise I'd like to keep everything fluid

wide mica Jul 8, 2026, 6:01 PM

#

I agree that it doesn't sound good but I've seen a bunch of kernels do it at least for thread structures it seems

urban vale Jul 8, 2026, 6:01 PM

#

Which ones

wide mica Jul 8, 2026, 6:01 PM

#

Probably assuming that it won't grow unbounded without running out of memory from other stuff first

#

I've seen it in freebsd at least, which is where I learned the trick

#

https://github.com/apple-oss-distributions/xnu/blob/main/osfmk/kern/thread.c#L261-L262

#

xnu also does it, i think that is what they call sequestering

urban vale Jul 8, 2026, 6:12 PM

#

I mean I'm pretty sure they do eventually free the physical memory after some epoch has passed or something

wide mica Jul 8, 2026, 6:13 PM

#

Not from what I've read

#

Unless you mean XNU then maybe

urban vale Jul 8, 2026, 6:15 PM

#

They both do SMR pretty sure

wide mica Jul 8, 2026, 6:16 PM

#

yea but that is unrelated

#

that's for lock-free data structures

#

https://github.com/apple-oss-distributions/xnu/blob/main/osfmk/kern/zalloc.c#L6776-L6782

#

I dont understand what it's all doing but it doesnt seem to free here

#

this is freebsd

urban vale Jul 8, 2026, 6:20 PM

#

wide mica that's for lock-free data structures

How are lock free data structures unrelated to lock free data structures

wide mica Jul 8, 2026, 6:21 PM

#

They don't read the thread structs in a read critical section through SMR

#

And the thread zones are not marked SMR anyway

humble scroll Jul 8, 2026, 6:51 PM

#

wide mica https://github.com/apple-oss-distributions/xnu/blob/main/osfmk/kern/zalloc.c#L67...

sequestering is a security thing designed to protect against cross-zone attacks

wide mica Jul 8, 2026, 6:51 PM

#

is it similar to type-stable memory?

urban vale Jul 8, 2026, 7:49 PM

#

@wide mica I'm going to fix that race by grabbing ready queue lock while setting CurrentThread probably

wide mica Jul 8, 2026, 7:50 PM

#

both approaches work

#

lock might be better for accuracy tho

urban vale Jul 8, 2026, 7:51 PM

#

wel there's a problem, it matters whether the current thread is the idle thread at thread insertion time

#

because any thread should preempt the idle thread, even another thread at idle priority which normally can't preempt anything

wide mica Jul 8, 2026, 7:53 PM

#

mhm you're right

urban vale Jul 8, 2026, 7:57 PM

#

I need to redesign that code a little

#

That's a coexisting related problem

wide mica Jul 8, 2026, 7:59 PM

#

urban vale wel there's a problem, it matters whether the current thread is the idle thread ...

this is a temporary issue and will get fixed by work stealing tho

#

for other cpus

dense hare Jul 8, 2026, 7:59 PM

#

hi

#

Are there any Repo link?

hazy saddle Jul 8, 2026, 8:00 PM

#

dense hare Are there any Repo link?

https://git.evalyngoemer.com/evalynOS/evalynOS

dense hare Jul 8, 2026, 8:01 PM

#

Interresting. Which Features does it have?

hazy saddle Jul 8, 2026, 8:01 PM

#

dense hare Interresting. Which Features does it have?

Why not look at the code

#

PSP1G_pspTrollar

#

It's pretty basic rn due to the rewrite

dense hare Jul 8, 2026, 8:02 PM

#

I mean i am not against viewing the code but i think it should have been written in README file

#

like any normal Project

hazy saddle Jul 8, 2026, 8:02 PM

#

dense hare I mean i am not against viewing the code but i think it should have been written...

I mean, it's a work in progress

dense hare Jul 8, 2026, 8:02 PM

#

Cause i am not sure i will understand any of this

hazy saddle Jul 8, 2026, 8:02 PM

#

It's just a basic overview and some instructions

dense hare Jul 8, 2026, 8:03 PM

#

(WARNING: Because not an OS Developer)

hazy saddle Jul 8, 2026, 8:03 PM

#

@wraith star I wonder what I should be doing to fix the lock issues

urban vale Jul 8, 2026, 8:03 PM

#

wide mica this is a temporary issue and will get fixed by work stealing tho

No i think it's a major responsiveness issue

hazy saddle Jul 8, 2026, 8:03 PM

#

I am still like partly unable to understand this after my nap wahhgone

#

And my brain loves to be slow somtimes

wide mica Jul 8, 2026, 8:04 PM

#

urban vale No i think it's a major responsiveness issue

you should add better load averaging btw for load balancing

#

i sent a freebsd patch for this

viral bison Jul 8, 2026, 8:05 PM

#

my threads get reassigned to another cpu when they get switched, i need to fix it too, lol

#

i'll add a balancer thread

urban vale Jul 8, 2026, 8:05 PM

#

wide mica you should add better load averaging btw for load balancing

send a mintia2 patch

wide mica Jul 8, 2026, 8:05 PM

#

unironically i will

wraith star Jul 8, 2026, 8:09 PM

#

hazy saddle <@576071248933683250> I wonder what I should be doing to fix the lock issues

well, as i said, depends on how your kernel works

hazy saddle Jul 8, 2026, 8:09 PM

#

yaaar

viral bison Jul 8, 2026, 8:10 PM

#

hazy saddle <a:yaaar:1352763344142073946>

send it to claude or codex trl

hazy saddle Jul 8, 2026, 8:11 PM

#

viral bison send it to claude or codex <:trl:829316641191886888>

Bruh

wraith star Jul 8, 2026, 8:11 PM

#

sometimes it also comes down to feel meme

viral bison Jul 8, 2026, 8:11 PM

#

hazy saddle Bruh

i mean, they might be able to point you in the correct direction

wide mica Jul 8, 2026, 8:11 PM

#

what a horrible idea

#

you learn nothing and you dont understand your own code anymore

viral bison Jul 8, 2026, 8:11 PM

#

i don't mean to make them make code

#

just point you in the right location to look

#

and then you fix it yourself

hazy saddle Jul 8, 2026, 8:12 PM

#

i know where it is

tender mantle Jul 8, 2026, 8:12 PM

#

you should beable to solve this problem without any ai at all

hazy saddle Jul 8, 2026, 8:12 PM

#

the scheduler

#

i know what files this deals with

viral bison Jul 8, 2026, 8:12 PM

#

oh scheduler 💀

#

bruuhh, i hate real hw xhci

urban vale Jul 8, 2026, 8:13 PM

#

I got bored of copy pasting mintia2 code at Claude and asking it what it thinks because it just kept going "This is a very well engineered piece of code, part of a sophisticated operating system kernel, that accounts for every case. One thing to flag: the comment above line 21 may not be completely up to date. On second thought, it is."

wide mica Jul 8, 2026, 8:15 PM

#

does your company pay claude

wraith star Jul 8, 2026, 8:15 PM

#

https://klipy.com/gifs/peter-griffin-gif

Klipy

Peter Griffin and Friends' Surprised Reaction

▶ Play video

#

how will feels rn

hazy saddle Jul 8, 2026, 8:16 PM

#

half the time i deal with a clanker the thing is so incompetent i have to do it myself

urban vale Jul 8, 2026, 8:16 PM

#

why not post the gif that family guy is parodying

#

https://klipy.com/gifs/memes-rap-battle

Klipy

Memes Rap Battle Reaction

▶ Play video

wraith star Jul 8, 2026, 8:16 PM

#

i find the petter griffin one funnier

wide mica Jul 8, 2026, 8:16 PM

#

ai is only good at basic refactors and to help explain stuff imo

gentle quest Jul 8, 2026, 8:16 PM

#

urban vale I got bored of copy pasting mintia2 code at Claude and asking it what it thinks ...

copy pasting is probably not super useful , but if you throw a high effort model at the entire code base and ask for an html report it will make a relatively decent thing

viral bison Jul 8, 2026, 8:17 PM

#

wide mica ai is only good at basic refactors and to help explain stuff imo

and finding bugs

wide mica Jul 8, 2026, 8:17 PM

#

maybe if u use fable or something

viral bison Jul 8, 2026, 8:17 PM

#

nah, even 5.5

#

it helped me to find a deadlock that was preventing my os from booting in real hw

prime marten Jul 8, 2026, 8:18 PM

#

do you use ai like claude for bug fixing or idea generation?

wraith star Jul 8, 2026, 8:18 PM

#

i gotta say that claude is pretty good at creating websites with all the best and whistles

prime marten Jul 8, 2026, 8:18 PM

#

how does that work, you send your project in some format that llm can understand?

wide mica Jul 8, 2026, 8:18 PM

#

wraith star i gotta say that claude is pretty good at creating websites with all the best an...

yeah see the css it made me https://rdmsr.github.io

#

i gave it a bunch of cool designs

urban vale Jul 8, 2026, 8:19 PM

#

viral bison it helped me to find a deadlock that was preventing my os from booting in real h...

No offense but your project is probably really simple

viral bison Jul 8, 2026, 8:19 PM

#

true

wide mica Jul 8, 2026, 8:19 PM

#

prime marten how does that work, you send your project in some format that llm can understand...

typically you have agents that read your files for you if you wanna do that kinda stuff

prime marten Jul 8, 2026, 8:20 PM

#

is it like 1 agent per file

wide mica Jul 8, 2026, 8:20 PM

#

no the agent reads files one by one

viral bison Jul 8, 2026, 8:20 PM

#

or uses grep

#

@hazy saddle Checking for libarchive >= 3.3.3 via pkg-config ... libarchive.pc file not found, exiting.

gentle quest Jul 8, 2026, 8:21 PM

#

prime marten how does that work, you send your project in some format that llm can understand...

the llm has access to your filesystem, you tell it what you want, it then runs bash with all sorts of commands like find, grep, etc. then reads files it wants to understand what you need further

wide mica Jul 8, 2026, 8:22 PM

#

the only thing I'll praise LLMs for is learning tbh

#

it's been very useful to me

urban vale Jul 8, 2026, 8:22 PM

#

They know very little about my interests

wide mica Jul 8, 2026, 8:22 PM

#

i meant for school too

#

like to generate quizzes before the exam, clarify things, etc

viral bison Jul 8, 2026, 8:23 PM

#

and find resources online

craggy narwhal Jul 8, 2026, 8:24 PM

#

prime marten do you use ai like claude for bug fixing or idea generation?

Recently at work, I had to solve a problem for an important client. They had a lot of code written in Rust and Python, and a little in C. I know C well, but not Python, so Copilot came in handy for quickly getting up to speed on certain parts.

viral bison Jul 8, 2026, 8:26 PM

#

Evalyn pls add a list of packages that needs to be installed in the os

hazy saddle Jul 8, 2026, 8:26 PM

#

viral bison Evalyn pls add a list of packages that needs to be installed in the os

It uses jinx

viral bison Jul 8, 2026, 8:26 PM

#

it will fault if you don't have libssl or libarchive installed

hazy saddle Jul 8, 2026, 8:26 PM

#

You need it's deps

#

And it says that in the readme

#

It links to jinx

#

And that lists shit

viral bison Jul 8, 2026, 8:27 PM

#

it doesn't say those libs in there 💀

hazy saddle Jul 8, 2026, 8:27 PM

#

What are you even doing that's faulting

viral bison Jul 8, 2026, 8:28 PM

#

it was missing libarchive and libssl

prime marten Jul 8, 2026, 8:29 PM

#

craggy narwhal Recently at work, I had to solve a problem for an important client. They had a l...

but would claude be able to solve a kernel level problem

viral bison Jul 8, 2026, 8:29 PM

#

I: Configuring ifupdown...
I: Configuring libc-bin...
I: Configuring ca-certificates...
I: Base system installed successfully.
make: *** [Makefile 17 bootstrap] Error 1

#

is this correct?

hazy saddle Jul 8, 2026, 8:29 PM

#

What command started that

viral bison Jul 8, 2026, 8:30 PM

#

make bootstrap

hazy saddle Jul 8, 2026, 8:30 PM

#

Idfk then

#

Works on my machine

#

Jinx uses containers

viral bison Jul 8, 2026, 8:31 PM

#

and make run does fail

#

bc it cannot find limine.h

hazy saddle Jul 8, 2026, 8:32 PM

#

Yeah because bootstrap failed

#

🥀

#

And you need to run get deps

#

Which that runs

viral bison Jul 8, 2026, 8:32 PM

#

it doesn't even tell me why it failed 💀

hazy saddle Jul 8, 2026, 8:32 PM

#

And the bootstrap gets other things needed to make isos

#

Idfk how to help

viral bison Jul 8, 2026, 8:32 PM

#

f

hazy saddle Jul 8, 2026, 8:45 PM

#

wide mica ``` CPU0: thread goes to sleep CPU0: queue lock is held CPU0: switch(): CPU0: do...

would removing the currently running thread from the queue fix this?
eg when switching to a task its popped off the list. and then after switching the previous thread is popped back on then it unlocks?

#

that way the queue when unlocked can never contain threads in progress/running?

haughty acorn Jul 8, 2026, 8:45 PM

#

hazy saddle would removing the currently running thread from the queue fix this? eg when swi...

this is what i do and it works ok

viral bison Jul 8, 2026, 8:45 PM

#

same

hazy saddle Jul 8, 2026, 8:46 PM

#

it would also make sense since for mutexes they shouldnt be in the run queue

haughty acorn Jul 8, 2026, 8:46 PM

#

a thread can only be in the run queue if its in the ready state

#

in my kernel

hazy saddle Jul 8, 2026, 8:46 PM

#

issue would be moving the current thread there, and knowing to not move it back when putting in a mutex then rescheduling?

wraith star Jul 8, 2026, 8:48 PM

#

i keep the task in the queue because it eliminates complexity

#

if you are the highest priority process, next_task() will be yourself

haughty acorn Jul 8, 2026, 8:48 PM

#

i do a slightly weird thing and smuggle the old thread pointer through to the new thread and then the post-context switch part of yield/threadstart uses that pointer and some flags smuggled through to update the old thread's state after it stops being current so current doesnt become invalid

#

my yield also has a force flag and if thats false it does a peek first, and if the peek is lower priority it just aborts the yield. if force is true and youre still highest prio itll get requeued by the idle thread

hazy saddle Jul 8, 2026, 8:49 PM

#

i mean. thread needs to block -> puts that in the state -> but in mutex qeue -> calls reshcedule -> it ends up in both the runqeue and the mutex qeue

wraith star Jul 8, 2026, 8:50 PM

#

well, when you put in the mutex queue, dequeue yourself

haughty acorn Jul 8, 2026, 8:50 PM

#

yeah just dont put it in the runqueue?

wraith star Jul 8, 2026, 8:50 PM

#

and also disable irqs/put yourself to dispatch ipl

hazy saddle Jul 8, 2026, 8:50 PM

#

hazy saddle would removing the currently running thread from the queue fix this? eg when swi...

this would be whats putting it back

#

when you switch away from the task

wraith star Jul 8, 2026, 8:50 PM

#

have a task status

#

TASK_BLOCKED or whatever

haughty acorn Jul 8, 2026, 8:50 PM

#

you have a flag for what the new task state is yeah

#

and only push back on if new state is ready

wraith star Jul 8, 2026, 8:51 PM

#

imo, the scheduler should not care about task statuses in other places other than the after switch call

haughty acorn Jul 8, 2026, 8:51 PM

#

putting on the wait queue would set that to blocked so the status isnt ready and thus it doesnt get put back on the runqueue

hazy saddle Jul 8, 2026, 8:52 PM

#

So I should have task running and task blocked and task ready?

wide mica Jul 8, 2026, 8:52 PM

#

i have zombie and terminated too

clear bison Jul 8, 2026, 8:52 PM

#

Q eysknso oz l,o9$8 zozl

wide mica Jul 8, 2026, 8:52 PM

#

and selected

#

when it'll run next

haughty acorn Jul 8, 2026, 8:52 PM

#

(theres a nuance to this that @wide mica can probably find the video about where you need a pending block status to work around race conditions if the wait is aborted)

wraith star Jul 8, 2026, 8:52 PM

#

maybe collapse task running with task ready if you don't really care about what tasks are executing in a given moment

clear bison Jul 8, 2026, 8:52 PM

#

clear bison Q eysknso oz l,o9$8 zozl

What

#

Tf did i type

haughty acorn Jul 8, 2026, 8:52 PM

#

wide mica and selected

i have this too

wide mica Jul 8, 2026, 8:53 PM

#

haughty acorn (theres a nuance to this that <@379432087620550658> can probably find the video ...

yeah the win 7 thing

haughty acorn Jul 8, 2026, 8:53 PM

#

yeah

#

but yeah the bottom line is it wont be on both wait and run queues because youll know from its status that it isnt ready to run and cant go onto the run queue

wraith star Jul 8, 2026, 8:54 PM

#

and overall, the scheduler itself shouldn't be doing enqueues and dequeues to any sort of runqueues

#

have the task blocking code do the enqueues and dequeues, have the task creating code do the enqueues

haughty acorn Jul 8, 2026, 8:54 PM

#

apart from the post-yield callback anyway

#

in case of manual yield or preempt

wraith star Jul 8, 2026, 8:55 PM

#

yeah

haughty acorn Jul 8, 2026, 8:56 PM

#

a task goes onto a run queue when its wait finishes, it is created, or its switched away from without blocking. it goes onto a wait queue when it starts waiting. and it goes onto a cleanup queue when terminated depending on how exactly you do that

#

i personally call it a ready queue instead of a run queue because its a queue of ready threads but naming is a personal decision so you do you

hazy saddle Jul 8, 2026, 8:57 PM

#

so i should modify this to take in the thread_t*s them self, then call a function on the new stack that will manage the run queue based on thread states and then return

#

and that should fix this??

haughty acorn Jul 8, 2026, 8:57 PM

#

hazy saddle so i should modify this to take in the `thread_t*`s them self, then call a funct...

yes exactly

#

exactly that

wraith star Jul 8, 2026, 8:57 PM

#

https://github.com/AtieP/taratos/blob/418ae10946a5687e33a1f31ace8490c091158909/kernel/src/task/sched.c#L75 if you do it properly, a sched loop looks exactly like this

#

the preempt needed probably looks a bit sus

hazy saddle Jul 8, 2026, 8:58 PM

#

I also keep redoing my CPU local partly because it's kinda borked for some shit 😭

haughty acorn Jul 8, 2026, 8:58 PM

#

(there is more complexity later about priority inversion and temporary boosting and other such fun details but what atie and i describe is a perfectly functional priority-round-robin scheduler)

wraith star Jul 8, 2026, 8:59 PM

#

yeah

hazy saddle Jul 8, 2026, 8:59 PM

#

haughty acorn yes exactly

The main issue now is that the run queues can be inconsistent with the previous thread inside of it and causing races

haughty acorn Jul 8, 2026, 8:59 PM

#

hazy saddle The main issue now is that the run queues can be inconsistent with the previous ...

how so?

hazy saddle Jul 8, 2026, 8:59 PM

#

This should also work with priorities anyways right?,

haughty acorn Jul 8, 2026, 8:59 PM

#

yeah it works with prio

#

it just doesnt handle starvation

hazy saddle Jul 8, 2026, 8:59 PM

#

wide mica ``` CPU0: thread goes to sleep CPU0: queue lock is held CPU0: switch(): CPU0: do...

@haughty acorn

haughty acorn Jul 8, 2026, 9:00 PM

#

or whatever its called when a low prio thing cant function because a high prio thing exists

hazy saddle Jul 8, 2026, 9:00 PM

#

haughty acorn it just doesnt handle starvation

I mean that's a separate issue

haughty acorn Jul 8, 2026, 9:00 PM

#

yeah thats what i meant. this handles priorities but not that

hazy saddle Jul 8, 2026, 9:00 PM

#

Oh I'm just trying to handle the race condition rn 😭

haughty acorn Jul 8, 2026, 9:00 PM

#

hazy saddle <@121733282676211714>

you put current thread in a cpulocal and not in the queue and i still dont see what the race is here?

#

you can release the queue lock in the post-yield

#

(oh and you also call the post-yield function as part of threadstart for this to work, the idea is that the beginning of threadstart looks like the post-swap part of context switch)

hazy saddle Jul 8, 2026, 9:02 PM

#

haughty acorn you put current thread in a cpulocal and not in the queue and i still dont see w...

Oh no I haven't fixed that yet

#

Current thread also still exists in the queue

#

Along with the previous one etc

haughty acorn Jul 8, 2026, 9:02 PM

#

oh thats the issue

#

only ready-to-run threads should be in the queue

hazy saddle Jul 8, 2026, 9:02 PM

#

yeah

haughty acorn Jul 8, 2026, 9:02 PM

#

current should be a separate var

hazy saddle Jul 8, 2026, 9:02 PM

#

it is mostly just not removed from the list

haughty acorn Jul 8, 2026, 9:03 PM

#

that way when you push you can detect priority preempt conditions, you dont have to worry about whether to remove from list because it already was when it started running, etc

hazy saddle Jul 8, 2026, 9:03 PM

#

yeah, after swapping stacks prev gets pushed if needed and the new current is popped

haughty acorn Jul 8, 2026, 9:04 PM

#

well youd pop new current before swapping stacks

#

so you have it and know what stack to swap to

#

the prev thread gets left in limbo as a local smuggled through the stack swap in a register

wide mica Jul 8, 2026, 9:05 PM

#

haughty acorn you put current thread in a cpulocal and not in the queue and i still dont see w...

the problem is the thread can wake back up

#

you have to have some kind of mechanism for the thread to stop swapping its stack

haughty acorn Jul 8, 2026, 9:07 PM

#

wide mica the problem is the thread can wake back up

in my setup then the waker detects that its in wait_pending instead of wait_committed and changes its state back to ready (pending any waitany/waitall details) and the post-yield detects that and requeues it

#

the post-yield does a cmpxchg expecting wait_pending to wait_committed and if the old was instead ready then it queues it back up

wide mica Jul 8, 2026, 9:08 PM

#

that's not what I'm referring to

#

i believe

haughty acorn Jul 8, 2026, 9:08 PM

#

then what are you referring to?

#

because thats the only case i can think of where a thread would be woken when not already post-stack-swap

wraith star Jul 8, 2026, 9:09 PM

#

in mine, waits and wakes are mutually exclusive by a spinlock in the task struct, and when waiting, the lock is held until after the context switch

haughty acorn Jul 8, 2026, 9:09 PM

#

i tried that and got deadlocked lmao

wraith star Jul 8, 2026, 9:09 PM

#

how?

haughty acorn Jul 8, 2026, 9:09 PM

#

i think my code was just shit

wide mica Jul 8, 2026, 9:09 PM

#

wraith star in mine, waits and wakes are mutually exclusive by a spinlock in the task struct...

that is literally what i said you should do

#

and people keep roasting me

#

😭

wraith star Jul 8, 2026, 9:10 PM

#

where

#

lmao

#

now?

#

or before

wide mica Jul 8, 2026, 9:10 PM

#

no

#

i said you have a per thread lock u hold until the switch is done

hazy saddle Jul 8, 2026, 9:13 PM

#

wide mica i said you have a per thread lock u hold until the switch is done

eg thread->switch_lock?

wide mica Jul 8, 2026, 9:13 PM

#

just thread->lock

haughty acorn Jul 8, 2026, 9:13 PM

#

wraith star how?

oh i remember now my thing deadlocked because of a nested lock caused by trying to wake it from an interrupt handler running on the same core

wide mica Jul 8, 2026, 9:13 PM

#

you could have an atomic bool as well ig

hazy saddle Jul 8, 2026, 9:13 PM

#

eh i still think there are other issues with thr run qeeue i need to fix

wraith star Jul 8, 2026, 9:13 PM

#

haughty acorn oh i remember now my thing deadlocked because of a nested lock caused by trying ...

someone didn't disable irqs :^)

haughty acorn Jul 8, 2026, 9:14 PM

#

wraith star someone didn't disable irqs :^)

when i did that the irq got completely dropped instead of delayed 😭

wraith star Jul 8, 2026, 9:14 PM

#

what is the IRQ were talking about

haughty acorn Jul 8, 2026, 9:15 PM

#

nvme command queue

#

the apic just completely forgot the interrupt instead of waiting when i disabled interrupts, even when i used TPR instead of cli/sti

wraith star Jul 8, 2026, 9:15 PM

#

uh

haughty acorn Jul 8, 2026, 9:15 PM

#

i still dont know why it happened and its 80% of why my motivation to keep working on my kernel is at a low

wraith star Jul 8, 2026, 9:16 PM

#

that's not good

haughty acorn Jul 8, 2026, 9:16 PM

#

correct!

wide mica Jul 8, 2026, 9:16 PM

#

This is why you have DPCs

wraith star Jul 8, 2026, 9:16 PM

#

are you doing eoi somewhere where you shouldn't?

haughty acorn Jul 8, 2026, 9:16 PM

#

wide mica This is why you have DPCs

i did that and started getting use-after-frees like crazy that i still dont understand

#

my entire sched and dpc and irq handling needs help badly

haughty acorn Jul 8, 2026, 9:17 PM

#

wraith star are you doing eoi somewhere where you shouldn't?

at the end of the interrupt handler? after the main handler body runs

#

as i say i still dont know what i fucked up and ended up just taking time off and now im in side-project-land with zaml instead of trying to debug this hell

wraith star Jul 8, 2026, 9:17 PM

#

for edge interrupts, the eoi has to be at the beginning

urban vale Jul 8, 2026, 9:17 PM

#

Was gus named after this cat @wide mica https://www.freebsddiary.org/cats/gus.php

The cats - Gus

wraith star Jul 8, 2026, 9:18 PM

#

otherwise you miss new irqs

haughty acorn Jul 8, 2026, 9:18 PM

#

wraith star for edge interrupts, the eoi has to be at the beginning

are msi/x edge or level?

wraith star Jul 8, 2026, 9:18 PM

#

msis are always edge

haughty acorn Jul 8, 2026, 9:18 PM

#

ok that is likely at least part of the issue

wide mica Jul 8, 2026, 9:19 PM

#

urban vale Was gus named after this cat <@379432087620550658> https://www.freebsddiary.org/...

idk but fun fact, the allocator and gus thing is by the ULE guy too

#

his coolness has no limits

haughty acorn Jul 8, 2026, 9:19 PM

#

at least its one msi per queue so repeat vs delay/combined nvme interrupts are idempotent

#

but yeah when i make more progress on or get bored of zaml ill go back to my thing and fix this shit lmao

hazy saddle Jul 8, 2026, 9:31 PM

#

btw this means i dont need a lock on the thread qeueue since the threads being swapped can never be grabbed?

haughty acorn Jul 8, 2026, 9:32 PM

#

the swapping ones cant but multiple can be queued at once possibly

#

(if say a semaphore or something like that gets a bunch released at once)

wide mica Jul 8, 2026, 9:34 PM

#

hazy saddle btw this means i dont need a lock on the thread qeueue since the threads being s...

you do need a lock on the queues for remote enqueues

hazy saddle Jul 8, 2026, 9:35 PM

#

i mean only have the lock when its activly being modified

#

but that would fuck with alot of crap

#

since it would unlock and regrab right after anyways

hazy saddle Jul 8, 2026, 9:56 PM

#

Okay now I just wana cleanup my CPU local things

#

Because the previous stuff worked fine

#

But the schedular changes some things up

#

And it's a bit messy rn

#

#

Then blocking would just a preempt disable, set to blocked, add current thread to queue enable preemption then reschedule

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@wide mica @wraith star @haughty acorn thanks for the help

wraith star Jul 8, 2026, 10:01 PM

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if you wake up from irq context, be careful

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np

hazy saddle Jul 8, 2026, 10:07 PM

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wraith star if you wake up from irq context, be careful

How might that break?

wraith star Jul 8, 2026, 10:08 PM

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disable preempt won't be enoug

hazy saddle Jul 8, 2026, 10:08 PM

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Ig then mutexes need to disable IRQs when operating on them

wide mica Jul 8, 2026, 10:12 PM

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wraith star disable preempt won't be enoug

it can be if you use DPCs/softirq/bh/whatever

urban vale Jul 8, 2026, 10:12 PM

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hazy saddle Ig then mutexes need to disable IRQs when operating on them

no

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Yeah this is precisely what DPCs are for

wide mica Jul 8, 2026, 10:13 PM

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you typically NEVER wanna take a lock from an irq context unless it's some pathological case where you have no choice

hazy saddle Jul 8, 2026, 10:13 PM

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I guess il learn how to do thoes once I do mutexes

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Since I have other crap to do

haughty acorn Jul 8, 2026, 10:14 PM

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hazy saddle <@379432087620550658> <@576071248933683250> <@121733282676211714> thanks for the...

np

hazy saddle Jul 8, 2026, 10:14 PM

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Like making the CPU local layout non arch specific and paging reworks and some userspace things and timers

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I'm probably gonna make structs for each subsystem to put into the CPU local thing, this will also make accessing parts of it much faster since it's always a fixed offset for the core kernel things

haughty acorn Jul 8, 2026, 10:15 PM

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hazy saddle I guess il learn how to do thoes once I do mutexes

DPCs are just a queue of callbacks that get run asap with preempt disabled but not in an irq context

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theyre p easy

hazy saddle Jul 8, 2026, 10:16 PM

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Then drivers that need extra CPUlocal can do that seperate with the slower helpers

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Actually I can solve that by just adding an extra data pointer to the timing system for the drivers that activate to have extra data for them

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Holy fuck I over engineered the CPU local badly

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😭

haughty acorn Jul 8, 2026, 10:17 PM

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(DPCs can be cpu-local or agnostic depending how you do them, if you schedule one from a thread you just run it immediately if you schedule one from an irq you run it as soon as you finish irq handling and turn irqs back on)

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(the only DPC quirk is scheduling one from a dpc or onto a specific cpu from a different cpu but those arent hard to handle)

wide mica Jul 8, 2026, 10:18 PM

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guys APC or DPC which is the best
APC could be a strong contender since like every kernel has them pretty much (maybe not linux idk) + they're slick, stealthy and cool
but DPCs are pretty cool too and more useful i feel like, its like a good friend you can always rely on

haughty acorn Jul 8, 2026, 10:18 PM

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both tbh

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they are different™

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and both are useful

wraith star Jul 8, 2026, 10:18 PM

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imagine having dpcs

wide mica Jul 8, 2026, 10:18 PM

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noo this is vibes debate

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obviously they're different meme

wraith star Jul 8, 2026, 10:19 PM

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and imagine having apcs

haughty acorn Jul 8, 2026, 10:19 PM

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i like dpc vibes better because theyre easier to implement

hazy saddle Jul 8, 2026, 10:21 PM

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my cpu local code also was broken on la64 bwcause half of it ended up with riscv assembly syntax and i never noticed it

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😭

haughty acorn Jul 8, 2026, 10:23 PM

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F

hazy saddle Jul 8, 2026, 10:29 PM

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Welp time to fix ts

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And have a partly working scheduler

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Well it won't be fully working until SMP on all architectures and I handle shoot downs and other bullshit

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And thread migrations

hazy saddle Jul 9, 2026, 4:33 AM

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?????????

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lmfao

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it was LTO tossing out my cpu local

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😭

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I wonder if that was also causing other bullshit

hazy saddle Jul 9, 2026, 5:39 AM

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I'm gonna have to clean this up tomorrow

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And then implement the timer subsystem

viral bison Jul 9, 2026, 5:31 PM

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symbol + footprint done

hazy saddle Jul 10, 2026, 2:06 AM

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tis should be correct

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im just finnalizing my scheduling sutff and cpu local reworks

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it goes schedule() -> arch_thread_switch() -> schedule_finalize() -> arch_thread_switch()

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and the arch_thread_switch does the final unlock and then restores things

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i keep the lock held the entire time even if i dont FULLY need it

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since locking unlocking and relocking and then unlocking would be dumb :p

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and doing the unlock in assembly generates less instrictions than needing to use CPU_LOCAL_GET_SCHED_LOCK_PTR() etc

magic saffron Jul 10, 2026, 7:36 AM

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hazy saddle i keep the lock held the entire time even if i dont FULLY need it

you'll probably want it in the future when you implement blocking.

hazy saddle Jul 10, 2026, 11:03 AM

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magic saffron you'll probably want it in the future when you implement blocking.

In what way? Since the thread being blocked means it just gets dropped from the main thread queue since it should have been put into the mutex queue etc and then set to blocked

magic saffron Jul 10, 2026, 11:05 AM

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hazy saddle In what way? Since the thread being blocked means it just gets dropped from the ...

depending on your design it might be fine, but there's potential for race condiitons around waking a thread that is transitioning to blocking or is in the middle of a context switch.

hazy saddle Jul 10, 2026, 11:06 AM

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I think I solved thoes kinds of race conditions by making sure the thread is only in the scheduler queue if it's eligible to be scheduled

magic saffron Jul 10, 2026, 11:08 AM

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if the thread isnt locked during context switch it might commit to a wait: but before it can complete it's context switch another cpu can satisfy the wait and wake the thread. The waking cpu places it in a run queue somewhere or it may preempt on the waking cpu and begin running immediately.

hazy saddle Jul 10, 2026, 11:10 AM

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Ah this shouldn't be able to happen since the thread is owned by one thing at once here, eg it won't be in the schedule queue and the wait queue at the same time

magic saffron Jul 10, 2026, 11:11 AM

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right but what if its in the wait queue and currently executing (has committed to a wait but not yet switched to the next thread).

hazy saddle Jul 10, 2026, 11:13 AM

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the current thread would be refered to by the current thread in cpu local, if its status is blocked it wont get added to the main qeueue, and grabbing a mutex would disable preemption to not race on thoes operations

magic saffron Jul 10, 2026, 11:14 AM

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yeah you wouldnt have this issue on UP, its an issue where one cpu wakes a thread was preparing to sleep on another.

hazy saddle Jul 10, 2026, 11:15 AM

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so it should be fine™

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it will prolly be a bit til i implement shootdowns and other things anyways like that

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since im gonns wait for riscv and la64 smp for that

young hamlet Jul 10, 2026, 11:36 AM

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hazy saddle tis should be correct

What if you get preempted in between the time you get the lock for the core your task is on and grab the lock

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And another core steals the task calling schedule / the task calling schedule gets push migrated

hazy saddle Jul 10, 2026, 11:36 AM

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schedule() runs with IRQs disabled?

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thats an irq lock

young hamlet Jul 10, 2026, 11:37 AM

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Is it only called with interrupts/preemption disabled

hazy saddle Jul 10, 2026, 11:37 AM

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also getting the lock is a single instruction

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or at the very least should be impodent to not cause issues

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since it either just gets tp and does a single add on riscs

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or first loads the self pointer on x86

young hamlet Jul 10, 2026, 11:41 AM

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hazy saddle also getting the lock is a single instruction

(Assuming your macro CPU_LOCAL_GET_SCHED_LOCK_PTR gets a per runqueue lock rather than one which is global) In between the time you read what lock to grab from it, and grabbing the lock itself, if preemption occurs, this may be bad if your task is migrated, as when it wakes up it’ll grab the wrong lock (as then the queue which is read would be different)

Ofc, this isn’t an issue if schedule is called in a context where the task cannot be involuntarily preempted

hazy saddle Jul 10, 2026, 11:43 AM

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i think il fix this by having irq/non irq locks

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then just disable irqs seperatly

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Thanks for pointing that out

wide mica Jul 10, 2026, 12:06 PM

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hazy saddle i think il fix this by having irq/non irq locks

You need to disable preemption before reading that value

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Otherwise there's a race between reading the cpu and acquiring the lock

hazy saddle Jul 10, 2026, 12:09 PM

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wide mica You need to disable preemption before reading that value

i fixed it like this, i dont have preemption at all rn so i diddnt setup the counter. and iirc i still want irqs disabled anyways, + its simpler on the asm side

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spinlock_lock also is not not an irq lock and irq_spinlock_lock is

wide mica Jul 10, 2026, 12:10 PM

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hazy saddle i fixed it like this, i dont have preemption at all rn so i diddnt setup the cou...

You don't want to disable irqs here

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It is very rare that you need to disable interrupts

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also same thing with finalize here

hazy saddle Jul 10, 2026, 12:12 PM

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wide mica also same thing with finalize here

finalize is fine with how arch_thread_switch works

hazy saddle Jul 10, 2026, 12:12 PM

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wide mica You don't want to disable irqs here

ah yaaar

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so i can just disable the preemption

wide mica Jul 10, 2026, 12:13 PM

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yeah

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Unless you take locks from the irq for some reason

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In that case, don't

hazy saddle Jul 10, 2026, 12:13 PM

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i only take the scheduler lock so

wide mica Jul 10, 2026, 12:14 PM

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wdym

hazy saddle Jul 10, 2026, 12:14 PM

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the one for the thread qeueue?

wide mica Jul 10, 2026, 12:14 PM

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Yeah but don't take it in an irq

hazy saddle Jul 10, 2026, 12:15 PM

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but what if im trying to preempt from an IRQ?

wide mica Jul 10, 2026, 12:16 PM

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DPC

hazy saddle Jul 10, 2026, 12:16 PM

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i really still dont understand what the diffrence between running in a DPC is vs running in an IRQ context

wide mica Jul 10, 2026, 12:17 PM

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DPC runs with interrupts enabled and preemption disabled

hazy saddle Jul 10, 2026, 12:17 PM

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my IRQs also run with them enabled too?

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im like 99% sure this would still fuck up badly :p

wide mica Jul 10, 2026, 12:19 PM

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Obviously this is still wrong

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Same bug as before

hazy saddle Jul 10, 2026, 12:20 PM

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yeahb but its worse now because idk how the fuck its meant to be fixed without disabling irqs :p

wide mica Jul 10, 2026, 12:21 PM

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You have to disable irqs for a very short time when disabling preemption

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But the point is to not disable them across lock holds

hazy saddle Jul 10, 2026, 12:23 PM

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that wasnt even what had made me worried about this

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prev->preempt_disable_counter -= 1;
idk if there is a place for this that wont race?

wide mica Jul 10, 2026, 12:24 PM

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If preemption is disabled then that shouldn't race no?

hazy saddle Jul 10, 2026, 12:25 PM

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Well when the new active thread is set preemption would then get enabled?

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unless i disable preemption on both threads??

wide mica Jul 10, 2026, 12:31 PM

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Why is the counter per thread

young hamlet Jul 10, 2026, 12:31 PM

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Per thread preemption counts are kinda based

wide mica Jul 10, 2026, 12:32 PM

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Why

young hamlet Jul 10, 2026, 12:33 PM

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wide mica Why

Can allow ur task to get scheduled out if it’s preemption is disabled without side effects

wide mica Jul 10, 2026, 12:33 PM

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True

young hamlet Jul 10, 2026, 12:33 PM

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But how useful this is, I don’t know

wide mica Jul 10, 2026, 12:33 PM

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Yeah it's not really useful

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Sounds like it'd kill latency

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Or rather

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Make it higher

hazy saddle Jul 10, 2026, 12:35 PM

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wide mica Why is the counter per thread

il swap to a per core one. i could have sworn i heard it was meant top be thresad local

young hamlet Jul 10, 2026, 12:35 PM

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Afaik Linux and Xen both have it in gs (on x86 platforms)

wide mica Jul 10, 2026, 12:36 PM

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virgin preempt counter vs chad irql/ipl

wraith star Jul 10, 2026, 12:37 PM

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in linux the preempt counter is in current

young hamlet Jul 10, 2026, 12:37 PM

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wraith star in linux the preempt counter is in current

I see

wraith star Jul 10, 2026, 12:37 PM

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in x86

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idk other arches

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oh wait nvm it's a per core

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in other arches it's in current

hazy saddle Jul 10, 2026, 12:40 PM

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So what should I be doing

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Hmm

wraith star Jul 10, 2026, 12:40 PM

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switch to a per core counter

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you already have percpus set up in place, and in x86 you can do inc gs:whatever

hazy saddle Jul 10, 2026, 12:40 PM

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wraith star Jul 10, 2026, 12:40 PM

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in those other arches it is not possible to increase or decrease cpu locals, so the counter is in the task struct

hazy saddle Jul 10, 2026, 12:41 PM

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I do have plenty of room on the CPU locals on other arches anyways

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So it's fine™

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And I can just do a quick enable / disable irq

wraith star Jul 10, 2026, 12:41 PM

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nah

wide mica Jul 10, 2026, 12:41 PM

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wraith star in those other arches it is not possible to increase or decrease cpu locals, so ...

You can still disable irqs

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Temporarily

wraith star Jul 10, 2026, 12:41 PM

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eh

wide mica Jul 10, 2026, 12:41 PM

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That is what I do

hazy saddle Jul 10, 2026, 12:41 PM

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I mean

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On other arches it's cheaper than x86 iirc

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Because no flags memes

hazy saddle Jul 10, 2026, 12:43 PM

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wraith star eh

I mean then I have the same problem

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Just on the RISCs instead of x86

wraith star Jul 10, 2026, 12:43 PM

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the value of current is always going to be stable in a task

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(obviously)

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so you can put the preempt counter in the task struct

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and you know that you can only be interrupted in instruction boundaries, so you have either increased/decreased or nothing

hazy saddle Jul 10, 2026, 12:46 PM

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so in theory would this work?

wide mica Jul 10, 2026, 12:46 PM

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Anyway I think if you wanna do irqls you have to make it per cpu

hazy saddle Jul 10, 2026, 12:46 PM

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What if you did both

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PSP1G_pspTrollar

wraith star Jul 10, 2026, 12:47 PM

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wide mica Anyway I think if you wanna do irqls you have to make it per cpu

if the irql for scheduling is the lowest one after irql=0, not really

hazy saddle Jul 10, 2026, 12:48 PM

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hazy saddle so in theory would this work?

Getting the current thread is always stable and one instruction so that won't race.
And then it can switch safely the tasks etc. then when it's finalizing it disables it and then it can race

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I think I'd need to disable IRQs there?

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Unless I preempt disable on next and then switch and then decrement both?

#EvalynOS