#EvalynOS
1 messages · Page 24 of 1
Yeah, that’s why I only ever really use the web panels and paste relavent shit in and then see what it shits out for me to fix / if it did the thing right
90% of the time it falls flat on its face 💀
But somtimes it makes something workable
Yep
With the non-reasoning models? By good question.
That said
I just tried claude opus (I think it was called that?) and if you gently steer it in the right direction it can really help you build faster
Doesn't work if you don't already know how to do the thing you're doing though
Yeah I only dump shit I to free models and have it shit out some garbage 💀
lol
I’m only on it to be a freeloader to be lazy when not wanting to make 10 lines for a calloc function because I have malloc already
if in the distant future you can afford it though, I'd definitely say it's worth trying
I’d rather still keep having fun programming on my projects tbh
I'd like my OS to be AI optimized but not by using ai 
well point is you have it do the boring tedious gruntwork
That's what the Good first bug tag is for 
lmao as if your hobby kernel is gonna have more than 0.05 external contributors on average
If I can actually get good python support I will be the target OS for all beginning system developers everywhere 
I mean I wanted a microkernel so that you could write drivers in python...
🙏 What is python gonna be used for though
Drivers, kernel modules, user space programs, libraries, etcetera. It's a design philosophy, not a scientifically decided choice.
well its now only ~0.01 to ~0.02 seconds slower than gunzip!
just gonna do a bit more tweakings
then get the docs made and release it
library is done

I already have it implemented into the old kernel
I’m gonna clean that up a bit and push it since having it support it is nice
It’s also down to be a bit more optimized
There may be more that can be done
But for the tiny library it is, it’s pretty damn good
It compiles under C99 rn and C89 and K&R / unixv4? Support may be added later with the optimizations though unixv4 and K&R may have to be a seperate branch
What library do they use, I wana see if I can run benchmarks compared to it
kamila wrote her own
I did not see it there or in third party
bruh
But only on the noLLM branch
skrill tissue
Time to steal some paging code 

also im micro optimising the FRED path
By shamelessly stealing from the compiler codegen of course
What’s a movezx?
No fucking clue
But it works
move zero extend
Just looked it up lol
Makes sense
I don’t need that on the IDT path since it pushes a full word for the vector
Now this wont work if I use extended features of FRED
Like NMI source reporting etc
But this does work for now
I do wonder. Is zigs inline assembly powerful enough to properly align a function to a page and make another function at an exact offset from it?
i will let you know in a bit, im going to be trying that in a minute lmao

I think il make a comment about inlining that function and later when I add support for advanced stuff that needs extra decoding I can make it a compile option?
those will be packed in with the cs and ss in the frame anyway so dispatch_interrupt can detect it later presumably
Oh yeah true
And then I can push things back into one unified frame?
And make FRED push a dummy vector
yeah
and just you can switch on the flag for fred later to use the extra stuff in cs and ss or ignore it otherwise
thats legit what im doing
Then if fred == on { decode the vector and fill it in on the stack and continue }
yep
(except im using inline asm in the fred thunk to do the decode and fill bit hopefully, its just a shr and a movzx)
I can probably also make it a lower so it can stay in a register
That code up there is doing the decoding btw
mhm
oh true you can stack offset
Since its aligned
Yes bit aligned
Because they have a possibility for extentions to go beyond 256 vectors

So that may need a bit of extra decoding
now the only annoying bit is detecting syscall stuff
since otherwise those are hitting vectors 1 and 2
its just this
Yes
The Intel engineers were pretty smart

Let me go do this rework
oh i can even push a diffrent value based if it was a CPL3 vs a CPL0 from fred
this is a mess
decoding it in the asm is prolly best
or with a C shim?
actually
this isnt too bad
Good use of Goto aswell?
then the indentation gets a bit messy
yeah ig
oh! this will also be nice
because in the non FRED path i can check if its from CPL3 and swapGS
missing giant TODOs in the comments :P
makes it easy to search for them later

i dont need this but its prolly cheaper / better than
if(frame->cpu_frame.cs & 3)
mhm
Also @signal plaza I do just wana tell you now this is not the kind of thing to steal
Paging is a very fundamental concept and is meant to be a barrier to entry for getting into this hobby
As it makes you understand alot of concepts
YES IT DOES 
That’s fucking insane
Once zig stabilizes I really should just try and get past it and learn

did this and then bulk is a comptime string with the bulk of the handling
I wonder if you can shove some constants in the free area and reuses them
Don’t waste a single byte
maybe

oh and btw my offsets from rsp are computed by the compiler
zamn
I know, I say that as a joke. I find it easier to understand what's happening by reading code and I usually read yours, so I joke that I steal ur code
Ahh
I hope my new paging code is nice for you to read

It does have some limits to keep in mind that I left in due to performance stuff
It is, actually lol
Eg it’s a pain to do merging and splitting of pages
So I’ve elected to make it invalid and make some special things to make sure it will never need to happen
(They haven’t been made yet)
the movl andl shrl andl blob might be wrong btw, the intent there is to put the fred vector in dx and (hold on i just found a mistake in there) the type field in bx, and then set bit 31 of the vector if its a syscall and put it in the vector field of the struct (and also leave in rdx for the dispatchy bit)
Wouldn’t you want to put it into e(whatever) and have a zero extended byte move?
Because then it also zeros the upper part of the register
And if you use the 16 bit reg it may not work

its actually in e_x and im anding it since you cant do a zero-extending write to memory in one insn and im using that upper bit to signal syscalls anyway
Ahh
I wonder if doing the decoding in zig would be better?
And let the compiler optimize it heavily
probably
but i cant replace only prolog and epilog so itd need to be its own function
and the compiler i dont think can inline into inline asm
so it wouldnt be inlined which i kinda want here
so the way i do it
is i have a vtable for the exception vectors
I was also planning a function pointer and syscall table, but having things still be in C is nice
mhm
imo for this it isnt too bad
its basically just
- if bit 31 is set go to syscall entry
- if its less than 31 go to the vtable
- if its 0xDF go to the apic spurious handler
- otherwise go to the main irq dispatcher
My thinking is if you add syscalls and the other various things you get into the realm where a higher level language is nice & the compiler can still make perfect optimizations in that case minus the extra function call (or two in syscalls spot but that is very minimal compared to the rest of a syscall)
mhm
Btw thank you @haughty acorn for letting me know I could just push an extra thing 
And not need the jmp garbage
i think this is validated enough

il be pushing later™
and prolly work on either slab shit or printf shit
yeah that looks good to me
Because if I have a custom printf I can also make custom formatters for certain objects
It will be another combo single header & non single header library
So it can be integrated however you need

Though for this one I can imagine it being non single header is nice since I make it very easy to add custom formats
Only downside is I don’t wana parse IEEE crap
see for this I just use zig std format and it's great and works on its own lol
And this library will be made with no AI help (I somtimes use it for random debugging or whatever rarely) and I CBA to learn IEEE floating point shit
yeah no for osdev you can probably ignore ieee
Exactly
Il still add the hooks for it though if somebody wants to talk cheap send patches
And the format parsing fortune X.Y part
mhm
machine check exceptions are so fucking dumb omg
so it basicaly sends it to all cores by default i guess?
and i need to add a flag that says "hey im processing an #MCE just return"
i think this right now is fine though? since the parsing wouldnt fuckup other cores
intel
why
well this dosnt matter
since im not running this on i686 rn
Good thing that my architecture will not have any of this bs
welp its good enough for non SMP at least
Il just add an extra SMP flag so if it is mid #MCE handling other cores will just return and let the core that’s handling it right now decide to panic & broadcast etc
Btw if i get a C compiler running on my arch you might be able to make an port for it 
I will probably make a port for it after my loongarch64 one isn’t stub city 💀
meow
Meow
I'll learn loongarch64 deeply
This is working!
Well atleast good enough to not crash
Just by enabling it
Maybe I should add extra logging for stuff
Welp it works on Intel and AMD
well thats good
I wonder if there is a way I can have this trigger an MCE on real hardware
as I said

wiggle your ram a little
I’m not wiggling my ram on this expensive of hardware
😭
Go wiggle your ram @tender mantle
I'll run it and unplug a ram stick from my old pc
I doubt it would mce
it's just funny
wait
ram is WAY to expensive to be doing this shit rn
It’s already been done
Your doing ts now
It’s DDR2 or 3 or some shit
That’s still cheap
And prices have been going down
@tender mantle lmk when your done
I am unable to make a #MCE generate on hardware
Even using a special AMD only MSR
That lets you make a watchdog timer for instructions taking longer than 31us
To trigger a #MCE
🥀
And @tender mantle yanked ram and wiggled it
Nothing
do you enable MCE in cr4?
yes ofc
im gonna try this to slow the cpu down so bad
the watchdog may trigger
gl
this crap is so cursed as its only on AMD
#define MSR_AMD_MCE_WATCHDOG 0xC0010074
the MSR btw
its the only way i can trigger an #MCE without hardware damage 💀
oh i thought u were doing more interesting things lmfao
if an instuction takes longer than 31us to complete it should give an MCE
XD
i am also making some MCE handling stuff
usually a watchdog is used to detect hard lockups
technicaly it is but on an instruction level basis
what's an MCE?
how can an instruction take longer than 31us?
nah
ah 
not necessarily
generic interrupt used for notifying a cpu of urgent things
its not masked with cli
its just the minimum timeout
yeah but i think u misinterpreted it
Hm?
its not tied to how long an instruction takes
its just a timeout after which the watchdoing is going to fire
and you're expected to prime it before it fires
(if doing lockup detection)
prime just means rewrite the same value into it
This and the other screenshot is all the docs in the AMD manual
its like a oneshot lapic timer
but you're supposed to reset it before it fires
and if you dont u consider yourself stuck
So where do I need to write this 
usually in the periodic interrupt for example
if it doesnt fire that means u have cli for too long
thats not existing for this watchdog
am i really that bad at explaining
void timer_tick()
{
touch_watchdog(); // rewrites the same value into the MSR
sched_tick();
{
no? this is a special watchdog. not with LAPIC oneshot. i know how that works
...
What 😭
This is my rewrite, I haven’t gotten yo that yet. I ended up on a side quest with machine check exceptions and I’m trying to test them on real hardware
yes
just forget about the watchdog for now
so
you have a periodic timer
you can consider that timer a heartbeat of your kernel
but without a watchdog
if you skip a heartbeat
or flatline
there's nothing to catch that
Yes
if you arm a watchdog, you're guaranteed that not generating a heartbeat (that does wrmsr(watchdog, fire_in_1ms)) will fire the watchdog MCE
and if that does get fired
you realise that a heartbeat was skipped
because no one rearmed the watchdog
so it expired and fired
does that make sense?
wdym by that?
And for some reason this specialty is talking about instruction execution?
i do set a thing here
can u link that spec btw
cant grep this msr in linux
dont think they even use this
maybe it is specifically a hw debug msr, not the software watchdog
Yeah it’s some really strange thing I found when trying to see what can generate an MCE
The Intel manual partly mentioned it but dosnt refer to the MSR at all
and it just #GPF's under KVM
as well it dosnt emulate it

@hazy saddle perf events seems to be the way to do NMIs on x86
and its how linux does a watchdog on x86
ahh yeah 
but the main thing im trying to do is see what happens at all when i get an #MCE since they are so uncommon
I mean nmis are easy since you can just set delivery mode on apic things, mce is harder
cant you just IPI yourself on that vector?
maybe? but i dont think thats considered a "true" #MCE with stuff i can parse etc?
u want like literal hw bugs?
yes lol
what's the vector? cause iirc the apic won't trigger vectors 0-16 or something like that
0x12
ok so it's above 0x10 so apic can ipi that vector
what info do u currently parse on mce
weather its fatal & to panic or to log it and move on
i hope your printf is reentrant lol
it takes a lock on putc
which is why i am gonna make a proper log buffer later™
make a log ring like all of us lol
thats what i meant
i can generate them in QEMU, and they work as expected
was just wanting to verify real hardware

but idk if i can for now atleast
do they set all the msrs and stuff
yup!
cool
.
but yeah the easiest way is to get some throwaway hw i guess
and try pulling a pci device at runtime or something lol
i doubt ram would generate an mce
btw does qemu allow u to specify fatal/non fatal?
you set the flags register which says fatal/non
ah
i do mce 0 0 0xB100000000000001 0x5 0 0 for a non fatal
and mce 0 0 0xB100000000000001 0x0 0 0 for fatal
but yeah, enable PCI MCEs, and read a pci device config space in a loop,
then just pull it out
that should produce a read timeout MCE
iirc all MCEs are enabled by my code
then all u need is a testbed lol
who knows
welp its good enough 
If I ever find hardware that wants to spit them out il enhance the handling
But this will atleast catch them and ignore non fatal one and behave good 
yeah
Meowing dragon lol
pushed
I think this code is good
I think I’m gonna add logging helpers macros next to cleanup some crap
And then maybe work on mm or printf ✨
I definitely need to make logging macro
I’m probaly gonna have
LOG()
LOG_TAGGED(ansi code for the tag, “tag”, “text”)
LOG_TAGGED_PASS/FAIL to append a tag for passing and failing which should just be able to also call the LOG_TAGGED macro
how do we all like this?
using this macro soup
eg
printf(ANSI_BYELLOW "[ARCH EARLY INIT]" ANSI_RESET " GDT INIT " ANSI_BGREEN "[OK]\n" ANSI_RESET);
becomes
LOG_TAGGED_OK("ARCH EARLY INIT", ANSI_BYELLOW, "GDT INIT")
i think i got them into all the proper spots
i like how this looks, do the colours have a meaning
e.g. have you chosen a colour for a particular subsystem
just randomly picked per section
The logging has always been like this
Just uhh

I manually fucking did all the ANSI and spacing shit
Without macros
Btw I do wonder, does retro rocket of any support for the machine check exception / architecture?
you should change your font
just to make it different and unique
that way w hen someone sees a screenshot they can tell its EvalynOS not just generic VGA font OS
My old font was an 8x8 and honestly borderline unreadable 💀
Once I get userspace I will probably have that load a .psf file for the non earlycon console
I do want to get microcode updates supported soonish tbh too
As aparently it’s not too bad
You just have to get the file loaded into memory and then do some MSR magic
Which limine can do for me (the file loading)
now commit to limine to use this library
No
got KASLR working
also fixed up the build system a bit so you can do KASLR=false make run and debugging builds where it waits for gdb always has KASLR off
Not doing this to be ulta secure but it’s easy enough to support it 
And it makes me be not a dumbass and hard code values in my paging crap
wow when did you become a mod
um did the admin just ramdonly asked you about becomming a mod? or did you apply or something
wdym
I mean you don’t have to come to this thread there was a bit of talk about it in lounge0 
oh rly
Mint said they wanted to make me a mod when I turned 18
I turned 18 today

i just opened this thread and saw your name in red
congrats btw
I need to stop being lazy and make my allocator lol
nice
Thank you ^^
Memory allocator and virtual memory allocator
I’m doing a rewrite
I finished the new paging code recently
I lowkey burnt myself out a lot snd rushed too much
So it rewriting and not doing that

maybe you should implement some shiny userspace apps
btw i have weston and other stuff running and dont evne have smp and a usb driver
plus a lot of stuff that im probaly supposed to have
isnt smp easy with like limine
And portability to other architectures
Not when your kernel isn’t really designed for it lol
Me with 7000 thread safety issues even in one core
luckly my new kernel is sort of designed for it
The main thing is just to add it as soon as you can
Which I plan to do after I get the schedular and stuff up
well im not so sure, by that i mean just putting stuff on cpu specific things
Yeah but
If your kernel already has a ton of stuff
It’s gonna be a pain
And it’s not just “make it CPU local”
pretty sure rust already protected me before hand with Send + Sync and mutexes
the only thing that ill have to worry about is prob race conditions
And they use rust lol
isnt it in cpp
No.
huh
tbh it kinda is
You may be fine then?
if you want it to be good, that's another matter
tho the bootloader crate dont natively support smp, so maybe ill make it my self after 10 years
I had smp before scheduler even lol
I want my SMP to atleast be properly stable and for threads to migrate and stuff lol
or steal it from my original ai slop filled os
unlilke limine
I plan to have every core pick N buddy cores
And then only share with those
So it evens out naturally
And should work well with NUMA as I can make a seperate class of migrations
btw does C programmer usually make things them self, and only use libraries for huge things
like idk, ext4 driver?
And not connect cross NUMA for standard buddy migrations
and code other stuffs like datatypes them self
Yes I would make my own ext2 driver
(becuase i usually just use crates everywhere)
why 😭
I wrote my own UART driver even and GDT IDT and all of that
ig it makes you learn less
CC: @urban mulch because I’m not experienced enough in rust
But i can say a few crates i have seen are just bad
Like the x86 one
x86_64?
The x86 rust crate
never heard of it
and also my new kernel (the no ai one) actually uses the latest version of uart
Source of the Rust file src/registers/control.rs.
Also Rust is not the be-all end-all of safety
This one atleast
You can get pretty close with just linters
The real reason I use Rust is because I like its type system
You use unsafe so often that the notion of safe rust becomes almost an oxymoron
The only libraries I use are flanterm and nanoprintf because I haven’t NIHd them yet
why would you use unsafe tho
You have to
yea but
It's either that or unsound
You are very very wrong
You have to use unsafe for linked posts in rust right?
unless you hate your self or something
1sec lemme check howmany unsafes are in my code
IDK if you're writing in Rust but if you don't agree you need unsafe all over the place your kernel is full of unsoundness
They have an AI make a kernel in rust

Ah
that's why I go zig lol, safe rust is annoying and won't be that useful for anything osdev but zig also has a good type system and is meant for low level stuff like this
So the AI has been making unsound code as usual
i mean my no-ai kernel lol
Also
well because
And you get way more functionality and it generally will be better
any driver is unsafe to construct at the very least
Because what if the device does DMA?
:/
https://git.evalyngoemer.com/evalynOS/evalynOS/src/branch/main/kernel/src/arch/x86_64/drivers/16550uart.h
this is also relavent
tbh if i dont like some parts of a crate, i usually just fork it
At that point
Just sit down
Use your brain
Read some docs
And make a full driver
The UART crate is really not that good lol
It enabled IRQs
But provided no way of using them
if it works, and it prints characters, and doesnt crash your whole system, and is reasonable fast
then im fine with it
That’s not what UART is only for
It’s also an input device
And you may want a proper TTY layer over it
And it took a lot of iteration to even make my driver work and be stable enough for real machines
I can tell you now the versions of the rust UART crate would fail on lots of my hardware
It works in a VM sure
But you have E9 for that 
Plus a lot of the fun in making a kernel is making the drivers yourself
You just add an ext4 crate
Your done
You learnt nothing
And didn’t go through any of the fun
Also it’s gonna be harder to integrate into other systems of the kernel potentially
like, no?
i hate making drivers
Then why are you making a kernel?
Like an overwhelming amount of Linux code is drivers
because its cool
So you do it because it makes you look cool instead of doing it to learn and program low level things and hone your programming skills and stuff
basically yes
i like shiny userspace apps
kernels as a rule are either 90% drivers or theyre small and 50% of the code is to load drivers as external modules
Using a crate is even more boring
maybe, but it lets you focus on the thing that you actually wants to focus
Using a crate skips alot of that too
true
how?
Because you don’t end up designing a lot of the systems you would have to integrate it all together
??????
You’re just calling external code? That does all of it internally and exposes some public API
my drivers are like 30-50% integration with the rest of the kernel
um
Certainly a lot less flexible and you miss out on alot of it
what exaclty does "system" mean
do you mean like
scheduler
or something like that
The kernel
or like memory allocator
um
yeah all of the above lol
exactly
Maybe it’s a difference of opinion, but you still miss out on a chunk of the work and fun
Your given a clean public API for things
kiss out
?
but you still kiss out on a chunk of the work and fun
Crap
lmao
lol
well you still get the fun, except you dont have to work, which is probably ebtter
imo the fun of developing any software is to make subsystems work to geather
I mean I get not wanting to make ACPI or ext4 drivers, but a lot of crates are really dumb lol
If you have a clean public API the dev already did all that work for you
My KGZ library does all the porting work for you and provides macros and a single function to use
If I had made this for my kernel specifically
It would have been way more integrated
I feel like you’re missing alot of my points here. I’m not saying it’s piss easy to integrate it. But it’s certainly a different thing to integrate crates together than your own code
idk i feel like C developors just like making everything by them self
Rust and zig people also do it too 
yeah
@urban mulch
definitely not as much as C people
I mean Emma certainly does it themselves
or zig people
I’m pretty sure you ended up NIH more stuff than me @haughty acorn
don't use uint64_max crates for a 100 loc project challenge: impossible

I mean like I also use external deps in C projects
whats that
But I like to keep it minimal
c you also cant often take as many other libs easily because theyll depend on stdlib stuff that you dont have
what's what
I sort of make my kernel have a standard libc because I use standard header and function names
Makes some things a little less annoying to reuse
im not sure if this means imported more libs or less libs than you lol. my only library dependency is uACPI
uACPI is special because doing AML fucking sucks
yeah but you wont have standard libc file io lol
What stuff am I gonna try and port into my kernel that needs that though
I’m taking random stackoverflow shit that wants like stroull or whatever BS
Etc etc
my kernel has external deps on:
- zig
- an emulator to run it on
- uACPI (fetched automatically by zig)
- standalone/freestanding libc type headers for uACPI (autofetch)
- dimmer to make the disk image (autofetch)
- dimmer depends on a zig library called zig-args (autofetch)
- dimmer depends on zfat (autofetch)
- zfat depends on a standalone C fatfs impl (autofetch)
Who needs an emulator 
Just dual boot and reboot every time you wana test jt

my only runtime dep is zig and uacpi tho lol
(When I first did OSDev years ago that’s what I did)

Well I actually flashed it to a USB by manually copying files and using gparted to change the ESP flag
So it was even slower
😭
OOF
I think I got up to exiting UEFI boot services and getting some PS/2. input and then I quit
yeah thatll do it lmao
idk lol
My old kernel actual originally was a remake of that old project
Since I was bored one day
some part of my brain keeps going what if i made an acpi library in pure zig with full support and used that instead and then i squash that part of my brain because FUCK NO I AINT DOIN THAT
-# do it

someday lol
i havent had the ability to even do any dev work in over 10 days now because of irl shit i def dont have time to make an acpi library when uacpi exists
What if I reinvent the wheel but make it a sphere instead so it can go in all directions
Let’s make it out of concrete
Rust devs absolutely make too much shit themselves
That's not a language specific thing
Most programmers like reinventing the wheel
yep lmao
It’s fun too somtimes
im not sure x86_64 machines have the ns16550 uart controller do they
Well it’s a compatable chip or whatever
The interface
So it’s still a “16550” driver
nvm then
It'll be "fun" once you realize the spec is shitty and reality doesn't follows it 
Congrats on mod.
Thank you
You did a lot for this community
Btw how is your decompressing library?
Is it faster than miniz now
No idea I haven’t benched it (other than in userspace vs gunzip as a ballpark)
It was mostly made for fun tbf
It is certainly fast enough to not make me upset though™
I’m working on a rewrite
Again lol
Not your memory allocator
Oh after C++ I went back to the original project
I actually started anew her proper by myself
I should possibly update the post™
But it’s 2am and I’m going back to bed in a moment
Nah you didn’t wake me up lol
isn't that the broken uart
tmk the pc16550dn is the newer version that should actually be used
There was like one or two models with some issues
It’s just always called the 16550 by most things
my thing uses the pc16550dn
Did any models with the broken FIFO even end up in any PCs?
beats me
Huh
It's a ns16550
I don't think so? However the ns16550 had some predecessors and those lacked a FIFO and other stuff
happy belated birthday! 🎂
Thank you ^^
i think i have finished my early memory allocator
I may tweak it a bit more
But it’s good enough™ for now
After a bunch of work on it
And defer is working on clang22 nicely aswell
my earliest allocator is bump 

I need this one to support free() for vmem stuff later
And I didn’t wana make statically allocated objects
This one is able to return memory to the PMM too so there is nothing wasted either 
my early allocator is for pfndb
Ahh
No that’s probably fine
Though I use a freelist for that and I plan to just not free() anything before it’s setup so I can track things properly™
And I can flush out whatever is partially filled from the memory map into a more advanced PMM after pfndb init
I also hope nobody sees this and goes bitmap!!!!! Bitmaps must be good for everything because I use them
I have had like 3 people referring to my frankly garbage code in some cases
And I am very concerned
One of them even stole my code and made a PR somewhere 💀
While completely disregarding the license
After I get vmem and a proper slab allocator going though
Il work on SMP shit
Some timer crap
And try and get a mlibc port going for hello world
And then get the VFS squared away and /dev/fb0 /dev/ps2 and /dev/pcspkr crap so I can port doom and bad apple
But in a way more proper way
Then bash probably should work fine but I’d need to throw in fork()
Which should hopefully just work?
Oh yeah il also need the page table clone funcs and scheduler things
when will you get networking done
But it should hopefully just work™ after I finish it
After I get x11 and nvme il look into some network drivers
Il do a CLI browser 💀
I ain’t porting Firefox for a while
my next thing is prob nvme or usb
lol
Unless a png is acceptable

Wayland/DRM may also be fun?
Iirc zinnia did that
And that would be cool af
i want serchat on evalynos
If you get a CLI client in C I will gladly have a port of it
boring
Or atleast a light weight enough JS runtime
But I cannot run a full browser anytime soon 😭
meow
Mrrp
Meow
Give it a few years I’m sure she’ll get there
I mean I could just do Linux binary compat :x
But that’s lame as shit
Boring
Though if I get enough ports having some compat layer in userspace could be cool though
Do something interesting like nt binary compat 
I’m not a fucking insane as reactOS people
If I can I would port wine though
its eassyyy
git clone wine
Don't they basically also reuse a lot from Wine?
they share alot back and forth iirc
what do u use to allocate the linked list node structure?
on llist_push
It’s an intrusively linked list
typedef struct spalloc_page_header {
llist_node_t llnode;
uint64_t bmap[2];
} spalloc_page_header_t;
it just has the node in the header
and push just connects pointers
void llist_push_front(llist_t* llist, llist_node_t* node) {
if(llist->head == nullptr) {
llist_initial_node(llist, node);
return;
}
llist_node_prepend(llist, llist->head, node);
}
damn thats nice
Intrusive structures are quite nice
oh and push and pop are aliases
[[gnu::alias("llist_push_front")]] void llist_push(llist_t* llist, llist_node_t* node);
[[gnu::alias("llist_pop_front")]] llist_node_t* llist_pop(llist_t* llist);
okay i think every bug is zapped
i also have more asserts here to catch bugs
i also am temp tracking the PMM pages to make sure its not leaking
and i think it all works now
and the clankers arent complaining so

i think ive got this all properly fixed
any issues should be from severe miss use of the allocator at the very least
which im not particularly interested in hardening beyond the basics
I’m gonna let this clanker test to run overnight
This should catch anything
Then I can fix any issues or whatever
And then have a finished nice allocator
To be clear I did not generate the allocator with AI
Just the tests because tests are fucking annoying to make
im having this run overnight on two computers*
@tender mantle is gonna run it too :3
ty btw
all good :3
Looks like things worked over night

Though I had to change the test and code to return false on invalid configs
Because the test was of course dumb as shit 💀
haiii :3
continuing the bad ram test chain from #when-your-os-goes-crazy
Yup
I also may wana test managarm on this
Since I may work on some #MCE stuff for them
well when i get a functional nonfunctional ram to boot you can throw anything you want at me :3
🔥
ok so limine got invalid opcode with perfectly fine ram as well
so i'm pulling out the "modern" server
May wana ask mint about that #UD?
i think the #UD handler is definitely part of the ILO
cuz i keep seeing that when trying random bs
i do also hope we dont hit this deadlock 😭
Printf would only touch the stack and the framebuffer
So it should trigger mid log for this
Shouldn’t*
oh also on panic you get a ralsei
🔥
Hopefully the terminal emulator can render those right
Also my stuff shouldn’t break things 
Well atleast not until I add microcode updates
Which I don’t wana do
Because AMD fucked it up SO FUCKING MUCH
To the point Linux just sha256s every single fucking ucode for AMD for a lot of CPUs

Atleast on Intel it seems mostly sane?
no shot
this server actually boots up within 1 working day
on the bright side this server actually has serial bios log and the adapter seems to work
i really don't want to pull up my pentium III laptop just for serial
okies
got link local IPv6
very relevant
I paid 20 bucks for an overpriced cable just for an FTDI chip lol
Just because I couldn’t be added to have something not work
well
you ain't gonna believe this
illegal opcode 😭
i'm not even joking
this has to be a limine thing
i'm doin grub-mkrescue
f this noise
or is it the limine protocol?
💀
What happens if you just make a custom limine install on a USB
Then add my conf and kernel binary
(Remove the initramfs from the conf)
And my kernel only boots off limine

wanna see the error message up close?
like the faulting IP?
What is the IP?
And sure
But idk why it shows 32 bit registers
💀
Because my kernel is very much x86-64 and supports VERY modern features
(Though not required)
If anything it should fault in my kernel its self?
no clue to be hones
trying the limine usb thing now
kinda checking everything along the way
and i meant instruction pointer
also sry if not responding that often i literally cannot hear anything over the server lmao
ITS FINE
what did I miss?
How do you even handle MCEs?
You can check my code
CMONNNNN
@hushed oracle
nahh
bustin out the pentium-II box
i5-1345U skill diff obv
Is that pentium 2 32bit iirc?
yep
Does evalyn's kernel even support 32-bit?
Nope
But that’s just for serial
Ah
If I ever do 32bit it will be a source compatible kernel with a very similar syscall interface 
My kernel supports it if it's i686
Idk you should just use parallel, it's a simpler protocol 
I wanted to port mlibc and gotten depressed
Pentium II is i686 yeah
But I can try implementing MCE handling real quick 
i686 also has MCEs iirc
And my kernel supports compat mode
It may be the legacy variants though depending on how old it is
But which server is failing?
Though I support that too
The one running my kernel
Limine was dying
So x86_64?
Yes
My kernel boots with hyper as well
My kernel isn’t running on x86-32
We can check hyper 
I mean I can give an image (though I don't handle MCEs)
I don't have that...
Maybe later I will make functions that can grab things genericly
Did I say you did?
Idk I've got this on the pentium pro manuals
I support 2 bootloaders, but it's not very abstracted
MCA is the new one, you can lack MCA and just have normal MCEs which are always fatal
Idk, it all came from supporting RISC-V
This is MCA


MCE exists since the pentium days iirc
