#MINTIA (not vibecoded)
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basically yes
the wmb would ensure stuff inside the critical section cannot be reoredered to after the lock release
ok cool
i figured but i thought id ask in case youd go like "nooooo this causes a common and very subtle issue known as poopenhagen's blunder its described in page 500 of this c++ textbook"
lol
so this is some more instructions i can eliminate
really expensive ones too
these extra wmbs
you dont care about stuff after the release being reordered to before the release right?
no
yeah should be fine
im using the dec alpha memory model where you get mb and wmb and everything aside from that is a fuzzy haze where literally anything goes
which is scary
dec alpha was technically in-order but could get apparent arbitrary reorderings anyway because of how the dcaches were laid out
the alpha 21064 was dual issue
and each pipe had its own dcache
and the coherency between them within the core was obviously program order but very lazily so
and from the perspective of other cores theyd go wildly out of sync all the time which resulted in apparent arbitrary reorderings of loads and stores
good thing its dead, id be too lazy to figure out how to work with it lol
that isnt even possible with just the reorderings from OoO but it is with this dual dcache setup
OoO alone would not result in that iiuc
its funny bc one of the later generations was quad issue
and it had
4 dcaches!
so even more fun
if your broken program happened to work before it def wouldnt on a system with those ones
to this day there are still lots of special barriers and stuff scattered all around linux that are defined to an empty macro on everything but alpha
they maintain this meticulously even with the brand new maple tree stuff and whatever
dunno why
there must be linux on alpha legacy users still
how is this port still alive
cuz ppl bought tons of alphas in the 90s and they were being sold until the early '00s
they literally dropped ia64 but this crap is still there
it seemed to have a bright future as late as like 2001 when it was unceremoniously dumped in fear of itanium
it was the last risc standing
x86 never beat the reigning alpha in performance, it won by default because the next gen alpha (which would have been the first SMT microprocessor) was cancelled
i bet it would have eventually but its the only risc x86 didnt have a chance to kill in a performance knife fight
microsoft originally planned to support Windows 2000 and Windows XP on alpha
and we actually have an early build of XP for Alpha
which is the latest "classic risc" windows nt build known
isnt that the one that u revivied or whatever
no that was the R3000 one which is the earliest one known
ah
ignore "windows 2000" this is in fact very early XP
its very interesting that alpha had a solid future and didnt seem due to lose the performance wars just yet
but itanium was so scary and all the suits were convinced it would kill their risc architectures
isnt that kind of cheating if u reorder literally everything and force software to deal with it
sure but it worked
ig lol
so itanium kills off alpha
compels compaq (who had bought dec) to cancel the next gen alpha and lay off the team
the alpha IP is sold to intel
the team goes to AMD
where they work on athlon and kill itanium
sick!
thats good
the ghost of alpha got its vengeance
altavista was run on alpha machines
and they did some papers comparing performance of various nominally comparable servers in like 1999 and the alpha blew everything else out of the water still
so it wasnt just on paper, its model really worked
who knows what would have become of it later
probably if compaq hadnt cancelled it it would have found a solid long-lived mainframe niche like POWER did, there are still ppl with alphas today and theyd still be buying new ones rather than slowly switching away
thats my guess
and i suppose HP would own it
in tribute to alpha i have yoinked its monstrously evil memory model for my dumb fake computer
also i guess its important to note that the mbs after acquiring a spinlock are not collapsable for adjacent spinlock acquisitions
other cores have to observe you taking the spinlocks in the correct order or there could be deadlock i guess
it would not
is that a yes
i dont plan to support numa but ive gone to some lengths to make it painless if i decide to
for example my memory management state is isolated in "partition objects" (another idea shamelessly lifted from NT) and i can duplicate these for numa nodes
almost everything that was global in old mintia is now in partition objects
ah ok, well it would seem fitting for it
each one has its own worker threads for page-out, its own pagefiles, etc
its own page lists
do u support transparent migration between them?
i dont really have to worry about that yet thankfully
or like a page migration mechanism in general
given a range of pages migrate them to a different range
dunno
for now im just isolating the global state because thats the highest impact immediate thing i can do
to avoid massive work later
yeah
this is used in a lot of places, like memory offlining, poisoning, etc
so could be useful for u later on ig
from what ive seen nt doesnt support offlining memory
if i support numa it probably wont be to the degree of like cellular irix
ill do the high impact stuff like isolating the memory management state per numa node and add some basic awareness of it to the scheduler
and duplicating kernel code and page tables across each node
other than that i probably wont do much
fair
even that is 10000x more than youd expect for a shitty hobby kernel
maybe if it becomes more ubiquitous in the future
i feel like old mintia had a vms-y and like mid 80s vax aesthetic to me
whereas mintia2 feels more akin to like itanium or something if that makes sense lol
anyway numa support would feel at home in the latter so its probable
that ill support it at some point
ill probably work on this for like 15 years
i didnt say at the same rate
true
also i might just never get a cs job
i didnt do any of this to get a job
i did it cuz im extremely autistic and obsessed with old computers
the idea of leveraging it for work opportunities didnt come up until more recently and kind of distresses me
If you know about NT on non NUMA, are partitions used there?
what do they hold?
they are used there
its just theres only one of them
I'm more concerned with HMP than NUMA. Don't you have plans to target arm64 julysky?
arm 
said a "riscv shill" 
HMP?
correct 
His Majesty's Prison
some of the notorious ones include HMP Belmarsh, HMP Wakefield, and HMP Frankland
If mintia's so good why is there no
good point
Where are apps mapped to if there are >1 partitions?
Well, at some point I'll be sure to commit it
probably the memort partition associated with the given process
whats that?
marking a memory range as offline
and migrating any physical pages away from it
idk if the 2nd part is required or not
i guess that depends on the implementation
generally used for memory hotswap
before you pull the ram stick you first might want to make sure nothing is using it
it is ofc
yeah it didn't make a whole lot of sense
but tbh i kinda see myself implementing it like if memoryInUse: return EBUSY 
thats kinda your only solution if it contains any non movable allocations
but usually memory that you plan to how swap u only allow movable allocations
aka userspace stuff
then nt should be able to know how to offline memory since it supports unplugging (for hyperv only tho)
well there are a few things to keep in mind
such as
what if the page is referenced in multiple places
either by COW or by page cache
yeah, those are solved in linux but i dont know the details
it reuses the generic page migration mechanism used in a lot of places
compaction, numa balancing, numa migration, etc
all use it
wouldn't any pageable memory fit this criterion?
well linux doesnt page kernel stuff
so yes
this is my SMP safe way to get a pointer to the current thread
on xr17032 specifically
one cashew to whoever can correctly guess what this is doing and why it works
compiles to code like this
so there must be a page mapped to the end of the address space. but how on earth is that SMP safe! what happens if multiple cores do this!
what on earth!
software-filled tlb shenanigans?
๐
each core has a wired tlb entry set to map the final page to a per-core data area
so it maps a different page on each one
and it doesnt matter if you get migrated between calculating the pointer to it and loading the thread pointer, itll still be you
im thinking of making it the second-to-last page rn though because its a little dangerous to have something mapped within a page of the null pointer in either direction
how exactly does the tlb work on xr? does the hw help you pick the tlb entry to replace?
if so, how do you pin the entry for this in place?
i recall the tlb miss handler being short so that logic is not there
theres two tlbs, one for data one for instructions, they have duplicated control registers but both work the same so ill just talk about the data one
theres a control reg DTBINDEX which contains the index of the next tlb entry to replace
basically when you write a tlb entry, it automatically increments, so theres a FIFO policy
when it wraps to 0, it jumps to 4
so entries 0-3 arent replaced
you can explicitly set it to one of those and then write a tlb entry to cause a wired tlb entry to be created
ah interesting
those are the wired entries in the itlb and dtlb under mintia2
the "exception block" page is wired to 0xA0000000 in the ITLB
contains exception handlers, including the tlb miss handlers themselves
if it wasnt wired youd get an infinite tlb miss loop
and in the DTLB the page directory is wired into the recursive page table and theres also the per-cpu area
the page directory mapping is also necessary to avoid infinite tlb miss loop
makes sense
this is partly from MIPS
MIPS being easier than x86 kind of falls apart as soon as you look at the kernel mode architecture
x86 is 100% easier there
for example as far as paging goes u just have to set cr3 and ur done
xr17032 equivalent of mov cr3, eax looks like this
@twilit smelt how good is this https://www.reddit.com/r/osdev/s/oe4KiTvCfI
Says demand paging
Why lol
It has literally no locks
Interrupts are disabled in the kernel and it is uniprocessor
Damn didn't take you long to evaluate
What is happening here
I was able to determine that within literally seconds
What the fuck
There's inappropriate inline assembly everywhere
My superpower is being able to tell whether a kernel project is shit within 3.6 seconds with 90% accuracy
Looks like scheduling is tied to pit
Yeah
and development was relatively fast because I can reference code from early linux!
Wait did they really say that
Higly doubt Linux did whatever this is ever
Yeah it was kind of a mess
And the codestyle was huge statements without empty lines
Also depends what early Linux means ofc
What the actual fuck lmfao
Sorry I didn't expect it to be this bad
It said demand paging so I expected something serious lol
I didn't even see demand paging
I saw """"""COW""""""
No demand paging unless I misread their mess
That's just a lie it doesn't do anything
rule of thumb: if the OS project has the numbers 95 or 98 in it, there's a good chance it's terrible
Is it supposed to mean windows 98
probably a reference to Windows 98
If it did nt larp that'd be funny
bruh
With this level of competence
alr the main function
Uhhh
Lies
Already comment on the post from someone who didn't read the code and took it at face value from the feature list
Lmfao
It doesn't even have a buffer cache or any filesystem IO at all
It only has the hardcoded tty thing
So easy to farm engagement on that subreddit
@nocturne sentinel you goofed

they're in this subreddit
What does this mean btw
McMaster University (McMaster or Mac) is a public research university in Hamilton, Ontario, Canada. The main McMaster campus is on 121 hectares (300 acres) of land near the residential neighbourhoods of Ainslie Wood and Westdale, adjacent to the Royal Botanical Gardens. It operates six academic faculties: the DeGroote School of Business, Enginee...
tho tbf
half of the people at my uni also overuse ChatGPT
Like u generate that crappy feature list and don't even remove outright lies
i read a bit more through that kernel and it seems this guy doesn't have an assert macro
it's just if (some_thing_that_should_not_happen) printk("Warning: something happened");
that's sad
At least they get free osdev reddit points
i wish i could go back to when i just wrote code and didn't know any better
i could actually run bash with somewhat demand paged userspace 
Simpler times lol
no that was 2 years ago
Lmao
not much has changed since then
except for my inability to write code that works
๐ญ
Naah its just lack of motivation
#define NR_TASKS 64
#define TASK_SIZE 0x04000000
#if (TASK_SIZE & 0x3fffff)
#error "TASK_SIZE must be multiple of 4M"
#endif
#if (((TASK_SIZE>>16)*NR_TASKS) != 0x10000)
#error "TASK_SIZE*NR_TASKS must be 4GB"
#endif```
???
What the hell do they store in the task lmao
Uhh
just when i thought i've seen it all
union task_union {
struct task_struct task;
char stack[PAGE_SIZE];
};```
The type of slop chatgpt can produce
Loooool
why is the kernel stack in a union with the task struct
RTOSmaxxing
my channel has been taken over by viciously bullying some 13 year old's first project
i love how you can just stack overflow and overwrite your own ldt
struct task_struct {
long state;
long counter;
long priority;
long pid;
struct task_struct *p_pptr;
struct desc_struct ldt[3];
struct tss_struct tss;
};```
beautiful
They literally go to a uni
oh
Or have graduated already
crazy
"Researcher @ McMaster University" apparently
Ldt is the most important field
Gotta have an ldt
Also tss.. does it do hw tasking or something
No way right
#define switch_to(n) {\
struct {long a,b;} __tmp; \
__asm__("cmpl %%ecx,current\n\t" \
"je 1f\n\t" \
"movw %%dx,%1\n\t" \
"xchgl %%ecx,current\n\t" \
"ljmp *%0\n\t" \
"1:" \
::"m" (*&__tmp.a),"m" (*&__tmp.b), \
"d" (_TSS(n)),"c" ((long) task[n])); \
}```
hard to say
i don't even want to know what this does tbh
Waait
@sterile frost hey stop bullying children, let's add ECAM support to CSMWrap
unfortunately its a fully grown adult
i am starting to think you can only fiddle with P2SB using ECAM
Its a researcher in a uni
Literally
welp
what'd I goof
it's already a pr
by fly i think
wheeeeeeeeere
you praised that kernel in a comment on the post before reading the code
draft
youd know the list of features was 100% lie
it's not a PR, draft or otherwise
oh it just sounded good so I tried to give support, didn't bother reading ๐ญ
what's wrong with it
I'll have a read now
Yeah just scroll 
it would be faster to list what isnt wrong with it
- it presumably builds correctly
- thats it
meh old unix kernels had tons of fixed size tables
including the process table and stuff
See ain't so bad 
that doesn't have ECAM implemented
until early 90s that was a huge thing
one of the selling points of the NT kernel by contrast to unix was "dynamically sized system tables"
"no mysterious limits! everything grows to fill available memory!"
Did you see the page allocator
no ๐ญ I'll have a look
tf is PAGING_PAGES ๐ญ
@covert hound what's paging pages
parker wrote this kernel btw
@covert hound WHY DID YOU CALL IT THAT
Buddy youโre going to have to pay me to explain that.
theyre using recursive mapping
Really?
which is fine ig
To explain it to you would be a Herculean task
You feeble minded FOOL
its beyond us
Itโs time you accept that and move on
high readability
he doesnt know what youre talking about i just invited him for moral support
oh my god they use libc based include headers for the kernel ๐ญ

redefine stdarg
ends up insane
okay
so
we missed something
in the experimental/ directory there is a buffer cache and minix fs driver
they may even work
however i looked at the minix fs driver in linux 0.99 on bootlin elixir
its just plagiarized
its like rewritten one-to-one looking at the ancient linux sources
"kernel98" on the left, linux on the right
its all like this
a lot of the inline assembly is stuff copied one-to-one from old linux
what would happen if i make weekly "quality watch" posts on r/osdev where i go over all the posts from the previous week and point out how they suck or dont suck
in great detail
that would be nice tbh
but also likely would be poorly received by that community lol
maybe good for our community, but not there
yeah theyd probably go "youre taking it too serious people are just trying to have fun man!" cuz theyre wimps
i would upvote it
make alt accounts and create fake fans eager to watch your content
so then people are like "wow, this guy, he's being supported by totally-not-an-alt he must be saying truth"
then the redditors will graduate into actual OS philosophers
@twilit smelt how does hardware IPL setting in mintia work exactly? I see you're setting the hardware IPL on interrupt entry and restoring it on exit, but what if you raise to IPL high then get an interrupt (that's possible since the hardware one isn't set yet) then it sets the hardware one to high and now you don't ever get other interrupts and the IPL is stuck there
basically i pat the steak dry and then i season it with some salt and stuff which i knead into it gently and i let it sit for a little bit before i throw it on the grill
the problem youre describing cant happen because interrupts are disabled at the point where i raise hardware ipl
i also dont fully understand what youre talking about
but it sounds like something that cant happen because interrupts are disabled at the point where i set the hardware ipl register
Your raise and lower ipl only set the software stuff right?
yes, i NEVER use them to raise into a hardware ipl or lower from hw to sw ipl
And the hardware IPL seems to get updated on every interrupt based on that value
but if the IPL is high, that means that the hardware IPL will be kept high since further interrupts will get blocked and that update won't happen
its not
Then when you set the hardware IPL back at the end of the handler it's gonna be high
Because interrupts are not disabled in RaiseIpl?
Unless they are and I misunderstand the code
why not
i dont raise to those with that
i only use KiRaiseIpl and KiLowerIpl to move between LOW, APC, and DPC
levels
(by far the most common transitions to make)
Yeah ok that makes sense
thats why theres separate HalRaiseHardwareIpl and HalLowerHardwareIpl which do the full thing
and are slower
yeah then you can keep the raise and lower short
KiRaiseIpl is now a macro in fact
#MACRO KiRaiseIpl ( ipl ) [
NOTHING KI_CURRENT_PRB_LOCAL^.Ipl
KeAssert ( KI_CURRENT_PRB_LOCAL^.Ipl <= ipl )
NOTHING KI_CURRENT_PRB_LOCAL^.Ipl = ipl
BARRIER
]
(where BARRIER is a compiler barrier and doesnt cause a memory barrier instruction to be generated, dont get confused)
No more assembly :(
KiLowerIpl is still in asm
because it does more stuff?
yeah
So you want to ensure it's as short as possible
i experimented with inlining it but it bloated code size too much
which was detrimental to icache
so i only inlined the shorter KiRaiseIpl
which saves two instructions (the call and return)
Now that I've seen that way of doing ipl vs purely hardware It'd be interesting to compare how much overhead there really is with mov cr8 and self IPI on software interrupts (on actual hardware)
Cuz to me the software way seems way better but idk
i also inlined KiReleaseSpinlock
#MACRO KiReleaseSpinlock ( spinlock ) [
BARRIER
// Memory barrier to ensure old writes are committed.
INSERTASM "wmb"
BARRIER
// Set spinlock un-owned.
NOTHING (spinlock)^ = 0
BARRIER
]
but didnt inline KiAcquireSpinlock
why not
need to add __atomic
// a0 - spinlock
KiAcquireSpinlock:
.global KiAcquireSpinlock
// Common case: non-contended.
.retry:
ll t0, a0
bne t0, .spin
sc t0, a0, a0
beq t0, .spin
// Memory barrier to ensure reads in the critical section don't see stale
// junk.
mb
ret
// Spin until free without using atomics since they may incur more cache
// coherency traffic.
.spin:
pause
mov t0, long [a0]
bne t0, .spin
b .retry
heres the fox32 version
(its empty there is no smp fox32 so theres no spinlock on fox32. its unimplementable anyway because fox32 lacks atomics.)
fox32 is one of the biggest reasons i went out of my way to conditionalize all the smp code because theres no use having that all there bloating the codepaths
on the fox32 build
so mintia2 generates really tight code on uniprocessor builds, even compared to old mintia thanks to the inlining and stuff
ESPECIALLY on fox32 mostly due to jackal compiler's fox32 backend being ~infinitely better than df compiler's
what's good about it being your own arch too is you can optimize your code better compared to something like fox32, where you would know less about the internals and it'd be a bit trickier to optimize for without reading the emulator code
i do understand the emulator code on fox32 very well
mostly because ive had to debug it a lot
im ryfox's QA team
Truly like NT engineers collaborating with intel
That looks similar to x86
I wonder if you could save much space with more aggressive optimizations, like is the code it's emitting still a bit stupid or is it pretty optimized?
the above is pretty well optimized
it would be difficult to hand-write it any shorter than that
I guess it depends on the Jackal code
there are dumber sequences being generated elsewhere
the goal with the compiler was not to make a compiler that can turn dumb jackal into good assembly
but a compiler that can express good code in jackal form
even if it requires some contortion in the source code
If it's good enough it's good enough 
Hopefully the new compiler project will give you free space savings tho
that would be nice
i also appreciate that it's called "iron" which unintentionally fits in the rocks and minerals theme of like prism and gem and stuff
advancing the late 80s decwest larp by coincidence
coyote is the jackal frontend but the compiler infra is called iron
later theyre gonna do a frontend for their own (much fancier) language called mars and rewrite the compiler in it
so itll self host (which meets my requirement for the xrstation compiler to be self hosting on xrstation and fox32)
theyre already emitting some xr17032 assembly
hope they dont spontaneously lose motivation one day and never work on it again
seems to happen to other people a lot
you could always "just" do an LLVM backend or something if the need arises which shouldn't be extremely hard I think
that wouldnt self host for the simple reason that i couldnt fit an llvm-based compiler in 4mb of ram on xrstation
True
i could with page swapping but itd be so fucking bad
ideally one day ill be able to bring the larp full circle by writing mintia2 inside itself
which will only be practical if the compile times are reasonable
gcc 2.0 
i have my own self hosting compiler luckily so i dont have any hard dependency on iron although itd be reaaaally great if they could take the burden of evil compiler shit off my hands
if they dont ill inevitably have to rewrite most of mine (everything but the frontend)
and thatll be annoying cuz i hate compilers
i always get inspired and go "WOWOWOWOW COMPILERS ARE COOL" when i read this stuff
https://bitsavers.org/pdf/dec/prism/mica/870827_DECwest_Compiler_Project.pdf
https://vmssoftware.com/docs/dtj-v04-04-1992.pdf#[{"num"%3A1010%2C"gen"%3A0}%2C{"name"%3A"Fit"}]
and then im working on a compiler
and its just misery
i dont enjoy it
every second i worked on the jackal compiler i wanted to scoop my eyes out of my head with a melon baller and bleed to death
but if iron doesnt pan out im inevitably going to revisit it at some point and spend probably several months revamping it
before i do the amd64 backend
"if you hate compilers so much then why are you doing all these compilers and not just retargeting a small c compiler or something" SHUUUUT UUUUUUUP
its the cool factor
if its not 100% from scratch THEN WHAT WAS THE POINT
ykwim
i finally reached a point where everything the kernel touches directly (architecture, emulator, language its written in, build system, etc) are all NIH'd
if i randomly give up 1 of those things what was the point of all the others
anyone with a worse kernel than mine should feel bad because they didnt even have to worry about writing debugging and maintaining all that other shit
this is me with a massive cartoon ball and chain shackled to both feet
i copied code from linux 0.01 badge
I mean I think r/osdev has a very different demographic to here
it's mostly just:
- hello world kernels or kernelspace shells that somehow get a dumb amount of attention; or
- questions about stuff in docs like simple questions on setting up limine, "where do I start", etc - aka ppl who don't know how to use google
also copied from linux 0.01 :^)
it sounds like it's just linux 0.01 but buildable with a modern toolchain :^)
Ah so thats where they got all the weird inline assembly
Jesus
i really need to stop doubting myself
everyone starts somewhere ๐ญ
There's a comment calling 9front one of the best operating systems
What even is that
dude
the loongarch tlb refill scheme is almost identical to my old one from 2022
i thought i invented that
aisix tlb refill handler from 2022:
TLBMiss:
.global TLBMiss
mtcr tbscratch, t0
mfcr t0, pgtb
mov t0, long [t0]
tbld t0, t0
mtcr tblo, t0
tbwr
mfcr t0, tbscratch
rfe
linux tlb refill handler for loongarch:
SYM_CODE_START(handle_tlb_refill)
csrwr t0, LOONGARCH_CSR_TLBRSAVE
csrrd t0, LOONGARCH_CSR_PGD
lddir t0, t0, 3
ldpte t0, 0
ldpte t0, 1
tlbfill
csrrd t0, LOONGARCH_CSR_TLBRSAVE
ertn
that is craaaaaaazy similar
almost line-for-line similar
im not joking
this is pure coincidence
its a really unique scheme too
my arch and loongarch are the only two ive ever seen do this
they just have lddir instead of tbld
which is a special instruction that folds together some of the work and helps evade a branch
which i thought i invented
what is going on here
me and some guy in china linked brainwaves like 3 years ago
ITS FUCKING
ALMOST THE SAME
DOWN TO THE DETAIL OF HOW THE CR'S ARE IMPLICITLY MODIFIED BY THE LDPTE AND LDDIR INSTRUCTIONS
WHAT THE FUCK
bros am i a victim of chinese espionage
Ni hao bai chi de wai guo ren
LOONGSON SPY
the odds of coincidence occurring are actually insane im shook
jokes on them i already moved on to an even more magical tlb refill scheme
if the next generation loongson chips move to that scheme ill be convinced someone in china is a fan
okay nevermind
it turns out the loongarch tlb refill handler was committed to linux almost exactly 2 weeks before i committed mine to aisix
they did theirs on june 3 2022 mine was on june 14 2022
insane coincidence
i actually did synchronize brainwaves with a chinese engineer randomly in early 2022
๐ญ
How do you pronounce mintia? Minsha? Minty-ah?
last thing
isn't this literally copied from Linux?
it is yeah lol
some ancient early 90s linux code trying to optimize something the c compiler presumably did a bad job on back then
copypasted blindly
thats insane
@twilit smelt thoughts on this https://github.com/asterinas/asterinas
lol
asterinas is just a rewrite in rust of SPIN
What is that
Enforced modularity. Extensions are written in Modula3 [Nelson 91], a modular programming language for which the compiler enforces interface boundaries between modules. Extensions, which execute in the kernelโs virtual address space, cannot access memory or execute privileged instructions unless they have been given explicit access through an interface. Modularity enforced by the compiler enables modules to be isolated from one another with low cost
weird
Very strange
How would this be enforced if u can just slap an unsafe
And u have to in a lot of cases
you can NOT tell me that the entire architecture dependent code is 10 lines
Lol
presumably they would ban it completely (which would gimp the OS considerably)
all i see is cpuid parsing
Same yeah
as it happens rust is also a ripoff of modula-3 https://www.cs.purdue.edu/homes/hosking/m3/reference/unsafe.html
And this has 3k stars
they seem to spread arch-dependent code around the kernel
for example there's syscall/arch/{riscv,x86}.rs
...
Bruh
ew
that's such an odd way to do this
Is there really no easier way to dispatch a table in rust?
For example, in the network TCP tests, Asterinas uses the smoltcp [22] library, which lacks congestion control, enabling TCP to operate at full speed and resulting in faster performance compared to Linux
what
???
What the fuck
"we are using a bad library which doesn't do things correctly so it's faster"
Lmfao
apparently they're sponsored by intel or something
this is like saying you can get past a school with kids walking out the gats much more quickly if you drive at 90mph
I kinda doubt they pushed the Linux network stack to its limits
Its optimized into oblivion
By corporations
I wonder if this is bs lmfao
they should sponsor managarm instead
Managarm should use more loud words
And fake benchmarks
And say stuff like Linux killer etc
Vibe coded Linux killer os surpassing Linux in benchmarks
Safe and microkernel based and blazing fast
i should give up on my kernel and work on managarm
see you in 10 years 
woe
i mean to be fair, this kernel that you posted has been worked on for more than 3 years
ive only been at it for a few months
does it run kde?
fair
kde is my goal also i guess
altough it requires probably tons upon tons of syscalls
and sysfs stuff
it's not that hard to do from what i can see
sure you need a lot of linux interfaces
not that hard, only needs an entire drm stack 
on top of everything else
netlink too i think
i should get an intel sponsorship smh
think of buzzwords for limine then
why is kde everyone's goals now
fair
but my real (probably more achievable) goal was to run some sort of a 3d accelerated game on an igpu
that requires way less than kde
some misc syscalls and drm basically
that'd be super cool
my uni break starts next week I should look into getting astral to compile again

the vibe coded bootloader "limine killer"
someone should actually try that as a project
but no manual adjustments to the code
ai in, ai out
nah just replace all occurences of limine to enimil
as the proud owners of our next gen AI powered bootloader with web 3 support, we are glad to announce the new $ENIMILCOIN that we totally wont pump and dump
features: nft support, enable a20, web 3.0, chatgpt integration, load gdt
We been seen it
It's not the worst project ever but it's overhyped
uve seen every os
uve sounds like a bolivian fruit
julysky, would you use 2MB pages to back the PFN array? Wouldn't it be too much of wasting?
There's an alternate universe where I'm the guy who makes asterinas and someone links me mintia in here and I reply 2.6 nanoseconds later "that's shit."
Linux does
damn. ๐
Whether that's a waste or actually a memory saving (because you get rid of the leaf page tables) depends on what the phys mem layout looks like
If you have lots of contiguous physical memory then it's good
PCs do afaik
Well it picks the size to use dynamically iirc
Depending on contiguous memory length
Exactly because of this contigousness not guaranteed, I asked.
also yeah you can determine it dynamically
You can probably figure out the ratio of physical pages that exist versus don't in an aligned 2mb area of PFN db for it to be a saving
And then mathemagically determine whether to do that or not
for each such area
why not lol
gnome
probably, but I'm a fan of wayland myself
someone should make wayland but it actually works
once u xfce u can't backfce
cinnamon is cute too
?
last time i checked it didnt support nvidia cards
which is like your bootloader not supporting intel or something
idk it's been years since i last checked
things might have changed
i have been daily driving gnome with wayland on a 4070 since I've gotten it
hmm
also wayland has barely anything to do with the gpus themselves
if it doesn't work then that's a linux issue, not wayland
ig my system just doesnt play nicely with it
theres this bug with pipewire on my system where
the input mix rate wont match up when i use audacity
and it causes pipewire to break
apparently this is a common issue with people with my sound card
๐คทโโ๏ธ
did find a way around it though
is this project dead
No im just a big fan
I see
they mustve been a pretty shitty person, outsourcing all development to their fans and sitting at home collecting the rewards for themselves
They had some issues
do they have plans to continue the project in afterlife
is it possible that they blew up while getting pizza from a certain dominos
They went to fight for the IDF and got killed by a Hamas RPG
๐ฎ๐ฑ never forget our heroes
how do you manage to get israel into every conversation lmao
you werent like this a few months ago
I recently became aware of the terrorist existential threat to western values
honestly id worry about the capitalist system thats fucking people in the us more than jews and arabs killing eachother thousands of kilometers away
since one of those effects the other more
and californians stinkin the place up by revolting against the government
our lord shall smite them with the military if they dont obey the rule of law
Those are Americans exercising their rights. Don't be disgusting
seriously though
no updates here in a while
are u just focused on doing work and not posting about it
I have other things in my lif
i see

๐ฅธ
garbag collector.
other people get paging working. I get paging working. we are not the same
I shall have paged virtual memory within three years of today. Otherwise I quit osdev.
tried running mintia at 20khz and it gets stuck here because the 100hz timer interrupt soaks up literally all available cycles
ok at 50khz we get somewhere
wonder what happens if i do 50khz and 8 cpus
@mortal thunder in case you ever wanted to see your fireworks test running at 100khz with 8 processors
the extra processors do actually help it scale despite the extremely low clock speed
with just 1 processor it cant even do that much with the fireworks lmfao
i consider this a win for my scheduler
"hey man you seem pretty busy lately are you sure youre not being overworked"
"oh you know same old same old"
same old same old:
based font choices
mintia fireworks screensaver โ๏ธ
This actually helped me find a problem in my scheduler
I noticed some of the CPUs were strangely idle while others had tons of threads enqueued to them
I looked at my once per second balance DPC and saw that it was only moving up to 16 threads before bailing out
Increased that to 100 and the problem went away. This was also cropping up at full speed but was something I didn't clock as being because of the balance work
wouldnt it be better to scale the number of threads to move dynamically or nah
well yeah it moves as many as needed until theres balance
(or until it has tried too many times and its time to give up)
also i just got a very funny deadlock
i just redid scheduler rebalancing and it seems to have had a crazy good effect on fireworks test scaling
so i decided to run it with 2000 firework particles at a time
that is, each firework explodes into 2000 particles
it ran fine for a while but eventually got jammed and that was very concerning
i noted that all of the fireworks disappeared and the screen went black which was reassuring that it wasnt a scheduler bug
(because then probably thered be lots of firework particles stuck in place)
when i looked into it i found that one of the firework threads was infinitely trying to wait for free pages
while holding a lock required for thread creation
several other threads were waiting for it to release that lock
but most importantly
the worker thread that was responsible for thread reaping was waiting for that lock so it could delete the TID
so it wasnt able to free up memory by reaping threads
which is why this other thread got stuck
mintia screensaver design log
the solution i guess is to be more careful about the reaper thread taking locks that are also held while allocating memory
or i can change the order it releases resources in
in particular i can have it release all of the kernel stacks before it does anything else with the threads
lol yeah that resolved the deadlock
the "reaper thread" isnt really its own thread, its a work item enqueued to the worker thread pool
and as soon as it pops the list of threads to be reaped and starts working on them, the reaper item can be enqueued again and be executed in parallel
so if the first one gets deadlocked while unreferencing the thread objects because of an unlikely situation where memory filled with thread objects and theres no free pages coming in from anywhere and stuff, and it is deadlocked with some other thread that is blocked for free pages while holding a lock taken by the thread object deletion codepath, a second reaper can come in and free all the kernel stacks and release the first one from its prison
it could happen that every single thread in the worker pool gets tied up by this and theres still a deadlock but its really unlikely
and this all becomes nullified as soon as there are resource limits and swapping to disk anyway
i never once encountered this deadlock in a hell of a lot of stress testing with old mintia even though i didnt do any of these measures to try to decrease its likelihood
because old mintia had page swapping by the time i was trying that stuff out
funny how much stuff "i dont want to panic on oom" adds to your kernel design
also i did the thing
@warm mural i made some changes to my scheduler that made it way better at self-balancing, u might want to check out the recent commits cuz you were looking a lot at mine for yours
where do i find the vim syntax highlighting scripts for the jackal language
they dont exist
what IDEs are supported
none
it is
have you considered writing a syntax highlighting grammar or regex or however its done
treesitter
i mean you built the compiler so there's gotta be some regex in there that's reusable
i only made it so i didnt have to look at this
theres no regex in the compiler cuz the compiler is fully self hosting and that would require me to implement regex
the jackal toolchain is written 100% in jackal including build system
it has been run on fox32os
after using it to build itself for fox32
did you boostrap it by first writing the compiler in Lua as well
i am struggling to find the language specification
writing and compiling a fox32os application *all inside fox32os*!! this is using Jackal, a custom high level language made by hyenasky.bsky.social
the text editor is Hjkl which was made by my friend Olive and is also written in Jackal: github.com/OliveIsAWord...
see my pinned for more fox32 details!
do i just read the code and use my best intuition
i'm kinda bored i might write a syntax highlighter for jackal
yeah theres no spec yet
i had the basics of one going for a fantasy bad assembly syntax i made a while ago so i can copy some stuf
ryfox's fox32os is actually not that far from self hosting
its been perpetually like a handful of days of work away from self hosting for like a year
probably would be the first self hosting fantasy computer OS
unless you count oberon
as a fantasy computer
the work required i think is
well, fox32os is written primarily in two languages, fox32 assembly and okameron
the fox32 assembly it's written in is in the syntax of ryfox's own assembler
it would only take a few afternoons to migrate it to the syntax of the jackal toolchain assembler and rewrite the okameron bits in jackal
and then theoretically you could build fox32os from inside itself
if it aint broke there is nothing to fix ๐ I use vim because I am extremely lazy
thanks by the way
๐ now i can read your code without getting a headache in vim
well, nice
i might publish this once i finish this up idk
ok this is good enough for me, i will now look at header files
youll get a headache anyway if youre looking at the compiler
(it is ass)
regex is such hacky BS sometimes
"Yes doctor, I would like a
syn match jklFieldAccess /\<[A-Za-z_][A-Za-z0-9_]*\>\(\^\)\?\.\<[A-Za-z_][A-Za-z0-9_]*\>/``` please"
https://github.com/BlueGummi/jackal-syntax-vim ok if any vim users are tired of reading Jackal code with no highlighting here you go
I hope the regex is portable enoughish to copy to other text editors
this was a fun detour
might make one for dragonfruit later idk, I dont read that code as much
dragonfruit is dumbfruit
there's nothing in dragonfruit that doesn't have a better implementation in jackal
other than the stuff yet to be implemented at all in jackal like fs drivers
but shut up.
looks like a red dead redemption 2 loading screen
were the syntax design choices due to compiler limitations
like att asm
It was because i was 15 and heard rpn was easy to compile
It's a bob ross painting
It was the first thing that i displayed on limnstation (later called xrstation) when it had a 2 bit grayscale display in like summer 2018
so was that a monumental accomplishment and why the image is that
Was it easier than normal order
when it was a simple thing that just did this yeah
when i needed it to generate code that was like semi-not-horrible uhhh
no
not easier
also id like to note
when i ran with 8 cpus at like 100khz
none of the scheduler spinlocks showed up in profiling at all
even at that insane extreme there was basically no contention
what does that mean
it means he gets paging working while we get paging working

your paging: slapping ptes into tables and setting cr3
my paging: software tlb refil pageout to disk demand paging page cache
vro
thats crazy
i wrote a syntax highlighter for vscode a while back
if u just search up "jackal language" in the extensions tab
but its not incredible it mostly just highlights keywords and literals and such
it's ok i made one for vim and it's almost done except for highlighting variable types https://github.com/BlueGummi/jackal-syntax-vim
copypasted
so i didnt notice this but apparently the Multics Design Notebook has been mostly digitized. this is the internal design documents they wrote for multics before writing any code, and is what directly inspired the creation of the NT Design Workbook later:
https://multicians.org/biblio.html#mdn
note to self for later: when a thread handles a page fault on kernel space (like bringing in paged pool or code) it should probably raise its own priority floor to the lowest realtime level
kind of a semi janky alternative to doing priority inheritance through page waits
what'd be a non semi janky way ?
just doing priority inheritance with page waits
probably reusing turnstiles
ohhhh ok neat
x86 doesnt need barriers
but something like this might be helpful on like ARM for example
so I could implement spinlock_release_two but just make it mostly a no-op on x86?
souonds good
yeah other than releasing the two spinlocks
lol
i only even noticed the excess memory barriers cuz i was looking at assembly listings of my kernel
while micro optimizing
obsessively
which is probably dumb cuz the compiler generates enough bad code that i cant do much about
that the micro optimizations are probably lost in the noise
does the jackal compiler do any fancy optimization or nah
dead store elimination, constant folding and other stuff?
yeah
oh yeah as I'm discovering the keywords to your language, the syntax highlighting is becoming more complete. I might port this to treesitter or other editors soon so maybe you will find it useful? idk
it's not a big deal or anything
example of a simple function vs what the jackal compiler generates for it
so its not AWFUL
its workable
xr17032 lets you do shifts and rotations and stuff of the second register operand of every instruction that takes two source registers
without doing an extra shift instruction
and jackal compiler can do instruction selection for this
what is the NOTHING keyword?
so like
prb^.StashedCurrentThreadInfo =
KiSetInteractivityInStash ( prb^.StashedCurrentThreadInfo, newinteractivity )
is really
prb^.StashedCurrentThreadInfo =
(((prb^.StashedCurrentThreadInfo) & ~255) |
(newinteractivity << 8))
and it generates this as
mov t0, long [s0 + 244]
subi t1, zero, 256
and t0, t0, t1
or t0, t0, s3 LSH 8
mov long [s0 + 244], t0
u can see the cool inline left shift (LSH) by 8 in the OR instruction
it also generates the ~255 mask by doing t1 = zero - 256
so its not outright moronic other than sometimes.
I wonder how difficult it'd be to write an llvm backend for xr17032 and an llvm based jackal compiler for performance comparison
idk but me and pitust brainstormed some ideas for making the emulator probably legit 10x faster
#MACRO KiRaiseIpl ( ipl ) [
NOTHING KI_CURRENT_PRB_LOCAL^.Ipl
KeAssert ( KI_CURRENT_PRB_LOCAL^.Ipl <= ipl )
NOTHING KI_CURRENT_PRB_LOCAL^.Ipl = ipl
BARRIER
]
``` so what does it do here
do you really want to know
yea ๐
yes
this creates a very evil problem
uh oh
because theres no indicator to stop expression parsing
so for example
a = b + c
parses fine, but if you do
a = b + c
(something)^.SomeField = 1
or something like that, itll parse it as
a = b + c(something)^.SomeField = 1
where c(something) is a function call, and itll error
here the NOTHING token has the effect of indicating that the following open parenthesis is not a function call
the KI_CURRENT_PRB_LOCAL macro contains an open parenthesis
it is (CAST 0xFFFFC000 TO ^KiPrb)
oh deary, is the newline used as the statement terminator?
no
so for example if you do
oldipl := KiRaiseIpl ( KI_IPL_DPC )
itll expand to
oldipl := NOTHING (CAST 0xFFFFC000 TO ^KiPrb)^.Ipl
NOTHING (CAST 0xFFFFC000 TO ^KiPrb)^.Ipl = KI_IPL_DPC
in this position, the NOTHING is ignored
however if you do
if you naively do
a = b + c
KiRaiseIpl ( KI_IPL_DPC )
and it expands to
(CAST 0xFFFFC000 TO ^KiPrb)^.Ipl
NOTHING (CAST 0xFFFFC000 TO ^KiPrb)^.Ipl = KI_IPL_DPC
itll parse as
a = b + c(CAST 0xFFFFC000 TO ^KiPrb)^.Ipl
which will cause a weird syntax error
but if you add the NOTHING then basically the parser knows its a new statement and not a function call
and that load will be elided
why did you choose to design the language without semicolon statement termination?
thats not actually specifically what NOTHING does
it looks pretty nice but is there another reason
but in that position thats the function it serves
no it was just cuz i thought it looked better
the exact specification of NOTHING that me and sandwichman arrived at is that in the position of a statement, it has absolutely no effect
following a binary operator or at the beginning of an expression, it also has no effect on parsing (its like its not even there)
but in the specific location of where a unary operator might be
like the ( for a function call for example
it terminates expression parsing
again this is the function it serves the actual way it works is way simpler but its more difficult to see how it accomplishes this
this is the entire implementation of NOTHING in the jackal compiler
at the start of each subexpression (such as the beginning of an expression or the second operand of a binary operator) the NOTHINGs are peeled away and ignored
in any other location they cause expression parsing to terminate (because they are a statement and not an operator)
and are then parsed as a statement that does nothing
basically its like a really weird replacement semicolon
specifically for this weird case of jackal macro behavior
idk if i explained that well
but basically youre meant to use it when you dont want a ( to spuriously parse as a function call of something in the previous statement
should it have been called NOTHING? probably not
because it actually does do SOMETHING
sometimes
so it is nothing, but that doesn't mean it does nothing
yeah
i sh ould have called it something more tongue in cheek like SEMICOLON
its not actually equivalent to a semicolon though
cuz you can do a = NOTHING b and have that parse as a = b
(which is highly intentional)
if you did a = ; b that wouldnt parse in C
maybe could have called it STUPIDPARSER
idk
its difficult to come up with a brief name that encompasses what it does