#uDRM - a portable Direct Rendering Manager

1 messages · Page 5 of 1

main crow
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yes, that you do not need to make a large physically contignous memory area

livid sentinel
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then we can still use map_device_memory and it would return not supported and the driver would then fallback to single page allocations and scatter gather

main crow
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i mean i hardcode an 8 entry queue atm lol

livid sentinel
main crow
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it also has difficulties with fragmentation

main crow
tawdry trench
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what about fb memory?

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that is easily more than a single page

main crow
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not host memory

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but hmm

tawdry trench
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virtio_shm?

main crow
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okay this sucks

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making very large allocations is annoying for many designs

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my allocator at least can deal with it, but its just bump allocating out of the memory map

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and i wouldnt do that in a performance-targetting design

agile halo
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just use scatter gather where ever its possible and if its not and you really need a big blob of memory then request a bigger block of memory from the kernel ig

agile halo
livid sentinel
main crow
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gpus have page tables for a reason, though

tawdry trench
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someone with more knowledge than me needs to decide this

main crow
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i think its pretty simple though

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allocations like that are very very hard to do

tawdry trench
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then the kernel needs a way to signal capabilities to drivers

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i wouldn't use large physical pages most of the time anyways

main crow
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#if defined UAPI_KERNEL_HAS_FAST_LARGE_PHYS_ALLOC

livid sentinel
#

either also a iommu ifdef or both are combined and are abstracted behind a single function

main crow
#

iommus are not global

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for example you may have an iommu for the normal gpu, but not the integrated gpu

livid sentinel
#

does such a plattform exists?

main crow
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m1

livid sentinel
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as this exact scenario soundy incredibly stupid design wise

main crow
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i.e. yes

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its not

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iommus are expensive

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and gotta go fast

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the m1 has unified memory

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and the GPU has its own page tables anyway

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like for userspace mapping or something

livid sentinel
#

then ifdefs per driver?

main crow
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its a runtime value

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sometimes you just

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dont have an iommu

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so its a runtime per-device thing

livid sentinel
main crow
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also it could if the user turns it off in the bios

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also, GPUs are runtime hotplug which is fun

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so yeah uh im glad im not the one designing this!

agile halo
main crow
agile halo
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so yeah its not that uncommon

tawdry trench
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drm will have a hotplug event

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whatever linux drm can support

hexed flare
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is it hard to support?
Also, there are PCs without that (?)

hexed flare
main crow
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(2) yes

median yoke
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I don't think I even own a PC with an iommu

livid sentinel
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Afaik all x86_64 cpus that support virtualization have one

median yoke
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3/3 of my computers with virtualization do not have an IOMMU

livid sentinel
#

Are they older?

median yoke
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2013

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They all have the acpi table for the IOMMU, but it's invalid

livid sentinel
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Iommu is part of the virtualization extension but I don't know which gen

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And maybe they only gave Server chips one

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Maybe the mb doesn't support it

livid sentinel
median yoke
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Wdym

livid sentinel
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How do you know the acpi table for the iommu is invalid?

median yoke
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It has 0 as the physical address

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In the table

livid sentinel
#

Maybe it's disabled or broken firmware

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Amd or Intel?

median yoke
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Intel

median yoke
livid sentinel
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Wikipedia lists the Core2 Quad Q9400 as one of the first supporting cpus (2007/08)

median yoke
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Maybe my firmware is just stoobis

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*stupid

livid sentinel
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Maybe it's disabled in uefi?

main crow
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you need iommus for thunderbolt

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or secure thunderbolt anyway

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so i think its gonna be a thing in all new stuff

errant onyx
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i wonder if a thunderbolt device can do DMA without being limited by an iommu, if yes it could be used for cheats and probably a lot more stuff

main crow
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otherwise lolnope

errant onyx
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well yes I'm asking whether there are systems without an iommu for thunderbolt, I'd assume most do

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because letting something do DMA on a USB port is probably a security hole so no sane design should let that happen?

livid sentinel
main crow
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firewire:

robust abyss
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Anything Skylake and newer usually comes with vtd enabled by default

median yoke
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Bios doesn't have a setting

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Iirc

livid sentinel
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so apparently core i3s dont have a iommu so its possible for the user to combine a i3 with a thunderbolt mainboard
Insanity

livid sentinel
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So from our discussions I think we need three different phys mem allocation paths:
-iommu mapping
-large continuous allocation
-"give me a list of pages"

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The lowest one would be guaranteed to be supported, large allocations support with a define and iommu mapping with a define(to tell the driver that at least the kernel supports it) and fails with not_supported

robust abyss
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Why do you even care if iommu is supported tho? The driver never really needs to touch physical memory directly so having every allocation just give a device address and virtual address is enough no?

robust abyss
livid sentinel
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a iommu makes it very easy for the kernel and driver, the driver needs physical addresses for scatter gather lists, but tbh the iommu alloc and large alloc could be unified into one alloc function

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a iommu means that no matter how fragmented your physical memory is you can always allocate memory for devices as long as you have sufficient total memory

robust abyss
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I mean, technically yes but practically most allocations you need aren't that large

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I agree that an API that makes it easy to have contig in virt and non-contig in device address can be nice

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Linux basically just has dma_alloc_coherent, there are functions to map virtual memory to the device but they are highly discouraged from the ease of misuse

livid sentinel
robust abyss
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Yeah that's pretty rare

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Hardware vendors know that you need to keep minimal down to a page or two so they design the hardware with that in mind

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Xhci segmented queues exists for a reason

agile halo
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yeah most devices work with <= 4kb contiguous physical mem allocations and don't really benefit from larger ones that much

livid sentinel
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so we want to artifically limit uAPI to those devices?

robust abyss
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you could make larger queues with it, but nics for example usually cap at 512-1024 entries in a queue which even with 16 bytes per descriptor is only 8-16k which is really not that much

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I say that no driver wants to have random defines around memory management just to know if it could happen to have a large allocation, or if it thinks it can benefit it could very much try to make the allocation and fallback

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I think only one API is actually needed which is an alloc_sg, if the kernel can return it as a single contig device range so be it, otherwise it will segment it

livid sentinel
robust abyss
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But why do you need any other one

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And again the driver doesn't care for either

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It could always just try and fail

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You will have an if either way

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And having random ifdefs around memory management is just error prone

agile halo
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and for iommu it has to fallback anyway as its a runtime thing

robust abyss
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And map_sg always succeeds, you can have a flag telling it it must be contig in device memory for the case you do care (which tbf there are, but the driver shouldn't spam it around if it supports both)

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Like device address == physical address without iommu, but the driver literally doesn't care

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For the driver it could be wherever

livid sentinel
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so we could make it one single function that would return an array of {virt_addr,device_address,size}

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with iommu or large alloc support it would be a single entry

robust abyss
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It can always be contig in virt memory tho

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Unless we want to support mmu-less drivers lel

agile halo
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there is also a virtual map function already

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couldn't it be like host phys addr + device phys addr + size?

robust abyss
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Why do we need a virt map tho, in what case does a driver needs to map arbitrary physical address (ignoring uacpi completely)

livid sentinel
agile halo
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or actually wait no that wouldn't work as the current map function just maps contiguous physical memory to some kernel-decided virt addr

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ig returning an array of device addr + size and then a virt addr separately would work? though the driver doesn't always need the virt addr so ig there could be a flag for that

livid sentinel
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in what scenario does the driver not need access to memory mapped for a device?

agile halo
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scratch buffers only used by the device

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xhci for an example has them

livid sentinel
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we could add that as a flag parameter

agile halo
# agile halo xhci for an example has them

though I think those specifically also need to be saved/restored on suspend/wake so you'd need the virt addr to be able to do that but there might be cases when you don't need to do that

robust abyss
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Pass null as the parameter to the out virt address

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And it returns a handle you use to free

livid sentinel
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that would make the function less readable

robust abyss
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How so

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Like you want to return a handle anyways, how else would you return the virt addr

livid sentinel
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how would you differentiate a handle from a valid virt address

robust abyss
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They are two different things

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A handle is something pointer sized and opaque to the driver, only used for things operating on the mapping (in practice free)

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Virt is the virtual address you are given back to access the memory

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And we could have it optional

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Like it's an out parameter

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void**

livid sentinel
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you currently want to pass both trou one parameter

robust abyss
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No?

livid sentinel
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if i understand correctly

robust abyss
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uapi_handle_t thing(void** out_virt, ...)

livid sentinel
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nevermind i understod you wrong

robust abyss
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Technically we might want to return a status instead, but personally I think for memory allocation a null handle is enough to signify the allocation failed

livid sentinel
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we should signal why it failed, if we add allocation constrains like force continuos or <4GB

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so that the driver may handle it or just aborts

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so uapi_mem_status thing(virtaddrhint, size, flags, handle)

hexed flare
livid sentinel
astral gate
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It's debatable whether this would have any use, though. After all, it should be userspace that renders to the framebuffer, not the kernel

inner crater
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virtually contiguous is not an allocator property, but a mapping thing

astral gate
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I misread the message lol

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I missed the "phys mem allocation" part

hexed flare
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udrm disappeared from active threads nooo

tawdry trench
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wtf

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anyways, virtio memes shall continue today

hexed flare
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How's uDRM doing? ultrameme

hexed flare
tawdry trench
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no lol

tawdry trench
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expect actual progress start of feb

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i get 2 weeks off then

hexed flare
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I'm asking because I'm in a mood for S3 sleep and it would be nice if it could do that

tawdry trench
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i won't forget

hexed flare
main crow
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okay time to make a shkwve_modeset crate so i can beat you out meme

tawdry trench
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go ahead meme

astral gate
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marv needs that S5 sleep before he can work on uDRM trl

tawdry trench
#

FR

main crow
tawdry trench
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real

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im waiting for my ryzen to arrive so i can build a test station

main crow
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because if you only do VMs is it really modesetting

tawdry trench
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or in other words, my work laptop fucking sucks

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so i'm building myself a work pc

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work pc
9600X

median yoke
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Vbr

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Vbe

tawdry trench
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wbr

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working on my setup at work is painful asf

hexed flare
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And I have 2 PCs with COM ports

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So I can test on physical hardware

median yoke
tawdry trench
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troll

gleaming plume
north rock
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vouch

maiden birch
gleaming plume
maiden birch
gleaming plume
maiden birch
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You implemented a virtio GPU based opengl backend from scratch?

gleaming plume
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Yeah

maiden birch
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Damn

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How many lines is it

gleaming plume
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3k 4k if I remember it correctly

maiden birch
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Where's the code for it?

unkempt hearth
gleaming plume
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I think it's pushed on the repo

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If not I need to upload it

maiden birch
#

Also lol found an old school os still with lai

gleaming plume
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Yeah xD

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A lai era OS

maiden birch
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Was it on pause for a while?

gleaming plume
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Yeah, I didn't have much time

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Work consumes a lot of hours, but I'm having more time recently

maiden birch
gleaming plume
#

🤣🤣

maiden birch
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What can the os do atm?

gleaming plume
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Currently it can fully boot into a custom compositor based environment, it supports xhci mouse and keyboard, the compositor is really basic and doesn't have too much for now.

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Nvme, etc

maiden birch
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Thats cool

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Is it posix

gleaming plume
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Yeah

tawdry trench
maiden birch
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Are you gonna make a progress thread?

gleaming plume
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At least it tries to be

gleaming plume
maiden birch
#

Custom libc too?

maiden birch
#

Link?

gleaming plume
maiden birch
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Ah

gleaming plume
maiden birch
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Ah

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Cool

gleaming plume
#

The last progress I made was to implement the cursor thing on virtio

tawdry trench
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looking through the code rn

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you're relying a lot on HHDM

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(not inherently a bad thing, but might cause issues)

gleaming plume
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You mean using that on drivers?

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It's not hard to port that to other types of mapping on the drivers

tawdry trench
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cool

tawdry trench
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lower 4G of phyiscal or the entire phys space?

gleaming plume
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The kernel?

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You mean what size I map or the address of that mapping?

tawdry trench
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size yea

gleaming plume
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lower 4G if I remember correctly

tawdry trench
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that for example would crash on my PC meme

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even in qemu

gleaming plume
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False

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I just map the addresses that exists

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Based on the memory map

agile halo
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above 4g too?

gleaming plume
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If I remember correctly

gleaming plume
tawdry trench
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i'm just mentioning this because it happened to me lol

gleaming plume
gleaming plume
gleaming plume
tawdry trench
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nothing, just uDRM won't be able to use it at all

gleaming plume
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Why?

tawdry trench
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because uDRM also needs to work in user space

main crow
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couldnt you make map return hhdm addresses?

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ah

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ah yeah

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just hhdm map into userspace 4head

tawdry trench
gleaming plume
gleaming plume
main crow
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kernel only tho

tawdry trench
main crow
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and the userspace gpu driver is behind an SMMU

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unless you search for "bypass the smmu" in the datasheet because there is a bit to bypass the smmu from the gpu side

inner crater
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How's virtio going btw

tawdry trench
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i can get it working today or tomorrow

inner crater
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Based, happy to help today

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I'm unavailable tomorrow tho

tawdry trench
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i'll be off work at 4

inner crater
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I'll be in VC at about 18:30 cet

median yoke
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When uDRM

tawdry trench
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soon tm

tired steppe
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soon™️ is also gta vi

tawdry trench
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i still need to find a way to test using an existing kernel

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my own kernel is too bad

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managarm is too phd for me

tired steppe
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linux

median yoke
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We got gta6 before udrm

hexed flare
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Do you need mesa?

tawdry trench
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yes

errant onyx
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uDRMOS when

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for testing uDRM

tawdry trench
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lol

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i could do it with linux

errant onyx
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literally only does uDRM and nothing else

errant onyx
#

or a kernel module?

tawdry trench
#

userspace would be fucking based lol

errant onyx
#

yea userspace would be based af

tawdry trench
#

i mean udrm is meant to run on microkernels

errant onyx
#

do userspace then

tawdry trench
#

hm

errant onyx
#

it's easier for debugging too

errant onyx
tawdry trench
#

:3

errant onyx
#

without rebooting possibly

tawdry trench
#

good point

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time to clone kernel

errant onyx
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don't forget --depth 1

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and do you need the kernel for doing it in userspace? does linux expose the needed stuff to userspace?

tawdry trench
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uhhhhhh

errant onyx
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e.g. can you map a device's pci configuration space to a process?

half forge
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iirc for Linux userspace drivers you need a small kernel module that does hard irqs

errant onyx
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that's finee

half forge
#

but all other stuff can be done in userspace

tawdry trench
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yep

tawdry trench
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you can read pci cfg space through sysfs

errant onyx
#

udrm through sysfs is diabolical

tawdry trench
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i have not worked with linux userspace stuff before

errant onyx
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time to learn then!

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don't call the platform just linux imo

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call it linux userspace or something

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you might have a udrm in kernel space later

main crow
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i literally told you this before already btw

tawdry trench
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i have memory loss

main crow
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i can tell

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lol

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vfio is the stuff you do for passthrough

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so you pretend udrm is a """virtual machine"""

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so that you can steal the gpu for testing stuff

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and that works for modeset at least

agile halo
main crow
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huh

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on linux?

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im guessing integrated gpus are weirder tho

agile halo
#

the south bridge registers that are used for stuff like display detection just don't properly work

main crow
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ah

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damn lol

inner crater
#

I've never tried anything behind coffee lake tho

agile halo
#

yeah, I also tried it with the igd stuff but no dice (for an example SHOTPLUG_CTL + SDEIIR just returns all zeros regardless if there is something connected or not iirc)

inner crater
#

That might be some kernel meme tho

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Or

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Is that supposed to even work on that gen

agile halo
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it is supposed to work yeah, I tested it on bare metal boot and it worked just fine

inner crater
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Idk how sriov relates to all of it too

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Intel changed around how all of the virtualization modes work with tiger lake iirc

main crow
#

gpu moment

inner crater
#

It's almost like gpus are somewhat small computers of their own

tawdry trench
agile halo
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especially when you start to consider all the render stuff too

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EUs executing their own code and then communicating with the shared functions using message queues (well its not really exposed like that, its just a send() instruction to send a message to a specific target function)

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(on intel)

unkempt hearth
#

Re-asking here, what's the status of uAPI?

hexed flare
#

How is uDRM going? meme

tawdry trench
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i should have something working in the next few weeks

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i have little to do until march

hexed flare
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cool

tawdry trench
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im using linux as a test kernel since that's the easiest for me to work with and is guaranteed to have everything i need

tawdry trench
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okay linux is saying hello to udrm

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@maiden birch this might be too late but uapi is really not a convenient name

maiden birch
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got any better ideas?

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right now seems like the perfect time to change it since nothing uses it

astral gate
shut sorrel
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μapi

astral gate
#

µ

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yes

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require a system with a keybind for writing 'µ' for using uAPI

errant onyx
#

include/µapi

tawdry trench
astral gate
#

alright. a new name is needed

tawdry trench
#

udi

astral gate
#

uniform driver interface?

tawdry trench
#

yea

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but that's already a thing

astral gate
tawdry trench
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(although it sucks terribly)

astral gate
#

I think I read about something like that

tawdry trench
#

its just dead

median yoke
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mudi

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more unified driver interface

tawdry trench
#

unified udi

astral gate
#

my opinion is that we need no "uAPI"/common driver interface. the reason for this is that the kernel APIs required by eg. uDRM and uACPI differ substantially, to the point that the cost of maintaining a separate "uAPI" exceeds the benefit

tawdry trench
#

uHDA would also use it

median yoke
#

write the code for obos

tawdry trench
#

but you are right

median yoke
tawdry trench
#

do you have msix

median yoke
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yes

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(well I do after I fix the MSI-X code that broke once upon a time...)

tawdry trench
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im not against it

astral gate
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(this might be a bad example, I guess, because GPU drivers might want specific caching modes for certain things, and that cannot be done by uacpi_kernel_map as of today)

errant onyx
#

micro unified udi

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uuudi

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or maybe

astral gate
#

µuudi

errant onyx
#

advanced unified driver interface

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audi

hexed flare
#

Just ultraAPI?

errant onyx
#

imagine ultraAPI in linux

hexed flare
#

but linux has their own drivers

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(except uACPI eventually trl)

mortal harness
astral gate
#

(except ACPICA now)

mortal harness
#

i never saw a greater design by committee in my life

hexed flare
errant onyx
#

ultra advanced performance unified driver interface
UAPUDI

mortal harness
#

and i don't mind designs by committee but UDI is insane and the osdev wiki community sought to make it moreso by making it bytecode

astral gate
#

whattheactualfuck

mortal harness
astral gate
#

Let's not do that.

Screenshot_20250216_213559.png
shut sorrel
#

I actually wanted to implement udi once
thankfully people here stopped me

astral gate
#

you can design something really well

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and you can implement it really well

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those are two separate things.

mortal harness
#

the website is down

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1 second

astral gate
#

and I believe we should strive for the latter

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iirc Torvalds said something along the lines of "Linux is good engineering, not good design."

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and I agree with that to some extent

mortal harness
# 
static udi_pio_trans_t cmos_trans_read[] = {
        /* R0 <- SCRATCH_ADDR {offset into scratch of address} */
        { UDI_PIO_LOAD_IMM+UDI_PIO_R0, UDI_PIO_2BYTE, SCRATCH_ADDR },
        /* R1 <- address */
        { UDI_PIO_LOAD+UDI_PIO_SCRATCH+UDI_PIO_R0,
                                UDI_PIO_1BYTE, UDI_PIO_R1 },
        /* R0 <- SCRATCH_COUNT {offset into scratch of count} */
        { UDI_PIO_LOAD_IMM+UDI_PIO_R0, UDI_PIO_2BYTE, SCRATCH_COUNT },
        /* R2 <- count */
        { UDI_PIO_LOAD+UDI_PIO_SCRATCH+UDI_PIO_R0,
                                UDI_PIO_1BYTE, UDI_PIO_R2 },
        /* R0 <- 0 {current buffer offset} */
        { UDI_PIO_LOAD_IMM+UDI_PIO_R0, UDI_PIO_2BYTE, 0 },
        /* begin main loop */
        { UDI_PIO_LABEL, 0, 1 },
        /* output address from R1 to address register */
        { UDI_PIO_OUT+UDI_PIO_DIRECT+UDI_PIO_R1,
                                UDI_PIO_1BYTE, CMOS_ADDR },
        /* input value from data register into next buffer location */
        { UDI_PIO_IN+UDI_PIO_BUF+UDI_PIO_R0,
                                UDI_PIO_1BYTE, CMOS_DATA },
        /* decrement count (in R2) */
        { UDI_PIO_ADD_IMM+UDI_PIO_R2, UDI_PIO_1BYTE, (udi_ubit8_t)-1 },
        /* if count is zero, we're done */
        { UDI_PIO_CSKIP+UDI_PIO_R2, UDI_PIO_1BYTE, UDI_PIO_NZ },
        { UDI_PIO_END_IMM, UDI_PIO_2BYTE, 0 },
        /* increment address and buffer offset */
        { UDI_PIO_ADD_IMM+UDI_PIO_R1, UDI_PIO_1BYTE, 1 },
        { UDI_PIO_ADD_IMM+UDI_PIO_R0, UDI_PIO_1BYTE, 1 },
        /* go back to main loop */
        { UDI_PIO_BRANCH, 0, 1 }
};
shut sorrel
median yoke
astral gate
#

ACPI is (often) bytecode, and UDI is apparently also (sometimes) bytecode... lui (lightweight UDI interpreter) or uUDI when?

maiden birch
mortal harness
#

what's worse udi (from the relatively superficial inspection i made of it) seems extremely static

#

things must be defined in advance in properties textfiles and it looks to be an interface fundamentally incompatible with treating modern day needs like multi-queue devices with core local queues + MSIs

errant onyx
#

IT'S BECOMING REAL

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everything is being unified we're approaching singularity

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all osdev projects will merge

astral gate
#

... and that is a bad thing

errant onyx
#

yep

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but it's funny

mortal harness
#

and some, i assume, of UDI are good ideas

astral gate
#

if well over 90% of your code is just dealing with an interface instead of doing the work that it should be doing, that interface (UDI) is probably bad

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or rather

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it is a hint that a better interface is probably possible

maiden birch
#

No way this is real

tawdry trench
#

that's not fucking real

#

I refuse

astral gate
#

no. obviously fadanoid just wrote 5496 lines of actual code to make a joke

static prairie
#

surprising that they didn't at least invent some assembler for it so you don't have to fuss around with the arrays of structs by hand

mortal harness
tawdry trench
#

"""""simpler"""""

shut sorrel
#

lmao

tawdry trench
shut sorrel
#

definitely fewer lines

mortal harness
#

believe it or not there is allegedly a full USB stack that was implemented in this

tawdry trench
mortal harness
#

at least full by the standards of the late 90s

#

unfortunately it's sco so it's proprietary

maiden birch
#

and does anyone actually use them

tawdry trench
#

go figure

mortal harness
# maiden birch where do u get these

i have a copy of the UDI Implementor's Licensed Reference Implementation sitting on my hard drive from some time ago, probably 2023 when i last looked at udi

tawdry trench
#

i dont like this

maiden birch
#

Probably not a single soul does

mortal harness
#

amusing remark from there:

The complexity of ACPI makes people want to use ACPICA. The complexity of UDI should make people want to use Project UDI.

tawdry trench
#

lmao

mortal harness
tawdry trench
#

jfc

mortal harness
# 
    // - Reset Sequence
    // > Power on
    LOAD_IMM.B R0, 0x00;
    OUT.B Regs::Config1 as _, R0;
    // > Reset and wait for the reset bit to clear
    LOAD_IMM.B R0, 0x10;
    OUT.B Regs::Cmd as _ ,R0;
    LABEL 1;
    IN.B R0, Regs::Cmd as _;
    AND_IMM.B R0, 0x10;
    CSKIP.B R0 Z;
    BRANCH 1;
    // > Reset complete
    // > Disable interrupts
    LOAD_IMM.S R0, 0x00;
    OUT.S Regs::Imr as _, R0;
maiden birch
#

Like wtf

#

What is this doing even why is it needed

tawdry trench
#

aml if it was even worse

maiden birch
mortal harness
static prairie
maiden birch
#

Or ya know

#

Int x = 0

tawdry trench
#

💀

#

iirc udi drivers were supposed to be arch independent?

#

like fully

half forge
#

well judging by the example drivers posted earlier that's a failure

#

they still need C sources

maiden birch
#

The c language is like fully arch independent lmfao

tawdry trench
#

on a binary level

half forge
#

and if you need C sources why have bytecode

tawdry trench
#

^

maiden birch
mortal harness
#

the official reason, if you are interested, is because they thought in the future drivers would be run mostly on special coprocessors, and only those coprocessors would have access to the register spaces of devices

half forge
#

...why did they think that?

maiden birch
#

What the hell

tawdry trench
#

that's fucking stupid

mortal harness
#

so udi drivers require all such accesses to happen by instructions to the udi pio subsystem, so they can add support for these coprocessors in the future

tawdry trench
#

they didn't think of hardware vendors not giving a singular shit lmfao

maiden birch
#

Was it designed in the 70s

tawdry trench
#

i mean, look at the risc-v hardware people

#

it's literally a "everyone does what they feel like" situation

maiden birch
#

I've never seen driver coprocessors

mortal harness
#

they had some in old mainframes

#

channel i/o controllers

maiden birch
#

How old is udi

mortal harness
#

the committee sat from 1995 and completed the specification in 2001

maiden birch
#

Damn

#

Seems like an outdated idea at that point

tawdry trench
#

tldr unified interfaces are bad a lot of the time

mortal harness
astral gate
tawdry trench
#

i wonder if it's feasible to make a linux abstraction layer for the drivers

inner crater
#

freebsd does that sometimes

tawdry trench
#

i know they do it for the drm drivers

#

maybe that makes more sense tbh

tawdry trench
#

uDRM - a portable Direct Rendering Manager

hexed flare
#

How's uDRM doing? meme

tawdry trench
#

still doing research on xe modeset

maiden birch
#

X E

tawdry trench
#

intel X E.

unreal pagoda
#

i already made this joke

#

thieves

livid sentinel
#

What will be the oldest Nvidia card supported? I have a few quadro fx 570s lying around

unkempt hearth
tawdry trench
#

I'm currently only going to do nvidia gpud with GSP

tawdry trench
#

i think gtx 1660 also works?

#

cc @inner crater

inner crater
#

iirc 1600 series has GSP too

livid sentinel
#

How hard would it be to write a driver for such an old card if one would have full documentation?

inner crater
#

do you have full documentation?

#

also what do you mean by such an old card

errant onyx
#

i think they mean quadro fx 750

inner crater
#

holy shit that's ancient

#

idk, probably best to look at nouveau to figure out what it takes

hexed flare
#

I have a PC with AMD iGPU which has documentation for it...

#

Idk the one that was before GCN

tawdry trench
#

for amd i only have Polaris, Vega and RDNA3 cards

hexed flare
tawdry trench
#

the code is open

#

that's my documentation

#

also, i have my sources

#

i also have access to the pci spec meme

#

legally

robust abyss
#

What an osdev way to flex about money :^)

tawdry trench
#

wdym money

#

i didn't buy them lol

#

my company is a pci sig partner

obtuse matrix
fiery sierra
unkempt hearth
tawdry trench
robust abyss
dusky current
tired steppe
#

Any progress?

maiden birch
#

the project has been cancelled

shut sorrel
#

I saw an unread udrm thread and I got excited for a moment smh my head

inner crater
#

lil might be seeing some work soon™️

tawdry trench
#

yep

fiery sierra
#

With the help of ChatGPT I am continuing the work on this project

tawdry trench
#

no

shut sorrel
#

no

maiden birch
#

Good luck

shut sorrel
#

even luck won't help him

fiery sierra
#

Guys... I'm getting an error
cd: udrm: No such file or directory

#

How to fix

tawdry trench
#

sudo rm /boot/init*

fiery sierra
#

Didn't work

frozen matrix
#

Try rebooting then, must be busted state trl

tired steppe
tired steppe
maiden birch
#

lil

errant onyx
#

big

shut sorrel
#

if true

tawdry trench
frigid island
#

Would anyone be able to give me the gh link lol

#

I won't bother scrolling up this conversation on phone

tawdry trench
#

it's dead

frigid island
#

rip

#

why

tawdry trench
#

lil exists

#

from the managarm project

maiden birch
tawdry trench
#

also yeah using lil + a small drm handler isn't very hard

ivory depot
tawdry trench
#

but it's designed to support anything

ivory depot
#

does it have like 3d acceleration?

maiden birch
#

no

ivory depot
#

ig its time to buy a intel igpu

maiden birch
#

for nvidia use nvidia-open

#

it has a very large api surface tho

tawdry trench
inner crater
tawdry trench
#

intel arcs are pretty good

ivory depot
maiden birch
#

yes

#

port it