#lord84

1 messages ยท Page 1 of 1 (latest)

wise lynx
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which when reaches its full potential will be capable of time travel
looking forward to this

quaint magnet
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If it ever achieved time travel we would know about it by now

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He would've travelled in the past and talked to us

midnight scroll
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u unconditionally use xsdt if revision is >= 2

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u must check that its not null and fall back to rsdt if it is

wise lynx
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what if I use xsdt if it's not null

midnight scroll
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dont u use uacpi

wise lynx
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yes

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but I haven't gotten to switching to early table access

midnight scroll
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ah

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the logic is

if (rev >= 2 && xsdt)
  use xsdt
else 
  use rsdt
wise lynx
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ACPIRSDPHeader* rsdp = (ACPIRSDPHeader*)Arch_MapToHHDM(Arch_LdrPlatformInfo->acpi_rsdp_address);
bool tables32 = rsdp->Revision == 0;
ACPISDTHeader* xsdt = tables32 ? (ACPISDTHeader*)(uintptr_t)rsdp->RsdtAddress : (ACPISDTHeader*)rsdp->XsdtAddress;```
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that's what I do

midnight scroll
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if rev is 1 and u use xsdt it might contain random garbage

wise lynx
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of fixing that

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*ok

midnight scroll
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np

midnight scroll
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Yeah re read my message please

plush wadi
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xsdt is not guaranteed to be present on any ACPI system, even if its revision is greater than or equal to 2
instead you're expected to do this:

if (rsdp->revision >= 2) {
  if (rsdp->xsdt_address != NULL) {
    // Use the XSDT
  } else {
    // Use the RSDT
  }
} else {
  // Use the RSDT
}```
stray crest
plush wadi
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hope this helped ๐Ÿ™

midnight scroll
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in firmware world nothing is guaranteed

wise lynx
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what's up with your printf concern

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how print you do the letter 'n'

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kprintf("nn");

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?

quaint magnet
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Bruh

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\n does too and it's one character shorter

wise lynx
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and it needs no special handling

quaint magnet
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I understand why it may seem useful but it just confuses whoever looks at your codebase

wise lynx
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except for whatever the terminal emulator does with \n

plush wadi
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I'd assume you have some issue with memcmp, especially if you implemented it yourself
otherwise I'm not sure of why this comparison would fail, other than some other weirdness we can't see

plush wadi
wise lynx
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and that's not really a formatting specifier

plush wadi
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ahhh x3

plush wadi
quaint magnet
quaint magnet
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This is why you enable warnings

wise lynx
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-Wall -Wextra -pedantic -Werror -pedantic-errors

quaint magnet
# plush wadi wdym

If there's %n or {n} I expect there to be one parameter that maps to that argument

plush wadi
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meh, that's fair enough
too each their own I suppose

radiant robin
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You can use gdb to pause on the instruction after the write to cr3, and it'll let you explore the memory mappings before it faults

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Info mem and friends are helpful

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But also maybe print out what regions youre mapping so sanity checking

radiant robin
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How does a write to cr3 fail, did you miss?

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Ah I guess there are certain bits than can't be set

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What's the value you're trying to write, and the code that does it

radiant robin
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the hpet comparators let you select what gsi they fire.

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also for the purpose of calibration you dont need interrupts, you can poll the main counter

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yeah the first 2(?) comparators tend to only support fixed routing for the legacy compat mode

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where it replaces the PIT and something else - rtc timer?

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fair, but you also add complexity (and possibly to other parts of your kernel) for stuff you'll never use ๐Ÿ™‚

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you dont need to make use of everything the hardware offers

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just take what features you want and get on with what you wanted to do

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I say this as someone who used to add support for everything, but it gets exhausting when you get to more complex devices ๐Ÿ˜›

low sky
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orrr maye the time period he chose to go back to

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is a bit more later than now

glacial harness
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I recommend doing PCIe, it's much better

glacial harness
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Memory mapped, has a consistent access mechanism

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yes

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all pci devices should show up

midnight scroll
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what frosty recommends here is actually called ECAM, not PCIe. Its just a more modern PCI device discovery mechanism

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From wikipedia

The second method was created for PCI Express. It is called Enhanced Configuration Access Mechanism (ECAM). It extends device's configuration space to 4 KB, with the bottom 256 bytes overlapping the original (legacy) configuration space in PCI. The section of the addressable space is "stolen" so that the accesses from the CPU don't go to memory but rather reach a given device in the PCI Express fabric. During system initialization, BIOS determines the base address for this "stolen" address region and communicates it to the root complex and to the operating system.
glacial harness
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regardless, its much better

midnight scroll
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is each header 4k?

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btw not a good idea to read anything memory mapped as a C struct, there's a good reason why READ_ONCE and stuff is a thing in Linux

radiant robin
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Nice

wise lynx
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Wtf

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Cool

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Now test it

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Thoroughly

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Allocator bugs are the worst

glacial harness
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what type of heap was it?

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how did you implement the old one

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I'm genuinely curious how you made it that slow

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ah

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how big was the heap?

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interesting

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thats only 1MiB

glacial harness
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seems fairly simple. looks more like a PMM that a kernel heap though...

midnight scroll
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uint64_t pages_to_alloc = size / PAGE_SIZE;

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see anything wrong with this?

glacial harness
midnight scroll
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what if i request 4095 bytes

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how many pages do i want

glacial harness
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4095/4096 = 0

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so you would allocate nothing

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you should be aligning up

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pages_to_alloc would be 0

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so no iterations

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just align up

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then no confusion

wise lynx
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Your math ain't mathin

glacial harness
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I just use 2 macros:

#define DIV_ROUNDUP(VALUE, DIV) ((VALUE + (DIV - 1)) / DIV)
#define ALIGN_UP(VALUE, ALIGN) (DIV_ROUNDUP(VALUE, ALIGN) * ALIGN)
wise lynx
#

My kernel once had a bug because of a typo while aligning

glacial harness
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I think I first stole those macros from limine

midnight scroll
glacial harness
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GCC will optimise as long as I'm using constants

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if not, then I'll have to use some other magic to make it fast

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in my old kernel I had a log base 2 function for this purpose

midnight scroll
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i just do this

#define ALIGN_UP_MASK(x, mask)   (((x) + (mask)) & ~(mask))
#define ALIGN_UP(x, val)         ALIGN_UP_MASK(x, (typeof(x))(val) - 1)

#define ALIGN_DOWN_MASK(x, mask) ((x) & ~(mask))
#define ALIGN_DOWN(x, val)       ALIGN_DOWN_MASK(x, (typeof(x))(val) - 1)

#define IS_ALIGNED_MASK(x, mask) (((x) & (mask)) == 0)
#define IS_ALIGNED(x, val)       IS_ALIGNED_MASK(x, (typeof(x))(val) - 1)

#define PAGE_ROUND_UP(size)   ALIGN_UP(size, PAGE_SIZE)
#define PAGE_ROUND_DOWN(size) ALIGN_DOWN(size, PAGE_SIZE)
fathom talon
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that only works for powers of 2

wise lynx
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In compiler optimizations I trust

midnight scroll
fathom talon
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it is not the same thing, is all i am saying

midnight scroll
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thats true ye

wise lynx
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Only place I even remember aligning in is in my vma and FdSeek

fathom talon
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the "better" version of my version would be to special case powers of 2, but in any case that wasn't the intent of the macros

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they are not performance sensitive

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in Limine's case

midnight scroll
fathom talon
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i'll probably do that anyways

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these things just get under my skin in the sense that i have to sort it out after it's pointed out to me lol

dense night
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this should work

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at a glance

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what's PCIE_CONF_SPACE_WIDTH

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0x1000 * 8 * 32?

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oh

dense night
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btw why not write the code like: ```cpp
void check_function(uint64_t bus, uint64_t slot, uint64_t function) {
if(header_for(bus, slot, function)->vendor == 0xFFFF) return;

// do whatever

}

void check_slot(uint64_t bus, uint64_t slot) {
uint64_t max_functions = 1;
if(header_for(bus, slot, 0)->vendor == 0xFFFF) return;
if(header_for(bus, slot, 0)->type & MULTI) max_functions = 8;

for(uint64_t function = 0; function < max_functions; function++) {
    check_function(bus, slot, function);
}

}

void check_bus(uint64_t bus) {
for(uint64_t slot = 0; slot < 32; slot++) {
check_slot(bus, slot);
}
}

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functions 1-7 are handled exactly the same as function 0, except for the extra check for multifunction in function 0

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anyway base + (bus << 20) + (slot << 15) + (function << 12) should work for computing the address

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i don't know why it doesn't work for you

dense night
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mcfg does not talk about slots at all?

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each mcfg entry covers buses N-M and you check all the slots there

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or well, there are ways to avoid doing all the extra work of scanning empty slots, but that works too

dense night
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why require the square brackets around labels?

radiant robin
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Lock around any resource that needs it

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So if your print functions touch some state in a way that needs to be synchronized, put a lock there

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Ideally you would do as much per-core or per-thread as possible and only protect the global state, like the outputs where your logs go

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You can even go lock free if youre feeling clever

dawn pebble
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๐Ÿฆ†

radiant robin
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Generally you want to hold the lock as little as possible

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And yeah you also have to think about what the purpose of the lock is.

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Like locking around the framebuffer everytime you write a character is kind of pointless, because what if two cors want to write there

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You'd get multiple messages interleaved

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You probably want to output a single line of text (or maybe a single message) at a time, I'm assuming we're only thinking about the framebuffer as a way to output logs

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Agreed, and that's also super error prone. Now you have to remember that every time.

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Possibly, your lock should be around your shared state

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Sorry if this isn't making much sense, I'm quite tired

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First figure out what you're trying to protect: what parts of the code would cause problems if multiple people executed it.

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Yeah nice

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Flanterm also has some internal state, so that would also need locking, but it's the same idea. You're already preventing multiple accesses.

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NP ๐Ÿ™‚

wise lynx
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Make sure you have caching synced between CPUs

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The PAT MSRs might be different

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And MTRRs

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(cache disable)

dawn pebble
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you really don't need to put (uint64_t*)

wise lynx
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The PAT MSRs should be the same on all CPUs

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And the APs should not affect the BSP performance if they are doing nothing

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Afaik

dawn pebble
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how you sending output to terminal

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give me a tutorial

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you using gdb ?

dawn pebble
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if you want i can test your os on 2 computers

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it emulated as ahci

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in firmware setup

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and I have sata disk

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it's an old pc with amd athlon 2

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okay I'll try to test on more modern pc

wise lynx
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No

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It can be ECAM

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But I ignore the segment field

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And I am fine

midnight scroll
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address is literally that, an address

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its a struct

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grep it

south sable
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This is my thread now