Hyper

[frank charm]

its a custom bios

im looking at the code right now

and it doesnt make any sense

it does set carry on error

and sets 0xC on error

in my case the carry is not set

yet i see 0xC

https://github.com/bochs-emu/Bochs/blob/0b367fa227188bf60b1d9afac6adaf7500981f2e/bochs/bios/rombios.c#L5887

[somber sage]

well

I guess you are getting the real 1989 experience where 50% of bioses would have bugs or different return conventions than others

[frank charm]

no like

im literally looking at its code

do i really have to build and debug bruh

there isnt a return path where carry is not set but 0xC is set

[somber sage]

and there should be?

[frank charm]

well this is what i get

AH = 0xC

carry not set

ok fuck it lets build bochs i guess

[somber sage]

Oh I see

lol

maybe carry is being cleared by something after the interrupt?

[frank charm]

maybe, definitely not my code tho

[somber sage]

bizzare

[frank charm]

ok i figured out to how add print statements to bochs bios

random bullshit go

BRUH

the kernel loads after i added printfs to bios

its a fucking bochs bios bug

with printfs added to bochs bios

bios logs

@blissful pier there's a ub in bochs bios

hyper loads if i add printfs

i dont really want to debug this further idk lmfao

this fixes the bug

[somber sage]

oh yes

I also had a UB which got fixed by adding a printf

iirc it was a heap corruption

[frank charm]

this is highly cursed compile steps

so idk what it does in there

cool, i wasted about 3 hours debugging hyper

only to find out its a bug in bochs

OHHH

nvm

https://github.com/bochs-emu/Bochs/commit/908cea26ed18068594339805de8c5a3896408c20

bochs was clobbering EBX

which is where hyper stores offset

(the bootsector)

[full adder]

☠️

[frank charm]

pre-call vs post-call

the trash emulator

upper half of EBX gone

@blissful pier TLDR update bochs bios

[blissful pier]

[full adder]

wasn't UB

[frank charm]

nah it wasnt ub just bad code

[full adder]

the bios is just shit

lmao

[frank charm]

lmfao

[full adder]

how was this only found out last year

baffles me

[frank charm]

i think its a recent regression

[full adder]

has nobody EVER run into this issue before

[frank charm]

thats why

[full adder]

ah

how does that even happen wtf

whatever

[frank charm]

yeah like do they not test anything at all

this regressed like everything if u read the issues

firmware dev brain damage got even to bochs

[flint sapphire]

So itanium

[full adder]

64-bit intel x86*

[blissful pier]

Is it hard to target itanium?

(though it would suck since there's no physical hardware)

[flint sapphire]

idk ask @slim bough

[full adder]

is it hard to target risc-v?

(yes i know there's actual risc-v hardware)

[slim bough]

It depends

[blissful pier]

RISC-V is easy

[full adder]

yeah ik it's just less broken arm

but the joke was that there's barely any good risc-v hardware

much like itanium (i assume)

[slim bough]

Having no hardware makes it complex, but im sure you can speak to other community members and request they run something for you
You can use Open64 and GCC for the compiler stuff, but I'm not sure how to set up a proper compiler for userspace stuff
You can also test userspace programs using Ski, but i would advice against testing anything other than linux kernel releases with it in system mode

[blissful pier]

But there is some hardware

[slim bough]

Itanium hardware is ok, just dated

And it can be hard to find well priced servers that arent in blade form

[blissful pier]

I have looked at ebay and you can't get any

For a reasonable price

[slim bough]

Ive found a few, but the shipping tends to be a struggle

I always try to find nearby servers that i can pick up myself

But this is almost always in the US

[somber sage]

what the hell is itanium

This is so wierd

[frank charm]

itanium is based af

[somber sage]

128 gpr
128 fpr
64 wierd ass boolean registers

does linux boot this

[full adder]

yes iirc

actually, apparently not since 6.7 lol

[somber sage]

[slim bough]

https://github.com/johnny-mnemonic/linux-ia64

[frank charm]

huh

is 1600x1200 correct?

[blissful pier]

I haven't set any options for framebuffer

[frank charm]

no like

[blissful pier]

It's a 4K screen

[frank charm]

ah

btw have u tried uefi

[blissful pier]

No

Will it load 32 bit kernel?

[frank charm]

ofc

[blissful pier]

I think I'll just use a smaller monitor for now

I need to recompile everything to build the 32 bit build

[frank charm]

i wonder what 847 means

i dont think the spec explains it

[frank charm]

can i give u a few debug builds later to test out

on this monitor

maybe it just refuses to set 1600

[blissful pier]

ok

Also it's the fun AMD A10 PC which remaps lapics

[frank charm]

ah

i can already smell RetarBIOS

[full adder]

what the fuck

why

[frank charm]

it changes the id i think, not remaps

[full adder]

they don't like them at 0xfee000??

oh

[frank charm]

yea

[blissful pier]

It booted when I connected it with DP instead of HDMI though

(also, 32 bit pmOS fully booted baremetal )

[frank charm]

very strange

but

[frank charm]

is the res picked on this monitor different on hyper vs limine?

[blissful pier]

and did shutdown that PC with the power button

[blissful pier]

DP is monitor's native resolution

4K60

While HDMI is limited to 4K30

on there

I think it's HDMI 1.4 or some memes

[blissful pier]

And it picked the native res

[frank charm]

cool

[blissful pier]

@frank charm

(on 2 laptops )

[frank charm]

Whats the screen res on them?

[blissful pier]

800x480

[frank charm]

Lmao that makes sense then

Can u just set that res in the config?

For testing

It picks 1024x768 as at least if it cant get an edid

[blissful pier]

https://www.thephintagecollector.ch/2018/08/24/asus-eee-pc-700-series/

[frank charm]

Wonder how good its aml is

[frank charm]

How do u have two of them lmfao

[blissful pier]

idk they're not mine

[frank charm]

Whose are they

[blissful pier]

My friends

[frank charm]

Ah

[blissful pier]

Idk why he has two

I'm talking to him on discord bruh

[blissful pier]

It still fails

[frank charm]

After what

[blissful pier]

Can't pick the video mode

[frank charm]

No like

What did u change

[blissful pier]

video-mode:
width=800
height=480

[frank charm]

Lemme just give u a binary which dumps all existing video modes and we'll see

[blissful pier]

Btw you're Russian, right?

[full adder]

damn don't have my russian keyboard installed :^(

[frank charm]

ytes

this just lists all video modes and hangs

[blissful pier]

do you want to join?

[blissful pier]

Appartently its xrgb8888 640x480

[frank charm]

nah lol

i guess it doesnt expose 800 or maybe its actually less

[blissful pier]

it could be a wikipedia error

[frank charm]

ye

how tf do u even use such a tiny screen

[blissful pier]

idk

ask asus designers lol

[frank charm]

imagine actually doing work on it

[blissful pier]

pmOS booted

[gentle pumice]

shouldn't you look for the highest possible resolution and use it

[frank charm]

as a fallback, perhaps

[blissful pier]

uACPI had shut it down!!!!

[frank charm]

but there isnt a boolean which says "this is a fake native res, we didnt actually get an EDID"

[frank charm]

nice

does the fb work as well

on pmos

[blissful pier]

yes

[frank charm]

letsgo

[blissful pier]

like it fully booted

[frank charm]

u should record a video

like if theres any init errors

[blissful pier]

(except he had to press enter for it to shut down)

[frank charm]

what uacpi said

[frank charm]

lol pmos qemu bug

[blissful pier]

i think it's timers skill issue

[frank charm]

basically the default constraint is "at-least", and it uses 1024x768 as the minimum sane res unless overridden in config

[blissful pier]

the second one worked as normal

[frank charm]

arent they identical?

[blissful pier]

no

[frank charm]

oh

[blissful pier]

they have different bios

[frank charm]

i see

cool that it worked

its 32-bit only right

maybe i should set 0x0 as the default if none is specified

[blissful pier]

we only set 640x480

I think it had EC?

bruh

[frank charm]

hard to tell

same amount of ops as qemu lol

these modules take 10 years to load bruh

they also have like an almost stubbed out VBE

with one single video mode

and there is an EC yeah lol

[earnest cliff]

eee pc, damn

about 18 years ago they were saying these were revolutionary and the new "netbook" form factor would be huge

but it turned out to be neither fish nor fowl when the ipad was released and turned tablets into appliances

[gentle pumice]

Are you russian ?

[blissful pier]

I'm not the person talking in the video, but yes...

Though I haven't been living there for a long time now...

[gentle pumice]

I am too russian, I live in Moscow Where do you live ?

[blissful pier]

I'm also from Moscow...

[blissful pier]

But now live in Barcelona

[grave nimbus]

good lord

[frank charm]

yes bochs is very high quality software

[flint sapphire]

me when:

Program Headers:
  Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
  LOAD           0x001000 0xffffffff80000000 0xffffffff80000000 0x0022c6 0x0022c6 R E 0x1000
  LOAD           0x004000 0xffffffff80003000 0xffffffff80003000 0x000150 0x000150 RW  0x1000
  LOAD           0x005000 0xffffffff80004000 0xffffffff80004000 0x000001 0x000001 R   0x1000
  LOAD           0x006000 0xffffffff80005000 0xffffffff80005000 0x0553ac 0x0553ac R E 0x1000
  LOAD           0x05c000 0xffffffff8005b000 0xffffffff8005b000 0x010de3 0x010de3 R   0x1000
  LOAD           0x06d000 0xffffffff8006c000 0xffffffff8006c000 0x101560 0x572e18 RW  0x1000```

ok a clean rebuild seemed to have made it go away

nvm

ok I fixed it

[blissful pier]

@frank charm do you have test images with PAE support?

Hyper seems to triple fault if I request it

If I enable KVM, or on physical hardware

And if it doesn't (in QEMU + TSC), something is messing with ACPI tables, and I also suspect that it might be it and not my kernel

[blissful pier]

Before reaching the kernel; I have a couple of PCs with serial ports, and the kernel didn't print anything (it's the first thing it does when entering it)

And commenting that out boots and works as normal, as if nothing had happened

(i686 kernel with PAE)

(also, memory map returns misaligned entries)

[frank charm]

Commenting what out

[frank charm]

Thats normal(?)

[frank charm]

Ill give you one

[frank charm]

ok jesus

thanks to bochs this was easy to figure out

apparently base PAE pointers have r/w bits as reserved

so you arent allowed to set them

wtf

if (pt->root == (void*)PAGE_ROUND_DOWN((ptr_t)table)) {
    entry &= ~PAGE_READWRITE;
}

Adding this fixes the triple fault in kvm

why did they do it this way in PAE tho

wtf

[cloud grove]

least retarded pre amd64 Intel extension

[frank charm]

thank god bochs did a PDPTR check failed log thing

this would take a lot of of time to figure out

[cloud grove]

bochs saves the day once again

[frank charm]

true

[blissful pier]

What

Could this also be Hyper?

[frank charm]

no

[blissful pier]

3 levels request

[frank charm]

#x86 message

[blissful pier]

Because it's fully working otherwise (for some reason), but ACPI tables are all messed up...

[frank charm]

bug in your maping function

i mean u see it contains some ascii string

u either corrupted it or mapped something else

[blissful pier]

those strings only appear in bios/qemu binary...

[frank charm]

see point 2

[blissful pier]

Where is it?

[frank charm]

hyper code

do u make sure to keep this zero as well btw

[blissful pier]

I've changed it just now

[frank charm]

@@ -82,7 +86,11 @@ static void *table_at(struct page_table *pt, void *table, size_t idx)
     memzero((void*)page, PAGE_SIZE);

     entry = (ptr_t)page;
+
     entry |= PAGE_READWRITE | PAGE_PRESENT | PAGE_NORMAL;
+    if (pt->root == (void*)PAGE_ROUND_DOWN((ptr_t)table)) {
+        entry &= ~PAGE_READWRITE;
+    }

if you want to fix the triple fault locally

[blissful pier]

I think the pointers here point to reserved memory (?)

Memory map entry 0: 0x0 - 0x7000, type 1
Memory map entry 1: 0x7000 - 0x80000, type FFFF0001
Memory map entry 2: 0x80000 - 0x9F000, type 1
Memory map entry 3: 0x9FC00 - 0xA0000, type 2
Memory map entry 4: 0xF0000 - 0x100000, type 2
Memory map entry 5: 0x100000 - 0x147000, type FFFF0004
Memory map entry 6: 0x147000 - 0x75B7000, type 1
Memory map entry 7: 0x75B7000 - 0x75BB000, type FFFF0003
Memory map entry 8: 0x75BB000 - 0x7FB2000, type FFFF0002
Memory map entry 9: 0x7FB2000 - 0x7FB3000, type 1
Memory map entry 10: 0x7FB3000 - 0x7FBB000, type FFFF0001
Memory map entry 11: 0x7FBB000 - 0x7FDE000, type 1
Memory map entry 12: 0x7FDE000 - 0x7FDF000, type FFFF0001
Memory map entry 13: 0x7FDF000 - 0x8000000, type 2
Memory map entry 14: 0xB0000000 - 0xC0000000, type 2
Memory map entry 15: 0xFED1C000 - 0xFED20000, type 2
Memory map entry 16: 0xFFFC0000 - 0x100000000, type 2

[frank charm]

u mean RSDP?

sure thats possible

[blissful pier]

and the other ones

[frank charm]

thats fine

[gentle pumice]

wtf what's wrong with this memory map

[frank charm]

?

nothing?

[gentle pumice]

why there's type FFFF0001

[blissful pier]

And now it's seabios...

[frank charm]

ultra memory types

[blissful pier]

Now it tripple faults without KVM...

[frank charm]

nah it doesnt

it will triple fault for non-pae tho

its just a pae-specific fix

[blissful pier]

Sorry, I'm dumb and couldn't properly apply a patch

Wtf, it's very consistent

[frank charm]

memory corruption

[gentle pumice]

I have one question

is hyper is super bootloader or kernel

[frank charm]

exactly the same as limine

this output is from his os not hyper

[gentle pumice]

a ok

[frank charm]

hes just trying to blame hyper

[blissful pier]

it's not hyper probably

but wtf, how does it also end up reading BIOS memory on physical hw?

[frank charm]

what makes you think its bios memory

[blissful pier]

Like this is very specific

ALASKA is bios?

[frank charm]

alaska is the correct OEM ID

for RSDP

the XSDT is not mapped correctly tho

[blissful pier]

I think that the phys map function must somehow be broken...

(anyway, this is the wrong thread)

[frank charm]

like the RSDP looks fully valid

revision, size, oem id etc

[cloud grove]

i heard Limine mentioned

[frank charm]

nah

lol

false alarm

[blissful pier]

idk it must be something very stupid

i've put printfs everywhere, and it's mapping the same memory with and without PAE

[somber sage]

we were just saying that hyper is better than limine

[raw dome]

does hyper garantee a minimum stack size or offset during handover or do i need to find a ULTRA_MEMORY_TYPE_KERNEL_STACK entry to figure out how large the boot stack is

[cloud grove]

are you actually using Hyper because of your cursed laptop?

i thought it was a joke

[frank charm]

Read the Ultra spec, pretty sure its specified, also you can configure the size yourself

[raw dome]

ah 16k i see

[somber sage]

16K stack is gluttony

You can bootstrap an allocator from that

What memory region is it in.

[somber sage]

Is the LOADER_RECLAIMABLE or how is the stack market

[flint sapphire]

meanwhile limine:

[somber sage]

Crazy

[blissful pier]

pmOS allocating multiple 8KB arrays on stack:

[cloud grove]

16k is pretty tight

you have to remember that languages other than C exist

Limine does 64k because that's about the minimum you kinda need for Rust to work semi-comfortably

[blissful pier]

rust skill issue

[blissful pier]

(this is an exaggeration, I only allocate one at most and 16K stack seems to be enough )

[full adder]

more like core::fmt skill issue but yeah

[frank charm]

this is disgusting tbh

i mean rust memory usage

[frank charm]

KERNEL_STACK

[somber sage]

👍

[somber sage]

Wait what? What does rust put there wtf??

[cloud grove]

Rust stuff

[raw dome]

crust

if you will

[earnest cliff]

listne

if you use the stakc

it's memory safe

[raw dome]

are file modules addresses virtual or physical?

because in qemu hyper gives me a virtual address, and on real hardware its giving me a physical address

[blissful pier]

The're supposed to be physical

(I always get physical)

[raw dome]

hmm i think i was getting lucky with the hhdm offset on qemu then

what kind of sicko gives a cpu a maxpaddr bits of 39

[blissful pier]

Are you targeting 32 bits?

[blissful pier]

What's wrong with that?

[raw dome]

it not an even number

its sin for computers to not use limits that arent powers of 2 tbh

at least a multiple of 2

[blissful pier]

You just shift 1 by it?

[frank charm]

Uhhh should be virtual iirc

Id have to look at the spec

ah nvm

if (is_higher_half_exclusive) {
    spec->higher_half_pointers = true;
    hi->flags |= HO_HIGHER_HALF_ONLY;
}

they're HHDM for higher half exclusive

[blissful pier]

Limine passes everything as virtual iirc

[frank charm]

this is basically limine by default i think

[somber sage]

How do you

Do stage 2 on ISO9660

[frank charm]

i did this like 3 years ago i barely remember

boot info table

maybe this is helpful

[somber sage]

Could you please add bios32 APM support?

Just give us the segments given to you by the bios in an attribute

[frank charm]

what is that

[somber sage]

Ideally also configure it to use not 1.0 but 1.1 or 1.2

[somber sage]

APM

[somber sage]

Bios interface for power

[frank charm]

do u have docs for it

[frank charm]

i know that

idk what u expect me to do with it tho

[somber sage]

Set it up for us so we dont have to go to real mode to configure it

[somber sage]

http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/APMV12.rtf

[frank charm]

where do i look for what u want me to do

[somber sage]

Connecting to an interface

4.6.4

And 4.6.15

To tell the bios we aint using legacy stuff

And we want modern version

[frank charm]

interesting

are u sure your pc has that

[somber sage]

Yes

I checked from basic

[frank charm]

32-bit specifically?

[somber sage]

I checked real mode and 32 bit protected mode interface both is avalable and it has version 1.1

[frank charm]

huh ok then

[somber sage]

But i hope that 1.1 and 1.2 has mostly the same stuff

I might try to find the 1.1 docs

[somber sage]

Also according to this: Mailing list on PnP bios calls, the 16 bit protected mode PnP interface should work in 32 bit protected mode, as the bios is supposed to explicitly checks for a 32 bit stack with LAR and work in a flat 32:32 model as well as the native 16:16. The osdev wiki seems to support this Osdev on PnP in protected mode. I am not sure if there is something that has to be done in real mode to configure it like APM, but I will check and come back to you with the findings.

[frank charm]

sure

[frank charm]

Finally fixing the PAE bug @blissful pier

[blissful pier]

Cool

(I also went for prepopulating page tables in pmOS kernel)

[fast river]

btw this is what everybody did on pae

[frank charm]

yeah i mean makes sense

[frank charm]

thought u didnt know much about x86

[fast river]

well that was a virtual memory related fun fact so ofc i know it

[frank charm]

lol

[fast river]

ik the broad strokes about x86, i mostly mean "dont listen to me i havent actually done an x86 kernel" when i say that

[frank charm]

well thats gonna change soon hopefully

[fast river]

theyd do recursive mapping of the page tables by inserting all 4 page directories into 4 consecutive entries of one of them

which produced the same effect of the unrolled page tables

[frank charm]

makes sense

[blissful pier]

But you're throwing away 1GB of address space

[fast river]

thats only 8MB

i think

[blissful pier]

Then I don't get it

How do you access the top level then?

[fast river]

you dont access the top level thru the recursive page table if you do this

in fact if its preallocated you dont access it at runtime at all, only at process creation and destruction

[blissful pier]

I still don't believe in recursive page tables...

[fast river]

they dont believe in you

[frank charm]

How do u handle paging on i386?

[fast river]

who u asking

[frank charm]

well u dont even support i386

[blissful pier]

Without recursive page tables

[frank charm]

yes but how

[fast river]

hhdm

[blissful pier]

temp mappings

[blissful pier]

I don't use hhdm even in x86_64 port

[fast river]

yeah but how do you access the page tables to make those

[blissful pier]

I reserve 16 virtual pages for each core, and map a window into the leaf page table

[fast river]

how is this better than a recursive page table

[frank charm]

less address space?

[blissful pier]

I don't have to flush cr3 every time I change page tables, or want to change mappings of a process that's not active

And it uses little address space

And allows to access any memory on 32 bit platforms

[fast river]

not an issue, it only takes up 1/1024 of the 4gb address space

[blissful pier]

Like I support up to 16GB RAM on i686

[blissful pier]

(compared to HHDM)

Like I've used recursive page tables initially, and got fed up with it

[blissful pier]

Also they don't work on RISC-V

[fast river]

i dont get the first thing, youre setting cr3 anyway when you change page tables

and you only rarely access remote mappings (in other processes)

[blissful pier]

In monolithic kernels

[fast river]

well microkernels are gay so idc about them

[frank charm]

why only 16

[blissful pier]

As in you change page tables, you have to flush cr3

[blissful pier]

So I don't have too many struct Pages

[fast river]

still dont get what you mean by "flush cr3"

[blissful pier]

Flush TLB

[fast river]

wdym just make them according to however much physical memory you have

[fast river]

are you using PCIDs

[blissful pier]

No

[fast river]

okay so... when u change page tables youre always flushing the TLB anyway

[blissful pier]

I might eventually

[fast river]

regardless of whether you have recursive page tables

[blissful pier]

No?

I think I'm not using the right term

[fast river]

if you set cr3 (which you must do to switch page tables) you are flushing the tlb

[blissful pier]

Yes

CPU can cache recursive entries. Let's say you change 2nd level of page tables, all tlb entries of recursive entry become non valid

[frank charm]

accessing them might be a problem tho

[blissful pier]

I could probably change it to 64GB or something

[fast river]

in practice you dont change a pde until youve invalidated all of the pages tracked in the corresponding page table first

if im understanding you right

[blissful pier]

Probably

But I remember having to change page tables of other processes, and it was forcing me to flush tlb all the time

[blissful pier]

Like the only disadvantage I see with this is that it potentially increases the number of page walks

And if I can access any memory through it, why not use it for page tables

[fast river]

i only(*) have to do this when im trimming pages from working sets and have to invalidate them in the process's page tables, and i temporarily assume the target process's address space to do this

this doesnt flush the tlb because i have ASIDs cuz im on a less skill issued architecture

[blissful pier]

I can probably add asids but would need to make changes to my tlb shootdown code

And also I haven't come up with a scheme of their allocation and sharing

[fast river]

i figured out what im pretty sure is the optimal way to do it

basically you attach an array to each process that has as many slots as you have cores

each slot is an ASID

you allocate ASIDs per-core and record it in this array as threads from the process are scheduled into the various cores

each array entry also has a sequence number

when theres an ASID roll-over on a core, it increments a sequence number; when processes are scheduled in on that core in the future, they notice the mismatch between the core's sequence number and the one in their array entry, and so they re-allocate their ASID and remember the new sequence number

also an ASID roll-over causes the core to flush its whole TLB (this is rare)

[blissful pier]

My kernel doesn't have to do that, it can just change and access memory and page tables of any process regardless the active address space, without switching to different ones

[blissful pier]

Do you allocate ASIDs per core?

[fast river]

yes

[blissful pier]

How do you decide where to send TLB flush IPIs then?

[fast river]

i dont get how this is related

[blissful pier]

Like my kernel only flushes entries of cores which have page table applied at that moment

Like if a process is single threaded, or other threads are not running, there are no IPIs

[fast river]

you can keep a bitmask in your process structure that tracks the cores that threads from the process have been scheduled in on

if you send a full flush IPI to all the cores whose bits are set you can clear the bit mask

[blissful pier]

I don't do full flushes

[fast river]

then you cant clear the bit mask

you just have to send ipis to all those cores forever bc theres no good way to know when they dont have any stale entries anymore

so you might want to Sometimes do a full flush

like every 32 pages you flush you just send a full flush IPI and clear this bit mask

[blissful pier]

I have a generation counter

[fast river]

what do you use it for

[blissful pier]

to know which cores have stale entries

Yeah idk it can be fixed

[fast river]

are you sure this stays applicable once you have ASIDs

and switching process =/= clearing tlb

[blissful pier]

It would stay applicable with a modification I guess

Like I could probably do full flush of inactive processors, and pinpoint flush of running ones

[blissful pier]

At the moment it is what I do

[fast river]

@frank charm sry for hijacking ur thread

[frank charm]

idc lol

[fast river]

true you do have two of them

[frank charm]

tru

[blissful pier]

Idk, I'm thinking about it and I will probably add asids eventually, but it's not a priority

[blissful pier]

https://gitlab.com/mishakov/pmos/-/blob/main/kernel/arch/x86_64/paging/x86_temp_mapper.cc?ref_type=heads

[north smelt]

i love recursive page tables

except when i have to check whether the page exists every page boundary my PTE pointer crosses but thats fiiiine

[fast river]

dont have to do this when you Assume its there eternally (this is how i do most system VA management)

[north smelt]

you can't do that on x64 unless you want to use an obscene amount of physical space per process

i could add a thing to fault them in if they're missing but

[fast river]

no

i mean specifically for kernel space VA management

i preallocate page tables for dynamic regions of kernel space

and then i can use simple math to calculate pte pointers inside that and then i just use those without checking if the page table exists bc i know it does

[north smelt]

what kind of dynamic kernel VA space do you do this for

[fast river]

i have 3 dynamic regions

one of them i use to map heap extensions, and i allocate and free it by popping single PTEs from a free list threaded thru the PTEs of the page tables for that region

another one is managed by a bitmap and is for > page size virtual allocations

the third one is managed the same way as the first except in like 64k chunks rather than page size chunks and ill use that to allocate windows for the file viewcache

[north smelt]

in your case you dont have to allocate too many PTs because your page table structure is only two level

i have to deal with 4 levels and as such it'd be more complicated to try to do something like that

and i also have a lot wider of an address space anyway

[fast river]

not really

[north smelt]

also the thing that was on my mind when I wrote that was user half address space management

[fast river]

you dont fill the whole thing up...

i do something like 4 * physical memory size as a rough estimate of how much will be needed

[north smelt]

but YOU seem to:

i preallocate page tables for dynamic regions of kernel space

[fast river]

thats not what that says though

the dynamic regions are sized at boot time according to what i just said

[north smelt]

you preallocate page tables for dynamic regions of kernel space

[fast river]

and other heuristics

yes

[north smelt]

oh, ok

right

[fast river]

nowhere in there does that imply they fill the entirety of kernel space

im not a moron

lol

[north smelt]

right

[fast river]

obviously i would not do that

[north smelt]

so they're capped to that fraction of physical memory

i mean, the PTs allocated

and this reflects in the amount of pages in those dynamic regions you can map

eh whatever

[north smelt]

can you tell me what you mean by "mapping heap extensions"

what are they

[fast river]

ran out of heap, need to extend the heap

[frank charm]

Hyper CI bitrotted into oblivion because I haven't touched it in a while, but I fixed it now

@blissful pier I've also merged the pae fixes

Hyper is now at 666 commits

[blissful pier]

cursed

[ornate locust]

the bootloader of the beast

[frank charm]

lol

[blissful pier]

Btw have you considered adding loongarch?

[frank charm]

Can clang natively produce a pe for it?

[fast river]

loongarch vs shrtarch

[blissful pier]

MIPS vs MIPS

[raw dome]

llvm can target loooongarch iirc

[blissful pier]

but you need pe

[full adder]

i dont think so

last time i tried i couldn't get it to

[frank charm]

then ill wait for it to mature, same as risc-v

[earnest cliff]

i worry it might take a while

loongarch probably is in a better position though

they let anyone make riscvs

[somber sage]

APM when

My real mode stub to init it doesn’t work

Maybe I can just

make a branch

Implement it

test it

make a PR

[frank charm]

Yeah, or it might not happen at all unfortunately

[frank charm]

What was it again, just make one bios call to init it?

[somber sage]

One to check its there one to query modes one to enter the latest (or requested) version one to connect the bios32 interface

And it gives you iirc base and limit for a segment that its located it

[grave nimbus]

Are you sure your machine supports APM 1.2? Earlier versions didn't require a 32-bit protected mode interface

[somber sage]

From what I checked yes it does

It has 1.1 but has a pmode interface

[grave nimbus]

How did you check?

[somber sage]

Connetcted the p mode onterface

[frank charm]

does it actually shut down via it

[somber sage]

And it didnt return errcode7state could myo be enetered

[somber sage]

Idk

[frank charm]

can u test that it works at least

u can patch hyper locally to do that via a few bios_call's

just as a quick hack for testing

[somber sage]

I cant boot hyper on the device

[frank charm]

why?

and if u cant, why do u even want it to support that

[somber sage]

I can from disk

Ill make a hyper installer later

[frank charm]

like u have to install it to disk to test?

[somber sage]

Yep

b cause my custom is broken

CdRom

[frank charm]

oof

[somber sage]

yeah and I couldn’t find any cheap PATA cdroms near me

So I have to transfer everything on floppies

[somber sage]

Suspend to ram works though

I tested that

[somber sage]

Ok so I am looking at the codebase and I am guessing the thing we should do is put it into hyper protocol specific stuff? Starting from ultra_protocol_static void ultra_protocol_boot(struct config *cfg, struct loadable_entry *le) and also add the APM BIOS32 info into somewhere to somehow get it into a modified attribute? I still have to figure that out.

Probably into the attribute array and have to modify build_attribute_array

[frank charm]

Dw about it I'll do it myself

[somber sage]

Oh ok thanks

[frank charm]

Np

[somber sage]

Ok looking forward to obtaining si di es ebx from the connect call (aka the segment values)\

[somber sage]

Also please don’t enable callback events

I don’t want a 16 bit handler for apm callbacks

[somber sage]

Also this might be very usefull

https://psomas.wordpress.com/2011/04/09/linux-x86-segmentation-apm/#:~:text=%2F,code to that CPU

[somber sage]

Also we might have to check the APM data region doesn’t collide with any of the non-free entries (loader used, modules, kernel or kernel stack)!

[frank charm]

is it specified inside the memory map?

[somber sage]

Also after an installation check we should first issue a disconnect (because nvs issues?) and only then connect the 32 bit interface

[somber sage]

I don’t think so, the connect interface call returns the bases and limits of the segments where code is in rom but data might be in ram

[frank charm]

so what are u supposed to do if it collides

[somber sage]

I can’t find any resources which explicitly state if it is.

🤷‍♂️ relocate the kernel/stack/module

I don’t know

[frank charm]

why would it be in free memory lol

anyways if u set it up before loading the kernel its fine

[somber sage]

I don’t know the specs just define it as a “memory region” so there is nothing preventing the bios from using some ram

“Also Linux will ignore small segment limits provided by the BIOS and always
set the segment limit to 64K. This is necessary as some BIOSes get the
limit values wrong.

Linux will call BIOS functions with a selector of 0x40 pointing to the real
mode address base of 0x40:0. Many BIOS functions rely on this selector being
present even though the specification does not permit the assumption.

Options control whether BIOS functions are invoked with interrupts enabled
or disabled. A correctly functioning APM BIOS should not care but some do.”

Quoting from https://lwn.net/2001/0628/a/bios.php3#:~:text=Linux supports APM power management,APM BIOS service calls in

[frank charm]

in the docs u sent it says events are polled

[somber sage]

I mgiht have consumed too much info with unreliable sources but I though there was both polling and interrupt callback. Maybe that was onyl real mode?

[frank charm]

dunno, i dont see anything about async events

@somber sage soo likke

do u want 16-bit protected mode as a fallback or

or what if neither are supported

https://elixir.bootlin.com/linux/v6.13.6/source/arch/x86/boot/apm.c#L19

ill just do this

I'll add like an apm-setup boolean to ultra protocol

[somber sage]

I test it and I have the 32 bit interface, so I dont really know. The 16 bit protected mode isntead really usefull because you still have to disable paging./

[somber sage]

Yeah thats good.

[frank charm]

ill just do what linux does

since i have no way to test this on anything anyway

[somber sage]

iirc bochs supports it

Yep

[frank charm]

thats cool ig

[somber sage]

So does SeaBIOS

But Ill test it on device.

[frank charm]

sure

[somber sage]

I love you sir

[frank charm]

lol np

@somber sage this good enough?

struct ultra_apm_attribute {
    struct ultra_attribute_header header;

    uint16_t version;
    uint16_t flags;

    uint16_t pm_code_segment;
    uint16_t pm_code_segment_length;
    uint32_t pm_offset;

    uint16_t rm_code_segment;
    uint16_t rm_code_segment_length;

    uint16_t data_segment;
    uint16_t data_segment_length;
};

[somber sage]

Isn't it 32 and 16 pm segments? But yeah I think this should be enough.

[frank charm]

dont think so Both 32-bit and 16-bit code segment descriptors are necessary so the APM BIOS 32-bit interface can call other BIOS routines in a 16-bit code segment if necessary

it's for internal use by APM

[somber sage]

Fair enough.

[frank charm]

and the spec calls them real mode segment base address

[somber sage]

Ok fair enough.

[somber sage]

666 commits

[frank charm]

alright works on qemu

bochs worked as well

[somber sage]

Nice.

[frank charm]

this seems to pass as well

@somber sage can you test this on your hw? https://github.com/UltraOS/Hyper/pull/65

[somber sage]

I will try but I will need to write a dos thingy to install it from floppy onto a hdd

[frank charm]

i mean i can merge as is, but it would be cool if you could verify that it works at all

[somber sage]

Yeah ill do it sometime today (hopefully)

[blissful pier]

Dumb question, but didn't that hardware already have PXE?

[somber sage]

yes it did

And there is this funny rom chip on the network card

that holds the firmware

[blissful pier]

Then why not use that?

I don't remember if hyper supports it

[somber sage]

This is the firmware chip on the network card.

[grave nimbus]

That's not a chip...that's a socket

[blissful pier]

can you not get a random newer network card for it?

[grave nimbus]

tbh most cards from the 90s didn't come with boot roms, you had to buy them separately. And they usually used Novell's IPL system to boot, not PXE.

iPXE should work though, and you can boot it from floppy instead of dealing with getting it written to an EEPROM

[blissful pier]

no, but I mean you can probably get a cheap "modern" PCI card

[somber sage]

I could but i already yave the RTL8029AS

[frank charm]

Any updates?

[somber sage]

No sorry i’ll try to get it done tomorrow i had a lot on my plate

[frank charm]

Np (hopefully that was food)

[somber sage]

Also watcom is horrid with modern toolchains (like an IDE) and i have to test with qemu as dosbox doesn't emulate raw disk io

Actually watcom is horrid period. I don't like dos style arguments, unix>>>

[earnest cliff]

you can use the watcom IDE

it even includes a VI-style editor

[somber sage]

I think i will try to get clangd vscode extension to recognize $WATCOM/h as include path instead.

[earnest cliff]

you can try but i'm not sure it'll do you any good

clang is a ripoff of gcc, the C it accepts is GNU C, not Watcom C which is entirely different

[somber sage]

I meant it doesn’t seem too different? It uses ansi c and if I get headers to be included it should work no?

[somber sage]

Yeah you are right

it absolutely didn't handle it

Can I open D: in dos

Hyper doesnt compile for me.

Oh because the header is on a detached commit inside the Ultra protocol branch @frank charm

Ok just a todo to not forget

[frank charm]

PR points to ultra protocol master

so not sure what u mean

[somber sage]

Huh thats wierd

[frank charm]

\

[somber sage]

oh right

yeah I am stupid

wait no

wait yes

I init submodules on wrong branch

[frank charm]

lol

[somber sage]

yeah my bad

I am slightly incompetent

[frank charm]

lol np

[somber sage]

how on earth does huge work inw atcom

[somber sage]

Stage2 is over 64k in size 😭 it can't fit into a segment.

[frank charm]

why does it need to fit in a segment

[somber sage]

🤷

[frank charm]

it's a raw binary, that is mostly protected mode

[somber sage]

I mean when compiling a mz executab;e

[frank charm]

also, why do u need to compile it, like just grab a precompiled one

[somber sage]

I can't embed it

so ill prolly just

make it a .DAT and have it load on rutniem

[frank charm]

damn

yeah idk what ur cooking

[somber sage]

Wdym

I mean

I can't embed the stage2 as an array into the executable

because its too big

[somber sage]

like you do with the installer

[frank charm]

have it as a separate file

or compress ig

[somber sage]

thats what im gonna do.

[somber sage]

Ok I hate real mode

[frank charm]

who doesnt

[somber sage]

I have to malloc it in segments because this stupid compiler can’t handle cross sogment allocations + it’s a hassle to do any fine grained programming like relocating the fat stuff

[somber sage]

It can shutdown 🥳

[frank charm]

Nice

[raw dome]

got a motherboard that fails to boot with this error, my config is ```ini
default-entry = "BezOS"

[BezOS]
protocol = ultra
higher-half-exclusive = true

stack:
size = 0x4000

binary:
path = "/boot/bezos-hyper.elf"
allocate-anywhere = true

module:
name = "initrd"
path = "/boot/initrd"

module:
type = "memory"
name = "allocator-bootstrap"

# 1M
size=0x100000

video-mode:
width=800
height=600
bpp=32
format=xrgb8888
constraint=at-least

motherboard is an ASUS TUF-Z270MK2

changing the stack size doesnt resolve the error

v 0.9.0

[ornate locust]

does Limine work?

[frank charm]

Huh, thats quite interesting

[frank charm]

Any diff on bios vs uefi there?

Oh wait its just a simple code bug

@raw dome this should repro on qemu, does it not?

Basically in this case it thinks allocation ceiling is the address because you didnt specify one, but did specify the size

Ill fix in a bit, thx

[frank charm]

yeah it repros on qemu

thats the fix

[raw dome]

Oh I couldn't repro it on qemu

[frank charm]

It only repros under uefi

[raw dome]

Ah, I'll apply that patch and give it a go on that motherboard again

[frank charm]

Ill upstream the fix today as well

I need to draft a new release since its been a while for hyper

[somber sage]

Son of a gun

Didn't shift my selectors

and I am out here pulling my hair

https://tenor.com/view/arlo-arlo-madness-descent-into-madness-black-cat-kitten-gif-2862695181199001234

[somber sage]

Ok APM now works, turns out SeaBIOS uses ACPI under the hood in APM calls and when you disable ACPI with qemu flags.. the bios just cli's and enters an inifite loop.

[frank charm]

Lol

[frank charm]

alright done

[somber sage]

The BIOS may not preserve the contents of segment registers across a call to the protected mode interface. Therefore, the caller must reload any segment registers that are required to remain valid.

[somber sage]

why is apm so much cancer

[grave nimbus]

It's firmware, it's always cancer

[blissful pier]

also, invented by firmware devs (?)

[somber sage]

Does Hyper support chainloading with int19

[frank charm]

Hyper doesnt have chainloading at all atm

simply because i never needed it

although its a useful feature in general

[ornate locust]

for the record int19 doesn't (necessarily) chainload anything

[lusty blade]

chainloading into rom basic :^)

[raw dome]

chainloading into a triple fault

[somber sage]

Yes but it’s hooked by IPXE when chainloading…

That’s why I mentioned it

[torpid scaffold]

@frank charm any ideas on why i get this output while building hyper on mac os?
https://gist.github.com/voxaloo/21180ab35f7f775de37ee222e9c8b1ce

sorry for ping btw

[blissful pier]

also, what are the plans for the name/cmdline thing?

[frank charm]

Nothing yet, dont have the time to work on it yet

[frank charm]

Perhaps you dont have ld.lld installed or whatever its called

[frank charm]

https://github.com/UltraOS/Hyper/blob/707cf65b7aa864f58232012e4c409aeb85d00584/toolchain/toolchain_clang.cmake#L1

i thought it would blow up on error but maybe not

[torpid scaffold]

i didnt have lld installed for some reason, so i installed it manually and its fixed

[frank charm]

cool

[brazen sage]

Hello.

I was told this bootloader has a 32-bit higher half protocol?

[frank charm]

Yes

[frank charm]

Adding PXE support finally as im tired of IDER being terrible, its pretty cool to see it working on real hw

Surprised at the UEFI PXE implementations being way worse than the BIOS PXE implementations

at least on my hardware

most laptops ive tested dont support GET_FILE_SIZE via UEFI lol

anyway this + serial-over-lan should make real hardware CI really easy

[coral linden]

@frank charm give an image with ultra with hyper pxe

[frank charm]

do u want a bios or a uefi version

[coral linden]

bios

[frank charm]

you need these 3 in tftp root

and that kernel might try to spam a random io port i have hardcoded for one of the laptops SOL but should work anyway

[coral linden]

thank

[coral linden]

your nbp is huge 😭

per specification, the maximum size is 0x8400 bytes

but grub is much bigger than that, so i made it up to 64kb

[frank charm]

really lol

[coral linden]

(dont worry, im testing my rom)

[frank charm]

what can u even fit in 0x8400

[coral linden]

nothing

the specification that i found is super old

[frank charm]

is it supposed to like pxe chainload stage2 or smth

[coral linden]

probably

[frank charm]

ah

well it worked on all the stuff i tested on at least so hopefully nothing actually enforces that

[coral linden]

yeah

[frank charm]

lol why

[coral linden]

idk

[frank charm]

whats your graphical backend for qemu

[coral linden]

gtk

but it doesnt matter, its an issue with my rom most likely

since with ipxe it works

[frank charm]

ah

u mean with builtin pxe?

[coral linden]

yeah

[frank charm]

i wonder how your rom could possibly affect this

[coral linden]

im not very sure

the only thing i touch from the ivt is for setting up the pxe interrupt

and i use the bios pmm so i am not placing myself on some random place, and i actually get marked as reserved in the memory map

[frank charm]

yeah strange

[coral linden]

the ret is weird, it's 0x4f01

[frank charm]

yeah, its the exact same as the call number

did the bios handler get uninstalled or smth?

[coral linden]

nope

it gets inside the vga rom

[frank charm]

interesting

[coral linden]

i suppose pxe support has not been released yet

[frank charm]

no lol

its just code i have locally

[coral linden]

i investigated a bit harder, and the vga rom sets the correct values

enter handle_10:
   a=00004f01  b=00000000  c=0000017a  d=00000000 ds=0000 es=0796 ss=e66c
  si=00000000 di=00000004 bp=00000000 sp=000001f6 cs=0000 ip=7ff3  f=0202
VBE mode info request: 17a
returning! g c000 0
printing exit info:
enter handle_10:
   a=0000004f  b=00000000  c=0000017a  d=00000000 ds=0000 es=0796 ss=e66c
  si=00000000 di=00000004 bp=00000000 sp=000001f6 cs=0000 ip=7ff3  f=0202

[frank charm]

so they somehow never get propagated back or just get overwritten?

[coral linden]

same values are set with ipxe

idk

[frank charm]

[coral linden]

lmao

well dw

when you release the code i will look into it, now im intrigued

[frank charm]

lol sure

wheres your option rom code btw

[coral linden]

https://github.com/atiep/pxe-rom

theres only a single issue

diff --git a/asm/bios/headers.asm b/asm/bios/headers.asm
index 35a0620..cdc3657 100644
--- a/asm/bios/headers.asm
+++ b/asm/bios/headers.asm
@@ -22,6 +22,7 @@
 ; - init_entry
 ; - bev
 
+bits 16
 
 ; PCI Option ROM header
 option_rom_header:
@@ -29,7 +30,7 @@ db 0x55                             ; ROM Signature Byte 1
 db 0xAA                             ; ROM Signature Byte 2
 .init_size: db (image_end - image_start) / 512    ; Initialization size (init code + runtime code)
 jmp near init_entry                 ; Entry point for INIT function
-times 0x12 db 0                     ; Reserved
+times 0x13 db 0                     ; Reserved
 dw pci_data_structure               ; PCI Data Structure
 dw pnp_data_structure               ; PNP Data Structure
 times 0x20 - ($ - option_rom_header) db 0

[frank charm]

wait why is there so much code

[coral linden]

you'll have to apply this

maybe the nasm version was different when i was developing this in wsl

but it's skill issue tbf

[frank charm]

why do u need an initrd for it?

[coral linden]

where

[frank charm]

static int
initrd_read(const void *buf, size_t len, void *private_data)
{
    (void) private_data;
    memcpy(initrd_ptr, buf, len);
    initrd_ptr += len;
    initrd_len += len;
    return 0;
}

[coral linden]

oh dw, i hardcoded that for linux

the correct way to boot linux with pxe is to provide a script anyway

[frank charm]

ah

[coral linden]

diff --git a/pxe/boot/nbp.c b/pxe/boot/nbp.c
index 4fa5afa..fec154b 100644
--- a/pxe/boot/nbp.c
+++ b/pxe/boot/nbp.c
@@ -77,8 +77,8 @@ is_nbp(void *nbp, size_t nbp_len)
      * a NBP is 0x8400 bytes long, but in practice, some bootloaders (GRUB)
-      * are even bigger than that. So, let's just occupy a segment.
+      * are even bigger than that. So, let's just occupy two segments.
      */
-    if (nbp_len > 0x10000) {
-        printf("NBP is too big: %d bytes, maximum 65536\n", nbp_len);
+    if (nbp_len > 0x20000) {
+        printf("NBP is too big: %d bytes, maximum 128 KiB\n", nbp_len);
         return 0;
     }
 

[frank charm]

looks like the function that fails literally succeeded earlier because fetch_mode_info is called twice

once to fetch the mode, and a second time right before modeset

[coral linden]

yeah

[frank charm]

is this the second invocation tho

[coral linden]

yes

[frank charm]

lol yeah idk

[coral linden]

fun

[frank charm]

where do u even print these values?

[coral linden]

in the vga rom

[frank charm]

wheres the vga rom source lol

[coral linden]

diff --git a/vgasrc/vbe.c b/vgasrc/vbe.c
index 2ae0a98..fa744da 100644
--- a/vgasrc/vbe.c
+++ b/vgasrc/vbe.c
@@ -207,6 +207,8 @@ vbe_104f01(struct bregs *regs)
         SET_FARVAR(seg, info->linear_alpha_pos, a_pos);
     }
 
+    dprintf(1, "returning! g %x %x\n",(u32) get_global_seg(), (u32) get_global_offset());
+
     regs->ax = 0x004f;
 }
 
diff --git a/vgasrc/vgabios.c b/vgasrc/vgabios.c
index 44fb26c..9c20eae 100644
--- a/vgasrc/vgabios.c
+++ b/vgasrc/vgabios.c
@@ -1130,4 +1130,7 @@ handle_10(struct bregs *regs)
     case 0x4f: handle_104f(regs); break;
     default:   handle_10XX(regs); break;
     }
+
+    dprintf(1, "printing exit info:\n");
+    debug_enter(regs, DEBUG_VGA_10);
 }

in the seabios source tree

[frank charm]

ah

[coral linden]

git clone https://github.com/coreboot/seabios

then, -vga none -display VGA,romfile=seabios/out/vgabios.bin

although if you want the messages to appear, you'll have to go to Debugging -> Debug level and Special IO port debugging

and set up -chardev stdio,id=a -device isa-debugcon,chardev=a,iobase=0x402

[frank charm]

btw do u have a clanker that could debug this

[coral linden]

to be honest, i have no idea how to use claude

or any other sort of agent or however it is called

but i dont mind debugging this myself

[frank charm]

u just type claude in the terminal lol

and then tell him what to do

[coral linden]

it is probably an issue with my rom, if you say it works on real hardware

[frank charm]

ive tested on 2 laptops

not a huge coverage but

[coral linden]

my coverage isnt that great either too, my test subjects were grub and limine

[frank charm]

lol

how do u fixup e820 to mark yourself btw

[coral linden]

before the bios starts trying to boot from devices, there's an api called the pmm (post memory manager)

so option roms are supposed to use that during initialization if they want memory temporarily (during their init) or forever

the api is inaccessible after this

[frank charm]

ah

where do u use it?

[coral linden]

https://github.com/AtieP/pxe-rom/blob/main/asm/bios/pmm.asm

ignore the comment in line 22

it is not available starting from the moment it starts looking for boot devices

[frank charm]

interesting

[coral linden]

i use the pmm to get a place to copy the 32 bit code (which is the biggest part) to high memory

[frank charm]

makes sense

[coral linden]

and also to copy the 16 bit entry points to ram

[frank charm]

is there any docs for it

[coral linden]

because during initialization, the optiom rom area is ram

and after, it does chipset memes to make it read only

and the fun part is, its read only in tcg but rw in kvm

the ram that you get in the lower 1mb is in the 0xe000 segment so you dont have to worry about hyper or something else clashing

[coral linden]

yes

one sec

[frank charm]

Cool

[frank charm]

what args do I use for qemu? just virtio-net-pci,romfile=./romfile seems to not work

[coral linden]

-net none -netdev user,tftp=tftpdir,bootfile=hyper.pxe,id=netdev0 -device virtio-net,disable-legacy=on,netdev=netdev0,romfile=romfile,bootindex=1 -boot n

also, don't give too much ram, because otherwise seabios is forced to put the bar >4gb and i don't set up pae paging, so it will fail :p

[frank charm]

yeah looks like disable-legacy=on is mandatory for it to work

why is that

[coral linden]

the legacy interface uses a different device id

and i didn't want to deal with old virtio bullshit so i just disable it altogether lol

[frank charm]

lol

[frank charm]

@coral linden so far what I've dug up is that the registers that are pushed back after real mode call are somehow off by 2 registers

[coral linden]

interesting

[coral linden]

can you put a breakpoint at the exact spot and print the register state with ipxe and with my rom?

[frank charm]

lets see

CPU#0
EAX=0000004f EBX=00000000 ECX=0000047a EDX=00000000
ESI=00000000 EDI=00000004 EBP=00000000 ESP=00007934
EIP=00008015 EFL=00000046 [---Z-P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0796 00007960 0000ffff 00009300
CS =0000 00000000 0000ffff 00009a00
SS =0000 00000000 0000ffff 00009300
DS =0000 00000000 0000ffff 00009300
FS =0000 00000000 0000ffff 00009300
GS =0000 00000000 0000ffff 00009300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT=     00008120 0000002f
IDT=     00000000 000003ff

your rom

default rom:

CPU#0
EAX=0000004f EBX=00000000 ECX=0000017a EDX=00000000
ESI=00000000 EDI=00000004 EBP=00000000 ESP=0000792c
EIP=00008015 EFL=00000046 [---Z-P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0796 00007960 0000ffff 00009300
CS =0000 00000000 0000ffff 00009a00
SS =0000 00000000 0000ffff 00009300
DS =0000 00000000 0000ffff 00009300
FS =0000 00000000 0000ffff 00009300
GS =0000 00000000 0000ffff 00009300
LDT=0000 00000000 0000ffff 00008200
TR =0000 00000000 0000ffff 00008b00
GDT=     00008120 0000002f
IDT=     00000000 000003ff

this is hang-after-push

looks like the out_regs_ptr value gets corrupted maybe?

Although if i try to print out out_regs_ptr the values look the same

maybe u corrupt my instructions?

[coral linden]

could be possible

but very weird if only that specific bit is affected

and why would it fail in that specific point only

after querying all these video modes

[frank charm]

yeah you corrupt my code it looks like

with original pxe its this

[frank charm]

who knows lol

[coral linden]

jesus

[frank charm]

Hardware watchpoint 1: *(int*)0x7FFC

Old value = 262147846
New value = 1576710
0x00000000000e64a2 in ?? ()
(gdb) 

This is where it gets corrupted

[coral linden]

thats most likely the !pxe entry point

[frank charm]

is that in your code?

[coral linden]

yes

in entry.asm

[frank charm]

hm

[coral linden]

bruh this sucks so much lmao

i kinda wasted your time

how does that not even #ud

[coral linden]

i don't recall using and like that

wait nvm

that's for returning to rm

[coral linden]

what is the instruction directly above?

[frank charm]

i cant scroll up since im disassembling at that address

[coral linden]

i think that's intermode.asm:108

ok yeah i know what's going on there

esp points to somewhere above 1mb

and I'm loading a 16 bit ss

and applying the base and limits i have the extreme luck of neutrino hitting your code

lol

[frank charm]

   0x000e645e:    mov    %eax,%cr0
   0x000e6461:    pop    %ax
   0x000e6463:    mov    %bx,%cx
   0x000e6466:    add    $0x473,%cx
   0x000e646b:    add    %al,(%eax)
   0x000e646d:    push   $0x8
   0x000e646f:    push   %cx
   0x000e6471:    lretw
   0x000e6473:    mov    %eax,%ecx
   0x000e6475:    mov    $0x10,%ax
   0x000e6479:    mov    %eax,%ds
   0x000e647b:    mov    %eax,%es
   0x000e647d:    mov    %eax,%ss
   0x000e647f:    mov    %eax,%fs
   0x000e6481:    mov    %eax,%gs
   0x000e6483:    mov    %ecx,%eax
   0x000e6485:    mov    %edx,%esp
   0x000e6487:    cld
   0x000e6488:    call   *%eax
   0x000e648a:    mov    $0x20,%ax
   0x000e648e:    mov    %eax,%ds
   0x000e6490:    mov    %eax,%es
   0x000e6492:    mov    %eax,%fs
   0x000e6494:    mov    %eax,%gs
   0x000e6496:    mov    %eax,%ss
   0x000e6498:    mov    0x500(%ebx),%cx
   0x000e649f:    pushw  $0x18
=> 0x000e64a2:    pushw  $0x4a8
   0x000e64a6:    lretw
   0x000e64a8:    mov    %cr0,%eax
   0x000e64ab:    and    $0xfe,%al
   0x000e64ad:    mov    %eax,%cr0
   0x000e64b0:    push   %ecx
   0x000e64b1:    push   $0x89cb04b5
   0x000e64b6:    enter  $0xd88e,$0x8e
   0x000e64ba:    rorb   $0x2,-0x5e177120(%esi)
   0x000e64c1:    add    $0xa166d08e,%eax
   0x000e64c6:    add    $0x5,%al
   0x000e64c8:    mov    %ax,%sp

this is what im getting

[coral linden]

yes

[frank charm]

yep

[coral linden]

omg

[frank charm]

what are the odds of that corrupting these specific instructions lmfao

[coral linden]

no idea man

i think i am going to classify this as the worst bug ive ever had due to my code

[frank charm]

lol

Whats the fix

[coral linden]

in entry.asm I have a tmp_stack_begin and a tmp_stack_end

so after loading the new value of SS,

lea esp, [ebx + tmp_stack_end] should be enough

[frank charm]

ah

lemme know if it boots after the fix

[coral linden]

i mean

if you have it already compiled

it's a 1 line fix

put it before the push

in line 105 of intermode.asm

[frank charm]

yeah that fixed it

[coral linden]

jesus christ

[frank charm]

well that was fun 5 hours

[coral linden]

i am never ever going to write 16 to 32 bit and back code

again in my life

sorry for also wasting your time in this bs lmao

[frank charm]

Its fine lol, happens

[coral linden]

at least now i can update the readme and put hyper is supported too

[frank charm]

Real

[coral linden]

like