pmOS - microkernel OS for RISC-V, x86, and LoongArch | Operating System Development | Page 12

twilit talon Apr 26, 2026, 12:46 AM

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since every tty write is a vmexit

carmine nacelle Apr 26, 2026, 12:48 AM

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Nah, it's not that bad

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And I can just use UEFI

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Also, I don't normally use kvm anyway

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Also bruh

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Actually, no, it's about the same speed/ a bit slower

twilit talon Apr 26, 2026, 12:56 AM

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What did you change?

carmine nacelle Apr 26, 2026, 8:35 AM

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Idk, everything

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Mainly how memory objects are handled

carmine nacelle Apr 26, 2026, 3:16 PM

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Bruh, how do I suddenly have so many ideas for async receive?

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I think I can just do it with a ring buffer, between the kernel and userspace

carmine nacelle Apr 27, 2026, 11:39 AM

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Ok, I've kinda implemented it in kernel already, on RISC-V for now (to the point where the kernel compiles)

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And I think both the userspace api and the implemention is quite clean

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Also, this allows to share interrupts between drivers now...

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(After I get it to work on risc-v, I'll do it elsewhere, since the toolchain takes several hours to compile on my laptop)

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The interrupt signaling/IPC and EOI paths are now allocation free, and almost lock free (the locks are only taken to push stuff into the IPC queue)

carmine nacelle Apr 27, 2026, 3:53 PM

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Cool, this stuff basically almost fully worked the first time

twilit talon Apr 27, 2026, 3:53 PM

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9k/s trl

carmine nacelle Apr 27, 2026, 3:58 PM

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You need a riac-v leaderboard trl

carmine nacelle Apr 27, 2026, 4:14 PM

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carmine nacelle Cool, this stuff basically almost fully worked the first time

Yeah, this looks like a scheduler skill issue

toxic torrent Apr 27, 2026, 4:44 PM

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carmine nacelle You need a riac-v leaderboard <:trl:829316641191886888>

just tell people to use tcg on x86

carmine nacelle Apr 27, 2026, 4:44 PM

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But TCG is much faster

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Also, am I still the only uacpi user on loongarch?

toxic torrent Apr 27, 2026, 4:48 PM

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carmine nacelle But TCG is much faster

is it?

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as in the jit is more optimized?

carmine nacelle Apr 27, 2026, 4:50 PM

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Idk, I get a higher score in uACPI

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Like 10x

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I can't check because I don't have disk space on my laptop

plain jungle Apr 27, 2026, 5:24 PM

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qemu also uses tcg when running riscv

carmine nacelle Apr 27, 2026, 5:48 PM

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ok, what the fuck is going on with my kernel

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All CPUs have ID 0 galaxybrain

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Ok, after fixing this stupidity, this is fully working on risc-v...

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(at least ahci and ns16550 drivers worked with no issues...)

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Ok, I'm nuking risc-v build and building x86...

carmine nacelle Apr 28, 2026, 11:17 AM

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carmine nacelle Cool, this stuff basically almost fully worked the first time

This is my i686 build in qemu with TCG, for example

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And on RISC-V it was using SBI's timer, and on x86 it's using HPET

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Is this why I couldn't use copilot and had to debug my shit myself? trl

carmine nacelle Apr 28, 2026, 11:24 AM

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carmine nacelle Ok, after fixing this stupidity, this is fully working on risc-v...

Also, this stuff also works on x86 (i686, I'll just trust that amd64 isn't broken trl ) now, with the same arch-independent impl

carmine nacelle Apr 28, 2026, 11:38 AM

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carmine nacelle Is this why I couldn't use copilot and had to debug my shit myself? <:trl:829316...

What the fuck are those offsets?

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This is way pre-AI for it to confuse hex and decimal

carmine nacelle Apr 28, 2026, 12:24 PM

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This is fun

fringe grove Apr 28, 2026, 6:04 PM

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carmine nacelle This is fun

lmao

carmine nacelle Apr 28, 2026, 7:13 PM

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Just gonna leave this here, since everything else is broken

📎 OVMF.fd

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on loongarch

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Oh no, my kernel is broken for some reason on loongarch64

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and it panics before initializing the framebuffer

carmine nacelle Apr 28, 2026, 9:31 PM

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Ok, it was a dumb thing, that clanker found for me (but then started writing some insane code)

carmine nacelle Apr 29, 2026, 7:51 PM

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I think I found one of the bugs

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toxic torrent Apr 29, 2026, 7:52 PM

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what's the point of inline without static?

carmine nacelle Apr 29, 2026, 7:53 PM

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multiple definitions of the same function?

toxic torrent Apr 29, 2026, 7:53 PM

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yeah but like

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where is this used

carmine nacelle Apr 29, 2026, 7:53 PM

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headers

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why use static?

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this is C++

carmine nacelle Apr 29, 2026, 7:55 PM

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carmine nacelle

ok, qemu is hammering all cores, which is a good sign

carmine nacelle Apr 29, 2026, 7:56 PM

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carmine nacelle

(address should have been ulong instead of u32)

toxic torrent Apr 29, 2026, 8:01 PM

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carmine nacelle this is C++

static exists in c++

carmine nacelle Apr 29, 2026, 8:02 PM

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toxic torrent static exists in c++

But inline means a different thing in C++

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afaik

toxic torrent Apr 29, 2026, 8:03 PM

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oh

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sorry i'm not c++ pilled

carmine nacelle Apr 29, 2026, 8:04 PM

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https://en.cppreference.com/cpp/language/inline

inline

hexed acorn Apr 29, 2026, 8:50 PM

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inline in c++ means "it's fine to have multiple definitions of this, and the linker will merge them together" more or less

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(and having differing definitions is ub)

carmine nacelle Apr 29, 2026, 9:18 PM

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Does this stuff need to be aligned to something weird, or something like that???

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no...

carmine nacelle Apr 29, 2026, 9:57 PM

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Why...

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It's just writing 0xffffffffffffffff to the mailboxes

carmine nacelle Apr 29, 2026, 10:14 PM

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What the fuck

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I wanna kms (figuratively)

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The clanker was gaslighting me

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(1 << 31) is 0xffffffff80000000

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Because numbers are int in C(++)

twilit talon Apr 29, 2026, 10:17 PM

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carmine nacelle The clanker was gaslighting me

did it tell you how awesome and smart you are in the process

carmine nacelle Apr 29, 2026, 10:17 PM

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I can't believe it, this shit works

carmine nacelle Apr 29, 2026, 10:17 PM

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twilit talon did it tell you how awesome and smart you are in the process

No

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Tbh every time I use AI I wish I didn't

twilit talon Apr 29, 2026, 10:18 PM

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you're kinda using it wrong tbh

carmine nacelle Apr 29, 2026, 10:19 PM

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How am I supposed to use it?

twilit talon Apr 29, 2026, 10:19 PM

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like u expect too much of it

carmine nacelle Apr 29, 2026, 10:19 PM

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what should I expect?

twilit talon Apr 29, 2026, 10:20 PM

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did you just tell it to debug your code?

carmine nacelle Apr 29, 2026, 10:20 PM

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Kinda

twilit talon Apr 29, 2026, 10:21 PM

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which model?

carmine nacelle Apr 29, 2026, 10:21 PM

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gpt 5.4 mini

twilit talon Apr 29, 2026, 10:21 PM

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ok lol

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if u want it to do complex stuff like that u need the best one with a huge context window

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at the very least

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mini is complete shit for anything

carmine nacelle Apr 29, 2026, 10:22 PM

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It started hallucinating when it saw loongarch, then it tried to copy linux, and failed miserably at it, then it had found it once I basically did all of the debugging myself and pointed its nose at the problem

twilit talon Apr 29, 2026, 10:23 PM

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lol

carmine nacelle Apr 29, 2026, 10:25 PM

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Like sure, "you're giving it -1", then "0xffffffff comes from virtual addresses", then after I told it I was sure it was fine, it started reviewing my printf...

carmine nacelle Apr 30, 2026, 8:28 AM

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this is nice

modest thistle Apr 30, 2026, 8:33 AM

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carmine nacelle this is nice

https://tenor.com/view/c-programming-segmentation-fault-segfault-gif-2148153610786238200

Tenor

carmine nacelle Apr 30, 2026, 8:33 AM

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carmine nacelle this is nice

this is gdb btw

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though tbh I should probably update my gcc/binutils toolchain

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omg, this shit is getting somewhere

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But it's reading 0 out of mailbox 1 nooo

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why

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something in qemu is clearing the mailboxes for some reason.......

modest thistle Apr 30, 2026, 8:59 AM

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are you sure it's qemu?

carmine nacelle Apr 30, 2026, 8:59 AM

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what else would it be?

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maybe edk2, who knows

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I mean, it shouldn't be https://github.com/qemu/qemu/blob/master/hw/loongarch/boot.c#L38

GitHub

qemu/hw/loongarch/boot.c at master · qemu/qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are disabled. Please only use release tarballs from the QEMU website. - qemu/qemu

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But I've looked at it in gdb, and it looked like different code was running

carmine nacelle Apr 30, 2026, 9:18 AM

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Ok, this build is saner and had actually booted https://github.com/osdev0/edk2-ovmf-nightly

GitHub

GitHub - osdev0/edk2-ovmf-nightly: Nightly images of EDK2 OVMF firm...

Nightly images of EDK2 OVMF firmware for QEMU. Contribute to osdev0/edk2-ovmf-nightly development by creating an account on GitHub.

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But it still clears the mailboxes

carmine nacelle Apr 30, 2026, 9:51 AM

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Ok, I've no idea who and why is doing that, but it looks like (from qemu traces) it passes the mailbox 3 into $a1, and the interrupt vector into $a0 ?

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Unbelievable

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(tbh, I need an IPI to stop other CPUs on panic...)

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This is a very good sign?

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(I mean it gets stuck...)

carmine nacelle Apr 30, 2026, 10:34 AM

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trl

carmine nacelle Apr 30, 2026, 10:38 AM

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carmine nacelle <:trl:829316641191886888>

Cool, this stuff is basically fully working

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What I'm missing is multiple interrupt controllers support

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(because loongarch is fun, and you basically get a per-cpu lapic, where all of the vectors are shared, and then each cpu gets its own controller)

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All I have now is one

twilit talon Apr 30, 2026, 10:41 AM

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carmine nacelle Cool, this stuff is basically fully working

Whats it used for?

carmine nacelle Apr 30, 2026, 10:41 AM

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SMP on loongarch

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that particular screenshot is uACPI doing better on loongarch than on risc-v

twilit talon Apr 30, 2026, 10:41 AM

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No I mean the ged

carmine nacelle Apr 30, 2026, 10:41 AM

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Power button

twilit talon Apr 30, 2026, 10:41 AM

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Ah

carmine nacelle Apr 30, 2026, 10:42 AM

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Idk, I forgot I even implemented it, but somehow it didn't bitrot and survived a lot of changes and just worked

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But like I ported to loongarch because risc-v didn't have ged for some reason...

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and I didn't want to deal with arm

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(I still don't want to deal with arm)

carmine nacelle Apr 30, 2026, 1:46 PM

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Ok, I think I can proclaim SMP to be officially fully working on my loongarch64 port

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934/s trl

twilit talon Apr 30, 2026, 1:47 PM

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i should add C++ exceptions to uacpi

carmine nacelle Apr 30, 2026, 1:47 PM

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Huh?

twilit talon Apr 30, 2026, 1:47 PM

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( trl )

carmine nacelle Apr 30, 2026, 1:48 PM

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This server is written in C trl

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Don't ask why

carmine nacelle Apr 30, 2026, 2:45 PM

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Ok, missing PCI is very concerning

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It finds PNP0A03 but then nothing happends?

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Yep, just nothing happends

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@twilit talon ?

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ok, clanker fixed it

twilit talon Apr 30, 2026, 3:05 PM

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what was the issue

carmine nacelle Apr 30, 2026, 3:06 PM

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It wasn't finding root bridges

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Because loongarch doesn't publish them in south bridge

twilit talon Apr 30, 2026, 3:07 PM

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yeah find_devices_at doesnt return any error if nothing was found, u kind of know it wasnt if your callback wasnt invoked

carmine nacelle Apr 30, 2026, 3:08 PM

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Yeah, ofc

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I need to check if Managarm is wrong?

twilit talon Apr 30, 2026, 3:09 PM

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managarm doesnt even support loongarch

carmine nacelle Apr 30, 2026, 3:13 PM

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But this might be a general issue, if I took this code from them

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Or idk, idr why it'd write it like that

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(like where this came from)

twilit talon Apr 30, 2026, 3:16 PM

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whats the issue part?

twilit talon Apr 30, 2026, 3:17 PM

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carmine nacelle Because loongarch doesn't publish them in south bridge

u mean in acpi?

carmine nacelle Apr 30, 2026, 3:18 PM

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Yeah

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twilit talon Apr 30, 2026, 3:19 PM

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south bridge lol

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SB is system bus

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where the hell does it publish it then?

carmine nacelle Apr 30, 2026, 3:20 PM

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Just \\PCI0

twilit talon Apr 30, 2026, 3:20 PM

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so weird

carmine nacelle Apr 30, 2026, 3:20 PM

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Does this violate any spec?

carmine nacelle Apr 30, 2026, 3:21 PM

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carmine nacelle It finds PNP0A03 but then nothing happends?

Like the second screenshot is how it discovered it

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Yep, a bunch of other stuff is in _SB_, this is just \PCI0

twilit talon Apr 30, 2026, 3:22 PM

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carmine nacelle Does this violate any spec?

the spec is toilet paper

plain jungle Apr 30, 2026, 3:32 PM

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is this qemu or real hw?

carmine nacelle Apr 30, 2026, 3:33 PM

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Qemu

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Yeah, I probably stole this from Managarm https://github.com/managarm/managarm/blob/master/kernel/thor/system/pci/pci_acpi.cpp#L249

GitHub

managarm/kernel/thor/system/pci/pci_acpi.cpp at master · managarm/...

Pragmatic microkernel-based OS with fully asynchronous I/O - managarm/managarm

plain jungle Apr 30, 2026, 4:26 PM

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i think Managarm is correct here and qemu is wrong meme

carmine nacelle Apr 30, 2026, 4:26 PM

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Yeah, I should just stop supporting qemu mememan

plain jungle Apr 30, 2026, 4:29 PM

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you could patch qemu

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or send a patch upstream

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it's probably because loongarch is rather obscure and essentially unused outside of china

carmine nacelle Apr 30, 2026, 4:30 PM

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would they care if linux probably doesn't?

plain jungle Apr 30, 2026, 4:30 PM

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did you test if linux works

twilit talon Apr 30, 2026, 4:31 PM

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linux might just do root relative search

carmine nacelle Apr 30, 2026, 4:32 PM

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No galaxybrain

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I mean their AP init code is also broken, but there's no spec and I couldn't find where in the sources

plain jungle Apr 30, 2026, 4:39 PM

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yeah from a quick glance linux searches the entire root

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actually not sure

twilit talon Apr 30, 2026, 4:42 PM

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I think it just does for each from root and registers every device

carmine nacelle Apr 30, 2026, 4:43 PM

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but how can you do that if you need PCI for everything else?

plain jungle Apr 30, 2026, 4:43 PM

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it does but there are places where it checks for explicit names

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so stuff may not work correctly if it's not below _SB

twilit talon Apr 30, 2026, 4:43 PM

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Yeah maybe

carmine nacelle Apr 30, 2026, 7:10 PM

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Cool, my SATA driver seems to be doing better with the latest changes to it...

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But the MacBook is still trolling

twilit talon Apr 30, 2026, 7:11 PM

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carmine nacelle But the MacBook is still trolling

how

carmine nacelle Apr 30, 2026, 7:15 PM

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carmine nacelle Cool, my SATA driver seems to be doing better with the latest changes to it...

I suspect the IPC layout is different between C and Rust

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Yeah, it's saying 4096 physical and 512 logical for some reason, which makes no sense

twilit talon Apr 30, 2026, 7:17 PM

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how does that not make sense

carmine nacelle Apr 30, 2026, 7:17 PM

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thonk

twilit talon Apr 30, 2026, 7:18 PM

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physical is what is actually stored, logical is the smallest adressable unit

carmine nacelle Apr 30, 2026, 7:18 PM

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I'm dumb and that check is just wrong

twilit talon Apr 30, 2026, 7:18 PM

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LBA units are logical

carmine nacelle Apr 30, 2026, 7:18 PM

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Yeah

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I'll ask clanker to fix trl

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nah

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Cool, it didn't find ext4 partitions, because there were none on this MacBook

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But like it read the disk and everything

twilit talon Apr 30, 2026, 7:24 PM

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cool

carmine nacelle Apr 30, 2026, 7:24 PM

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(also, how do I still get fascinated seeing my kernel boot on actual PCs and like not shit itself)
(Except the smp init on x86 trl )

carmine nacelle Apr 30, 2026, 9:14 PM

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I think I'll finally fix it, then push to main

carmine nacelle May 1, 2026, 8:20 AM

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Wait, do I not need to send INIT to APs?

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Alternatively, following a power-up or RESET, since all APs are already in the “wait-for-SIPI state,” the BSP can broadcast just
a single SIPI IPI to the APs to wake them up and initialize them.

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SDM says this

carmine nacelle May 1, 2026, 11:10 AM

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Can you not do this??

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The SDM says it's read/write

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The TPR (shown in Figure 13-18) is cleared to 0 on reset. In 64-bit mode, software can read and write the TPR
using an alternate interface, MOV CR8 instruction. The new task-priority class is established when the MOV CR8
instruction completes execution. Software does not need to force serialization after loading the TPR using MOV
CR8.

carmine nacelle May 1, 2026, 11:29 AM

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Ok, my cool new timer function is trolling

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Oh no

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Well, now I know my double fault handler is broken trl

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oh no, now it just tripple faults...

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actually, it's gpfing in the gpf handler...

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what the fuck

carmine nacelle May 1, 2026, 12:48 PM

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fuck

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my smp init is still broken on the macbook nooo

twilit talon May 1, 2026, 12:56 PM

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Smp init... FAIL

carmine nacelle May 1, 2026, 12:56 PM

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I'm having a skill issue adding a submodule to my git directory

twilit talon May 1, 2026, 12:58 PM

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how

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Just git submodule add URL path

carmine nacelle May 1, 2026, 12:58 PM

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idfk

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it doesn't work

twilit talon May 1, 2026, 12:58 PM

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What does it say

carmine nacelle May 1, 2026, 12:59 PM

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nothing

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I think I've gotten it to add but idk

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the files are there

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I'm so done with this

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why does it not work

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how is it not finding it on my desktop while the same branch works perfectly on my laptop

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did flanterm change its file structure again???

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also, I think my keyboard is dying as well

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nooo

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All I want is to see kernel logs

hexed knot May 1, 2026, 1:04 PM

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carmine nacelle <:nooo:750466870993223750>

also wtf 27 argument function

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what is a struct anyway

carmine nacelle May 1, 2026, 1:05 PM

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hexed knot also wtf 27 argument function

that's flanterm for you

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(what are you using in your kernel?)

hexed knot May 1, 2026, 1:06 PM

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carmine nacelle (what are you using in your kernel?)

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(i just have a pl011 driver lol, pl011 is arm uart)

carmine nacelle May 1, 2026, 1:08 PM

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hexed knot (i just have a pl011 driver lol, pl011 is arm uart)

Unfortunately, that MacBook doesn't have UART, I'm afraid

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Anyway, it just freezes when I try starting the APs nooo

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https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86/cpus.cc?ref_type=heads#L54

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Also, how does this macbook have smep but not smap?

hexed knot May 1, 2026, 1:14 PM

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carmine nacelle Unfortunately, that MacBook doesn't have UART, I'm afraid

should have gotten a newer mac

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m1+ all have uart

carmine nacelle May 1, 2026, 1:15 PM

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i mean maybe this has uart as sell through the typical apple weirdness

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it has firewire and thinderbolt though ultrameme

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yep, this locks up after sending sipi

modest thistle May 1, 2026, 1:48 PM

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carmine nacelle Anyway, it just freezes when I try starting the APs <:nooo:750466870993223750>

epic face reveal XD

carmine nacelle May 1, 2026, 4:19 PM

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This is better

twilit talon May 1, 2026, 4:23 PM

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Did you fix the bug

carmine nacelle May 1, 2026, 4:23 PM

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no

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its gpfing on rdmsr for no reason

twilit talon May 1, 2026, 4:24 PM

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Me when no abortable instructions

carmine nacelle May 1, 2026, 4:24 PM

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actually, only in x2apic mode

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because I'm dumb and was reading from the wrong register...

carmine nacelle May 1, 2026, 4:27 PM

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carmine nacelle This is better

nevermind

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Linux does this https://elixir.bootlin.com/linux/v7.0.1/source/arch/x86/kernel/smpboot.c#L851 ...

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wait, what

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init init startup?

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could my error lvt just be broken or something?

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Maybe I just shouldn't do parallel startup?

carmine nacelle May 1, 2026, 5:31 PM

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bruh?

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wait a second...

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I'm so dumb

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Ofc it crashes in QEMU if I give 16GB of RAM

hexed knot May 1, 2026, 5:49 PM

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there is actually a funny way to do this without a silly lock carousel (i think youd still need to make an array of all of the capabilities though so it doesnt really let you remove the limit) but

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you can make a global array of N locks where N is a number that feels right

carmine nacelle May 1, 2026, 5:50 PM

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Oh no

hexed knot May 1, 2026, 5:50 PM

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and then an objects lock is some_hash(object_addr) % N

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and then you make a local N-entry bitmap which tells you which locks you need to lock

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im doing this kind of really funny global lock hashtable for another thing in my kernel

carmine nacelle May 1, 2026, 5:51 PM

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Even more deadlock potential, how nice

hexed knot May 1, 2026, 5:51 PM

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carmine nacelle Even more deadlock potential, how nice

nono this is actually deadlock-free

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because with a bitmap you always acquire it in one order

carmine nacelle May 1, 2026, 5:51 PM

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If everything uses this

hexed knot May 1, 2026, 5:51 PM

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well obviously you only acquire one set of locks at a time

carmine nacelle May 1, 2026, 5:52 PM

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It's not nice on numa as well

hexed knot May 1, 2026, 5:52 PM

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carmine nacelle It's not nice on numa as well

oh yeah true numa is a thing

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fuck numa

carmine nacelle May 1, 2026, 5:52 PM

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You can make this per nuna cluster though

hexed knot May 1, 2026, 5:52 PM

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mm true

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im just gonna target apple which is numa-free

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and by "numa-free" i mean they stripe cache lines between numa nodes in hardware so that you dont have to care

carmine nacelle May 1, 2026, 5:53 PM

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How do they do it on M* Max stuff?

hexed knot May 1, 2026, 5:53 PM

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carmine nacelle How do they do it on M* Max stuff?

i think only ultra has meaningful numa?

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but anyway yeah the cache lines are striped between numa nodes lol

carmine nacelle May 1, 2026, 5:54 PM

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Whichever one has 2 CPUs glued together

hexed knot May 1, 2026, 5:54 PM

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yeah

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im doing this stupid lock sharding meme for a different thing in my kernel though

hexed knot May 1, 2026, 5:55 PM

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hexed knot im doing this stupid lock sharding meme for a different thing in my kernel thoug...

my async ops have a pointer to the queue that they belong to, but they cant hold a refcount to it because reasons

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and this lets you acquire a lock by virtual address without actually requiring the target to be valid

carmine nacelle May 1, 2026, 5:57 PM

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I just use rcu

hexed knot May 1, 2026, 6:02 PM

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carmine nacelle I just use rcu

yeah but for that id have to actually implement rcu

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and its also not something with a nice quiescent period

carmine nacelle May 1, 2026, 6:02 PM

#

tbh my rcu needs some improvements as well

hexed knot May 1, 2026, 6:03 PM

#

also this is much funnier anyway

carmine nacelle May 1, 2026, 6:03 PM

#

lol yeah

carmine nacelle May 1, 2026, 6:23 PM

#

Lol do I finally implement 5 level paging on x86?

#

Now that I'm done with smp

carmine nacelle May 1, 2026, 9:36 PM

#

carmine nacelle Lol do I finally implement 5 level paging on x86?

It's almost done...

carmine nacelle May 1, 2026, 10:27 PM

#

Cool...

#

I think this works both with limine and hyper...

#

(also, I've improved my x86 paging code in general...)

#

though this is unfun...

#

I think it's trying to enable 5 level paging, when it shouldn't be?

carmine nacelle May 2, 2026, 1:55 PM

#

(pushed this stuff to main yesterday)

#

Also, I asked the clanker to check my paging code, and it had found a lot of embarrassing bugs in x86_64 paging stuff

#

And while I was in the mood for fixing paging, I've also finally implemented memory types (and their deduction from memory map for uACPI and whatnot) for physical memory mapping syscall

#

Which can maybe speed up the framebuffer?

#

though qemu kvm feels slower for some reason

#

the macbook does feel faster though

#

idk

carmine nacelle May 2, 2026, 4:09 PM

#

Oh no, I think my smp init code is now broken on i686 nooo

carmine nacelle May 2, 2026, 4:25 PM

#

This is very dumb

#

Like lol why boot when you can just idle

#

it could have crashed, it could have deadlocked, but no, it just had enough and decided to idle()

carmine nacelle May 2, 2026, 4:46 PM

#

(thankfully, this was an easy fix)

carmine nacelle May 2, 2026, 9:29 PM

#

this stuff is refusing to work nooo

carmine nacelle May 2, 2026, 9:58 PM

#

Oh

#

this is weird?

carmine nacelle May 2, 2026, 10:28 PM

#

this is fun

#

nooo

#

nooo

#

this is trolling though

#

I'm declaring this a skill issue of the buildbot trl

#

huh

#

actually, maybe it's a jinx's skill issue....

#

yeah, dry run doesn't expand the variables

#

(It would be great if I could choose which recipes to build, for each arch)

carmine nacelle May 2, 2026, 11:22 PM

#

carmine nacelle huh

@left dew ?

left dew May 2, 2026, 11:40 PM

#

?

#

i didn't make jinx

#

but you are right

#

i already brought it up to mint at some point

#

@vale hinge

carmine nacelle May 3, 2026, 7:34 AM

#

left dew i didn't make jinx

Oh, sorry

carmine nacelle May 3, 2026, 2:08 PM

#

Ok, I'm doing the filesystem

carmine nacelle May 3, 2026, 2:30 PM

#

I need to figure out the namecache though

carmine nacelle May 3, 2026, 3:07 PM

#

This is fun...

carmine nacelle May 3, 2026, 7:55 PM

#

Ok, I think I'll merge VFS and process/posix together

#

because I think this stuff is too closely coupled

carmine nacelle May 3, 2026, 10:58 PM

#

So I think I'll rewrite that from Rust to C++ before it's too late...

modest thistle May 3, 2026, 10:58 PM

#

XD

#

the service?

carmine nacelle May 3, 2026, 11:00 PM

#

Yes

carmine nacelle May 5, 2026, 7:17 PM

#

I'm writing VFS, and it's trolling me (and it crashed the kernel...)

#

Address misaligned...

carmine nacelle May 5, 2026, 9:20 PM

#

How am I having a skill issue writing circular list stuff??

hexed knot May 5, 2026, 9:27 PM

#

just dont use a circular list

carmine nacelle May 5, 2026, 9:27 PM

#

but they are nice

#

I'm trying to write swap function for the move constructor

hexed knot May 5, 2026, 9:27 PM

#

move constructor???

#

for what

carmine nacelle May 5, 2026, 9:27 PM

#

for the list

hexed knot May 5, 2026, 9:28 PM

#

like for the list itself? or for the list hook

carmine nacelle May 5, 2026, 9:28 PM

#

for the list

hexed knot May 5, 2026, 9:28 PM

#

for the list itself you are swapping one or two pointers idk its not hard

carmine nacelle May 5, 2026, 9:28 PM

#

like not the list nodes, but the list head

#

Like this looks good I think?

hexed knot May 5, 2026, 9:29 PM

#

uhhhh idk tbh

#

my circular list did not contain the list itself

carmine nacelle May 5, 2026, 9:29 PM

#

huh

#

Imma ask a clanker trl

hexed knot May 5, 2026, 9:30 PM

#

and in rust i cant really make them work properly anyway

hexed knot May 5, 2026, 9:30 PM

#

carmine nacelle Like this looks good I think?

also why swap

carmine nacelle May 5, 2026, 9:30 PM

#

hexed knot May 5, 2026, 9:30 PM

#

personally i would just SK_NO_COPY(CircularDoubleList); SK_NO_MOVE(CircularDoubleList); ngl but like its your code

hexed knot May 5, 2026, 9:31 PM

#

hexed knot personally i would just SK_NO_COPY(CircularDoubleList); SK_NO_MOVE(CircularDoubl...

#define SK_NO_COPY(T) T(const T&) = delete; T& operator=(const T&) = delete;
#define SK_NO_MOVE(T) T(T&&) = delete; T& operator=(const T&&) = delete;

carmine nacelle May 5, 2026, 9:31 PM

#

I have no copy, but I think move is nice

hexed knot May 5, 2026, 9:31 PM

#

ehh

carmine nacelle May 5, 2026, 9:31 PM

#

I mean I didn't have them, and it destroyed my code with the default constructors

hexed knot May 5, 2026, 9:31 PM

#

moving an intrusive ds like this CAN work butttt

hexed knot May 5, 2026, 9:34 PM

#

carmine nacelle I mean I didn't have them, and it destroyed my code with the default constructor...

wdym

carmine nacelle May 5, 2026, 9:35 PM

#

I didn't delete the copy constructor, and I was accidentally copying the list map.emplace

hexed knot May 5, 2026, 9:35 PM

#

ah

#

do you not have macros that delete all of the constructors lol

carmine nacelle May 5, 2026, 9:37 PM

#

no

hexed knot May 5, 2026, 10:26 PM

#

they are very handy

#

especially because you basically always want to delete copy constructors tbh

carmine nacelle May 6, 2026, 4:36 AM

#

Sometimes it's fine

#

Like for small structs

#

I mean most of the times

#

Like bit fields for paging trl

carmine nacelle May 6, 2026, 4:35 PM

#

I think I'm getting somewhere...

carmine nacelle May 7, 2026, 2:59 PM

#

Ok, since I have the filesystem, I think the next steps would be

Implementing timer rights
Making send() optionally block (and then implementing async send as well?)
Implementing pagers
Mlibc and other posix stuff till I get bash?

carmine nacelle May 8, 2026, 8:31 AM

#

So my plan for the timers is to have them be per-CPU, and then if the timer object is not on the right core, to IPI the other one to get its attention

carmine nacelle May 9, 2026, 10:24 AM

#

carmine nacelle So my plan for the timers is to have them be per-CPU, and then if the timer obje...

I've gotten this to work on x86

#

(Like timer rights)

#

I nedd to implement this on risc-v and loongarch64 as well, but I'll do that later (since I can't test it on my laptop)

#

And I also need to get rid of the old syscall

modest thistle May 9, 2026, 10:16 PM

#

btw @carmine nacelle does your pci daemon support pcie or just pci?

carmine nacelle May 9, 2026, 10:16 PM

#

both

#

I mean pci is kinda broken at the moment because of some bs in my early pci init code

carmine nacelle May 9, 2026, 10:32 PM

#

This is trolling

modest thistle May 9, 2026, 10:34 PM

#

lol

carmine nacelle May 9, 2026, 10:34 PM

#

(So, to continue the discussion in https://discord.com/channels/440442961147199490/1217009725711847465) I think, I'll allocate 2 pages of IO bitmap per process (when it requests it). Then, I'll map those into the per-CPU TSS, so they are naturally shared (with the shared memory)

modest thistle May 9, 2026, 10:34 PM

#

and how do you exchange them?

carmine nacelle May 9, 2026, 10:35 PM

#

exchange what?

modest thistle May 9, 2026, 10:35 PM

#

the pages

#

when you need per thread control

carmine nacelle May 9, 2026, 10:35 PM

#

huh?

modest thistle May 9, 2026, 10:36 PM

#

like, if they are shared for whole per cpu tss, then every process / thread will have them, no?

carmine nacelle May 9, 2026, 10:36 PM

#

No, the TSS will have 4 virtual page frames allocated for it (with the first one having the per-CPU data, the last one for the trailing byte). Then I will be swapping the middle two pages in the page tables, without changing the TSS itself

modest thistle May 9, 2026, 10:36 PM

#

oh the phys pages

carmine nacelle May 9, 2026, 10:37 PM

#

yeah...

modest thistle May 9, 2026, 10:37 PM

#

yeah that could work tbh

carmine nacelle May 10, 2026, 3:53 PM

#

Nevermind, fred is anoying, because of how my idle works...

#

Omg, my brain hurts, FRED is so inconsiderate

#

or maybe nevermind

twilit talon May 10, 2026, 4:02 PM

#

lol its pretty easy actually

carmine nacelle May 10, 2026, 4:03 PM

#

No

#

I've been using CS to know what was preempted by interrupts

#

I guess I should be abusing this

twilit talon May 10, 2026, 4:05 PM

#

whats sti (stb)

carmine nacelle May 10, 2026, 4:06 PM

#

sti instruction

twilit talon May 10, 2026, 4:06 PM

#

but sti enables interrupts

carmine nacelle May 10, 2026, 4:06 PM

#

basically, if interrupts were disabled, it means it's an unwarranted exception

#

I'm pretty sure it's interrupts

twilit talon May 10, 2026, 4:07 PM

#

ah yeah its the thing they use for NMIs

carmine nacelle May 10, 2026, 4:07 PM

#

isn't it only for smi though?

twilit talon May 10, 2026, 4:07 PM

#

wdym

#

what does it have to do with smi

carmine nacelle May 10, 2026, 4:08 PM

#

nmi blocking

#

I didn't know about stb

twilit talon May 10, 2026, 4:08 PM

#

no, i mean

carmine nacelle May 10, 2026, 4:08 PM

#

And can't find it

#

wait, no, then I can't use it

twilit talon May 10, 2026, 4:08 PM

#

anyway tldr its not useful for u

#

cant u just check rflags tho?

carmine nacelle May 10, 2026, 4:09 PM

#

No, I need to switch stack if the exception/interrupt is coming from my idle, and stay on the same stack if it's from the kernel

#

because I treat my kernel threads as userspace threads

#

but if I check rflags, it'll break my SMP init code

#

don't ask why

#

Idk how to do this

#

Like I see the vision that you're just supposed to push everything onto stack, do your stuff, and return, without having to care about all of the special cases

#

But idk, I can't wrap my head around it

#

If I don't give my idle a separate stack, it will be eating kernel's stack as well...

#

Though I had an easy solution for this in risc-v

#

But I'd like not to branch if it's possible...

#

"nested level"

heady garden May 10, 2026, 5:37 PM

#

carmine nacelle No, I need to switch stack if the exception/interrupt is coming from my idle, an...

why is your idle special? Can’t you just treat it like a kernel thread too

carmine nacelle May 10, 2026, 5:37 PM

#

Idk, I just feel depressed now

carmine nacelle May 10, 2026, 5:37 PM

#

heady garden why is your idle special? Can’t you just treat it like a kernel thread too

It has a separate stack

heady garden May 10, 2026, 5:38 PM

#

kernel threads don‘t?

carmine nacelle May 10, 2026, 5:38 PM

#

I have one stack per CPU and not per thread

#

So I switch to a special idle stack when I enter it

heady garden May 10, 2026, 5:40 PM

#

oh ok

carmine nacelle May 10, 2026, 5:43 PM

#

carmine nacelle Idk, I just feel depressed now

My x86_64 code is a very big mess and it just feels very bad

#

And then the one stack per CPU was a deliberate decision and kind off a differentiating factor, but I feel like I have to fight with hardware design of everything any time I change anything in the kernel...

#

Maybe it's time to get rid of it

#

(one stack per CPU)

#

But then the issue is that the whole kernel was written assuming it, so I'd probably need to redo a lot of locking stuff, implement proper mutex, etc.

#

And then it's gonna be implications on top of implications on top of implications

#

And like at the same time I already feel that I'm pouring too much time into something that's a hobby for me to be making any sort of "big" changes like this right now

twilit talon May 10, 2026, 5:50 PM

#

Yeah

#

One stack per cpu sucks

carmine nacelle May 10, 2026, 5:50 PM

#

carmine nacelle And then the one stack per CPU was a deliberate decision and kind off a differen...

Namely, I don't know how I'm gonna handle NMIs because of this stack switching nonsense

twilit talon May 10, 2026, 5:50 PM

#

But also I wouldn't bother with fred until I can get my hands on hardware that actually has it

#

Which won't happen any time soon

carmine nacelle May 10, 2026, 5:51 PM

#

(I mean I came up with the solution while writing this, which is a software interrupt if the kernel was preempted without installing a preemption point)

carmine nacelle May 10, 2026, 5:51 PM

#

twilit talon Which won't happen any time soon

Zen 6 should have it, you can just buy a new CPU when it comes out

#

According to some news I read today while researching this

#

(sorry for the rant to anyone reading this lol)

carmine nacelle May 10, 2026, 5:53 PM

#

carmine nacelle Namely, I don't know how I'm gonna handle NMIs because of this stack switching n...

This doesn't depend on whether I use FRED or not...

twilit talon May 10, 2026, 5:55 PM

#

carmine nacelle Zen 6 should have it, you can just buy a new CPU when it comes out

Yeah 2026 hardware has it

#

Including new Intel laptops

#

But I cant justify buying a 1k laptop for fred lmfao

carmine nacelle May 10, 2026, 5:56 PM

#

Yeah

carmine nacelle May 10, 2026, 5:57 PM

#

twilit talon But I cant justify buying a 1k laptop for fred lmfao

But you can probably upgrade your CPU and sell your old one

#

But yeah

carmine nacelle May 10, 2026, 5:58 PM

#

carmine nacelle My x86_64 code is a very big mess and it just feels very bad

Like wtf is this https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86_64/registers.hh?ref_type=heads#L109

twilit talon May 10, 2026, 5:58 PM

#

carmine nacelle But you can probably upgrade your CPU and sell your old one

You need a new motherboard for that

carmine nacelle May 10, 2026, 5:58 PM

#

twilit talon You need a new motherboard for that

Didn't you have 9950X?

twilit talon May 10, 2026, 5:59 PM

#

Yes

#

Is zen6 still am5

carmine nacelle May 10, 2026, 5:59 PM

#

Probably

earnest imp May 10, 2026, 5:59 PM

#

twilit talon Is zen6 still am5

IIRC yes

carmine nacelle May 10, 2026, 5:59 PM

#

They've been releasing new AM4 CPUs for like 8 or 9 years?

#

There's no new memory standard

#

So like they may pull Intel, but I'd expect them to release a couple more generations on AM5 before switching to a new platform

earnest imp May 10, 2026, 6:01 PM

#

I think zen7 would be on AM6
Arround then is when ddr6 is getting up?

carmine nacelle May 10, 2026, 6:31 PM

#

carmine nacelle Like wtf is this <https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86_64...

tbh this is salvageable for FRED

earnest imp May 10, 2026, 6:36 PM

#

carmine nacelle tbh this is salvageable for FRED

the frames are near identical to what the IDT stuff pushes so yes

#

they just add a bit extra

soft turret May 10, 2026, 6:45 PM

#

twilit talon Is zen6 still am5

AMD has confirmed it will use AM5

carmine nacelle May 10, 2026, 7:41 PM

#

earnest imp the frames are near identical to what the IDT stuff pushes so yes

Btw, do syscall/sysenter use the normal return address with FRED, or is it still some %r11 or whatever weirdness?

earnest imp May 10, 2026, 7:44 PM

#

carmine nacelle Btw, do syscall/sysenter use the normal return address with FRED, or is it still...

they do not fucke with rcx and r11

carmine nacelle May 10, 2026, 7:44 PM

#

And it looks at the return type and returns from rcx/r11 instead?

carmine nacelle May 10, 2026, 9:40 PM

#

Idk if I'm dumb, but I can't get it to detect FRED in qemu??

#

I've given it the +fred flag

earnest imp May 10, 2026, 9:40 PM

#

carmine nacelle Idk if I'm dumb, but I can't get it to detect FRED in qemu??

do you have the vibe coded qemu patches?

carmine nacelle May 10, 2026, 9:40 PM

#

no

earnest imp May 10, 2026, 9:40 PM

#

otherwise QEMU TCG will not support it

#

and you need intel SIMICS

#

PSP1G_pspTrollar

#

#resources message

twilit talon May 10, 2026, 9:46 PM

#

carmine nacelle Idk if I'm dumb, but I can't get it to detect FRED in qemu??

Maybe because its not supported by qemu lmao

carmine nacelle May 10, 2026, 9:49 PM

#

Simic's trolling

carmine nacelle May 10, 2026, 10:21 PM

#

I need to figure out the serial io stuff...

#

Is this my OS doing this?

earnest imp May 10, 2026, 10:22 PM

#

carmine nacelle Is this my OS doing this?

nope thats the firmware

carmine nacelle May 10, 2026, 10:23 PM

#

but there's no screen or serial or anything

#

idk what I'm doing

earnest imp May 10, 2026, 10:23 PM

#

what command did you use to launch it?

#

it should open a display

carmine nacelle May 10, 2026, 10:24 PM

#

$cpu_comp_class = "x86-experimental-fred
$iso_image="\\\\wsl.localhost\\Ubuntu\\home\\misha\\pmos\\build-x86_64\\pmos.iso"
run-script ./targets/qsp-x86/qsp-dvd-boot.simics
run

#

thonk

earnest imp May 10, 2026, 10:49 PM

#

carmine nacelle ``` $cpu_comp_class = "x86-experimental-fred $iso_image="\\\\wsl.localhost\\Ubun...

I wonder how angry SIMICS is at the WSL path

#

Also that stuff was only tested in Linux™

#

Iirc @marble steeple got it working on windows

twilit talon May 10, 2026, 10:55 PM

#

carmine nacelle ``` $cpu_comp_class = "x86-experimental-fred $iso_image="\\\\wsl.localhost\\Ubun...

lol never seen anyone use a wsl patth

twilit talon May 10, 2026, 10:55 PM

#

earnest imp Iirc <@189759562910400512> got it working on windows

nah it worked perfectly for me on windows

carmine nacelle May 10, 2026, 10:55 PM

#

What packages did you install?

twilit talon May 10, 2026, 10:55 PM

#

all of them

carmine nacelle May 10, 2026, 11:00 PM

#

what else did you do?

#

idk

twilit talon May 10, 2026, 11:00 PM

#

idr tbh

#

its like

#

extremely fucking counterintuitive

carmine nacelle May 10, 2026, 11:00 PM

#

There's no gui

twilit talon May 10, 2026, 11:00 PM

#

there is gui lol

#

what are u doing

#

but yeah simics is the worst least intuitive piece of software i have seen maybe ever

carmine nacelle May 10, 2026, 11:00 PM

#

nothing happens?

inland temple May 10, 2026, 11:01 PM

#

carmine nacelle <:thonk:575445129863888896>

When I'm in a wearing out my SSD as quickly as possible competition but my opponent is mishakov

twilit talon May 10, 2026, 11:01 PM

#

lol

earnest imp May 10, 2026, 11:02 PM

#

twilit talon but yeah simics is the worst least intuitive piece of software i have seen maybe...

carmine nacelle May 10, 2026, 11:42 PM

#

earnest imp otherwise QEMU TCG will not support it

where do I get them?

#

simics is also refusing to work on my pc

earnest imp May 10, 2026, 11:42 PM

#

Let me find them

#

If discord on my pc won’t crash

#

#1431140025805832343 message
@carmine nacelle

carmine nacelle May 11, 2026, 12:07 AM

#

earnest imp https://discord.com/channels/440442961147199490/1431140025805832343/149218899339...

This seems to work?

earnest imp May 11, 2026, 12:08 AM

#

I can toss you my ISO if you wana test to make sure it built right etc

carmine nacelle May 11, 2026, 12:08 AM

#

It has detected fred

#

I haven't implemented it yet

earnest imp May 11, 2026, 12:08 AM

#

Yeah but the patches are still well dubious

carmine nacelle May 11, 2026, 12:08 AM

#

(my kernel I mean)

earnest imp May 11, 2026, 12:08 AM

#

So testing would be good trl

carmine nacelle May 11, 2026, 12:09 AM

#

simics is trolling

earnest imp May 11, 2026, 12:09 AM

#

well

#

it is SIMICS

carmine nacelle May 11, 2026, 12:09 AM

#

idk what I'm doing wrong, but there's no gui

earnest imp May 11, 2026, 12:10 AM

#

its simics simicsing all over the place

#

thats it

carmine nacelle May 11, 2026, 1:28 AM

#

This is cool

#

(I think I've gotten it because it tried to iretq

#

but also it's 3:30 am so I'm going to sleep

#

(I've also implemented guard pages for the stacks...)

#

Also, somehow it seems to get to userspace without crashing with 8KB stacks...

earnest imp May 11, 2026, 1:34 AM

#

carmine nacelle (I think I've gotten it because it tried to iretq

how did you even manage it to run iretq 😭

marble steeple May 11, 2026, 4:21 AM

#

earnest imp Iirc <@189759562910400512> got it working on windows

yeah I did, I asked gpt how to do it, but I also installed the full package and it's package manager thing and let it just install everything it wanted, didn't try to point it at existing stuff on my system like python

toxic torrent May 11, 2026, 7:31 AM

#

carmine nacelle "nested level"

why the offset comments

#

can't you just use offsetof with inline asm ethancat2

carmine nacelle May 11, 2026, 8:15 AM

#

earnest imp how did you even manage it to run iretq 😭

Because I haven't implemented it

carmine nacelle May 11, 2026, 8:16 AM

#

toxic torrent can't you just use offsetof with inline asm <:ethancat2:1390106531516907571>

You haven't seen my assembly...

carmine nacelle May 11, 2026, 10:11 AM

#

I've gotten to the timer interrupt??

carmine nacelle May 11, 2026, 10:45 AM

#

Trolling continues

#

I really need an unwinder

twilit talon May 11, 2026, 11:04 AM

#

homeless stack traces are funny

twilit talon May 11, 2026, 11:04 AM

#

carmine nacelle I really need an unwinder

yes

#

well u need a symbolicator since it seems u do unwind it

carmine nacelle May 11, 2026, 11:05 AM

#

but it's a simple rip/rbp thing

twilit talon May 11, 2026, 11:05 AM

#

depends if thats enough for u

#

if u explictly enable frame pointers its fine

carmine nacelle May 11, 2026, 11:05 AM

#

not the proper dwarf2 one which unwinds through nullptr %rips

carmine nacelle May 11, 2026, 11:05 AM

#

carmine nacelle Trolling continues

Like here

twilit talon May 11, 2026, 11:06 AM

#

dwarf cant unwind through a nullptr, at least not the eh_frame unwind

#

i had to add special code for that

#

carmine nacelle May 11, 2026, 11:20 AM

#

Bruh, I think GPT 5.5 has managed to get SIMICS to work?

#

Though there's still no GUI

#

Also, I think HPET wasn't the firmware...

#

bruh it has managed to get GUI working as well...

carmine nacelle May 11, 2026, 12:42 PM

#

gdtdoesnotwork

#

But this now gets deep into userspace

carmine nacelle May 11, 2026, 1:18 PM

#

Ok, this insanity fully works in vibecoded qemu meme

#

Time to fix HPET...

#

carmine nacelle May 11, 2026, 1:19 PM

#

carmine nacelle Ok, this insanity fully works in vibecoded qemu <:meme:575445094589661215>

Like there's no difference between kvm and tcg with fred

earnest imp May 11, 2026, 1:22 PM

#

btw i can test in simics later if you need to make sure its not just the vibe coded qemu

carmine nacelle May 11, 2026, 1:22 PM

#

I've managed to get it working, but it doesn't like my HPET code

#

so I can't really test fred

carmine nacelle May 11, 2026, 1:23 PM

#

carmine nacelle Also, I think HPET wasn't the firmware...

.

earnest imp May 11, 2026, 1:24 PM

#

ah yeahhhh

#

this is the only BS the firmware gives

carmine nacelle May 11, 2026, 1:50 PM

#

This is fun

#

Yeah, it seems to be fully working

#

And LASS !!

#

Now I just need shadow stacks trl

carmine nacelle May 11, 2026, 1:55 PM

#

earnest imp btw i can test in simics later if you need to make sure its not just the vibe co...

If you wanna try it lol

📎 pmos.iso

earnest imp May 11, 2026, 1:57 PM

#

carmine nacelle If you wanna try it lol

carmine nacelle May 11, 2026, 1:57 PM

#

Do you have serial I/O?

#

I mean if it has fred, it should have used it or failed

earnest imp May 11, 2026, 1:58 PM

#

yes but your line control is off trl

carmine nacelle May 11, 2026, 1:58 PM

#

Can you scroll up to right after the kernel loads to see if it's using it?

earnest imp May 11, 2026, 1:58 PM

#

carmine nacelle May 11, 2026, 1:59 PM

#

earnest imp yes but your line control is off <:trl:1477775551505633320>

This is userspace ns16550

#

Cool

carmine nacelle May 11, 2026, 2:39 PM

#

I think I'm gonna finish getting rid of the old usersapce timers API, implement proper IO ports rights, and push this to main

#

After which I think I'll leave this stuff for a bit, since I have exams in a few weeks

twilit talon May 11, 2026, 2:40 PM

#

Btw when are you actually going to port shit

carmine nacelle May 11, 2026, 2:41 PM

#

twilit talon Btw when are you actually going to port shit

After I do proper mutex and port mlibc

twilit talon May 11, 2026, 2:41 PM

#

Can you run something like bash now?

carmine nacelle May 11, 2026, 2:41 PM

#

No

#

I mean I probably have enough kernel/usersapce stuff to do it if I implement enough stuff in libc

#

Also, I'd need an input subsystem for bash

#

(though I have ns16550)

twilit talon May 11, 2026, 2:44 PM

#

I need to implement proper serial console with interrupts as well so I can use my kernel remotely over amt

#

But thats for later

carmine nacelle May 11, 2026, 2:45 PM

#

carmine nacelle (though I have ns16550)

My driver is fully interrupt driven for both input and output

twilit talon May 11, 2026, 2:45 PM

#

U need interrupts for output?

carmine nacelle May 11, 2026, 2:45 PM

#

You don't "need" them

modest thistle May 11, 2026, 2:45 PM

#

twilit talon U need interrupts for output?

for some serial yes

carmine nacelle May 11, 2026, 2:46 PM

#

carmine nacelle You don't "need" them

If you poll it

#

Because serial is very slow

twilit talon May 11, 2026, 2:46 PM

#

Ah does it generate an irq when the output is empty or smth

carmine nacelle May 11, 2026, 2:46 PM

#

twilit talon Ah does it generate an irq when the output is empty or smth

Yes

twilit talon May 11, 2026, 2:46 PM

#

Is it worth it

#

Like 115k baud is how may chars a second

carmine nacelle May 11, 2026, 2:46 PM

#

carmine nacelle Yes

What I do is I fill the queue, and wait for the interrupt to write it

modest thistle May 11, 2026, 2:46 PM

#

twilit talon Like 115k baud is how may chars a second

you can get up to easily 1M+ baud

twilit talon May 11, 2026, 2:47 PM

#

The isa com x86 has cant go that high lol

carmine nacelle May 11, 2026, 2:47 PM

#

twilit talon Like 115k baud is how may chars a second

I think my kernel writes a 9600, and it takes like 5 seconds to boot just because of how slow it is

twilit talon May 11, 2026, 2:47 PM

#

Lmao why

carmine nacelle May 11, 2026, 2:47 PM

#

On physical hardware

#

(my old test PC)

twilit talon May 11, 2026, 2:47 PM

#

Can it not handle 115k

carmine nacelle May 11, 2026, 2:47 PM

#

It can

#

I mean I had issues with it where the characters weren't arriving

#

But it think it was a Linux skill issue on the other side

#

Also serial has busy bits or however it's called, which lets you block the other side from sending if your buffer is full

#

But I haven't bothered with it

twilit talon May 11, 2026, 2:50 PM

#

Looks like 115k baud is approximately 1 char each microsecond

#

So not really worth interrupts

carmine nacelle May 11, 2026, 2:54 PM

#

Maybe 10 microseconds?

#

But yeah, it probably doesn't matter for logs

twilit talon May 11, 2026, 2:56 PM

#

carmine nacelle Maybe 10 microseconds?

Ah wait

#

Yes

hexed acorn May 11, 2026, 3:05 PM

#

carmine nacelle Also serial has busy bits or however it's called, which lets you block the other...

CTS/RTS

carmine nacelle May 11, 2026, 3:10 PM

#

carmine nacelle After I do proper mutex and port mlibc

Maybe I need to find contributors

carmine nacelle May 11, 2026, 9:10 PM

#

Clanker had found gold in my PCI interrupt routing code...

#

And the funny thing is that everything dies if I fix it

#

Cool, new hardware discovered...

carmine nacelle May 12, 2026, 8:58 AM

#

Bruh, I've looked at netbs and it's very easy

#

I basically already have something that's almost like that

hexed knot May 12, 2026, 8:58 AM

#

yes

carmine nacelle May 12, 2026, 8:58 AM

#

Just park/unpark and they fix the race with unpark setting a flag...

#

And userspace handles spurious wakeups

#

I don't really get the pointer hints though

#

But it looks like they don't even use it?

plain jungle May 12, 2026, 9:07 AM

#

what are the netbsd park APIs?

carmine nacelle May 12, 2026, 9:07 AM

#

lwp_park/lwp_unpark

plain jungle May 12, 2026, 9:07 AM

#

smh just do block_on(future)

carmine nacelle May 12, 2026, 9:07 AM

#

I think it comes from Sun

carmine nacelle May 12, 2026, 9:07 AM

#

plain jungle smh just do `block_on(future)`

Huh

plain jungle May 12, 2026, 9:12 AM

#

Managarm's kernel-internal primitive is also park / unpark

#

but this is only used to implement block_on(future) (also kernel-internal)

#

and block_on(future) is used to implement everything else (including futexes)

carmine nacelle May 12, 2026, 9:13 AM

#

So it's basically the same thing?

carmine nacelle May 12, 2026, 7:15 PM

#

Bruh, I'm having a giant skill issue with i8042 again...

#

Which is this

#

The i8042 is 2 ACPI devices...

#

#

but this is so anoying to deal with...

#

Do I just special case it like managarm?

#

Wait a second, ia64 has i8042??

carmine nacelle May 12, 2026, 7:56 PM

#

Also, this is next level trolling from the kernel ("-ENOMEM")

carmine nacelle May 14, 2026, 2:08 PM

#

I now have proper i8042 interrupts discovered from ACPI, maybe I can do shell trl

twilit talon May 14, 2026, 2:39 PM

#

I wonder why its under SF8

#

What device even is at address 8?

carmine nacelle May 14, 2026, 2:39 PM

#

I've no idea

#

That's what ACPI gave me for the keyboard PNP id

#

It's at LPC_ in simics

twilit talon May 14, 2026, 2:45 PM

#

Lpc makes sense

carmine nacelle May 14, 2026, 2:45 PM

#

what's lpc?

twilit talon May 14, 2026, 2:45 PM

#

I mean sf8 probably does as well but idk what that object is

twilit talon May 14, 2026, 2:46 PM

#

carmine nacelle what's lpc?

Like the chipset object probably

#

00:00

carmine nacelle May 14, 2026, 2:46 PM

#

huh https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf

twilit talon May 14, 2026, 2:47 PM

#

Yeah

carmine nacelle May 14, 2026, 3:42 PM

#

My keyboard driver is also fully working again

#

The more I use my timers API the more I like it

carmine nacelle May 14, 2026, 5:31 PM

#

Do I finally port mlibc?

plain jungle May 14, 2026, 5:50 PM

#

do it meme

carmine nacelle May 14, 2026, 5:51 PM

#

My kernel doesn't meet the first requirement ultrameme

twilit talon May 14, 2026, 5:53 PM

#

carmine nacelle My kernel doesn't meet the first requirement <:ultrameme:729026898666979428>

Why the hell is that even a prereq

kindred venture May 14, 2026, 5:54 PM

#

sys_libc_log

carmine nacelle May 14, 2026, 6:05 PM

#

I mean I kinda have all of this already...
https://github.com/managarm/mlibc/blob/master/sysdeps/demo/sysdeps.cpp

GitHub

mlibc/sysdeps/demo/sysdeps.cpp at master · managarm/mlibc

Portable C standard library. Contribute to managarm/mlibc development by creating an account on GitHub.

#

But I need to figure out how to bring the stuff I do in userspace in

twilit talon May 14, 2026, 6:15 PM

#

kindred venture sys_libc_log

Can't u stub it?

kindred venture May 14, 2026, 6:16 PM

#

I mean yeah but if you have to stub a required sysdep I don't think it really counts as porting mlibc

carmine nacelle May 14, 2026, 6:18 PM

#

carmine nacelle My kernel doesn't meet the first requirement <:ultrameme:729026898666979428>

I have it in userspace

#

But it's a bunch of IPC

#

Cool...

#

Can limine switch to a different git thing again? trl

#

At least Github's ssh thing still works

#

Where do I put my kernel API?

#

Like should I split my libc into two libraries, or just reimplement everything from scratch in mlibc?

plain jungle May 14, 2026, 6:37 PM

#

up to you

#

one thing that probably doesn't work terribly well is linking against a shared library

#

unless it's a VDSO

#

because ld.so will need some calls before it has processed all DSOs

carmine nacelle May 14, 2026, 6:38 PM

#

I mean static library should be fine?

plain jungle May 14, 2026, 6:38 PM

#

yeah

#

a static lib (compiled as PIC) should work

carmine nacelle May 14, 2026, 6:39 PM

#

I also need to decide what to do with my signal thread

#

Because at the moment, my libc initializes itself, and then does pthread_create for the thread that actually calls main()

#

wait a second, is frigg header only?

dense carbon May 14, 2026, 6:53 PM

#

carmine nacelle wait a second, is frigg header only?

the wonders of c++

carmine nacelle May 14, 2026, 6:54 PM

#

Because then it's very easy to integrate

carmine nacelle May 15, 2026, 8:31 AM

#

Btw @twilit talon is it normal that Hyper doesn't enable NX when booted with BIOS by default?

twilit talon May 15, 2026, 8:34 AM

#

Yeah it doesn't use any memory protection at all

#

It doesn't enable WP in cr0 either

#

Enabled nx under UEFI is probably leftovers from edk2

carmine nacelle May 15, 2026, 8:42 AM

#

Ok

#

I'm asking because limine seems to be enabling everything

#

(but like it's ok that it doesn't, my kernel was just triple faulting yesterday, and I found out that that was because I was assuming this to be done by the bootloader)

twilit talon May 15, 2026, 8:46 AM

#

ah

#

i remap my kernel myself anyway

#

so these mappings arent really relevant for me

carmine nacelle May 15, 2026, 8:46 AM

#

I do too, but I forgot to enable NX in EFER

twilit talon May 15, 2026, 8:47 AM

#

skill issue trl

carmine nacelle May 15, 2026, 8:48 AM

#

carmine nacelle I do too, but I forgot to enable NX in EFER

And as usual, only in the x86_64 port trl

#

Like idk why, but even though it's what I normally run, it has the biggest skill issue with everything

twilit talon May 15, 2026, 8:49 AM

#

how do u even not have common paths for such features for both modes ☠️

carmine nacelle May 15, 2026, 8:50 AM

#

That path is common, loading cr3 is not

#

My paging code is separate

twilit talon May 15, 2026, 8:50 AM

#

ah

#

u dont support PAE?

carmine nacelle May 15, 2026, 8:50 AM

#

I do

twilit talon May 15, 2026, 8:50 AM

#

that has NX too tho

carmine nacelle May 15, 2026, 8:51 AM

#

Yep

#

So I do NX detection for both arches

twilit talon May 15, 2026, 8:51 AM

#

ah i see u just duplicated the cpu stuff also

carmine nacelle May 15, 2026, 8:51 AM

#

twilit talon ah i see u just duplicated the cpu stuff also

Most of it is also common

twilit talon May 15, 2026, 8:51 AM

#

the way i do it is a common setup_cpu() detects all features and sets a bit in supported_pt_mask

carmine nacelle May 15, 2026, 8:51 AM

#

But stuff like gdt/IDT is different

twilit talon May 15, 2026, 8:51 AM

#

nx is set unconditionally in pt_prot but cleared if its not supported by the mask

carmine nacelle May 15, 2026, 8:52 AM

#

twilit talon nx is set unconditionally in pt_prot but cleared if its not supported by the mas...

I check it in ultra_main

twilit talon May 15, 2026, 8:52 AM

#

☠️

carmine nacelle May 15, 2026, 8:52 AM

#

And now that I think of it, I don't enable it when booted with limine???

twilit talon May 15, 2026, 8:52 AM

#

u support both protocols at the same time right

twilit talon May 15, 2026, 8:52 AM

#

carmine nacelle And now that I think of it, I don't enable it when booted with limine???

limine (the bootloader) probably always enables it, but idk if protocol gurantees it

carmine nacelle May 15, 2026, 8:53 AM

#

twilit talon u support both protocols at the same time right

Yeah

#

In the same binary

twilit talon May 15, 2026, 8:53 AM

#

i might do that as well but too lazy

#

limine doesnt have a kernel binary memory type etc

#

its gonna be a bit annoying

carmine nacelle May 15, 2026, 8:53 AM

#

It has kernel and modules

#

Why do you need it?

twilit talon May 15, 2026, 8:53 AM

#

i exclude kernel from the direct map

#

so i need the precise address for it

carmine nacelle May 15, 2026, 8:54 AM

#

Limine also does

twilit talon May 15, 2026, 8:54 AM

#

yeah but im making my own direct map lol

carmine nacelle May 15, 2026, 8:54 AM

#

It has a feature that gives you the kernel address

carmine nacelle May 15, 2026, 8:54 AM

#

twilit talon yeah but im making my own direct map lol

I don't use HHDM

#

(on x86)

twilit talon May 15, 2026, 8:55 AM

#

carmine nacelle It has a feature that gives you the kernel address

yeah but i will need to make a synthetic e820 entry and carve it out somewhere, which may be in the middle of kernel-and-modules or even crossing multiple of them

carmine nacelle May 15, 2026, 8:55 AM

#

I've been planning to add it as an optimization though

twilit talon May 15, 2026, 8:55 AM

#

it is a good optimization

#

because less TLB usage due to huge pages

#

global pages

carmine nacelle May 15, 2026, 8:56 AM

#

twilit talon yeah but i will need to make a synthetic e820 entry and carve it out somewhere, ...

I do create a synthetic e820 that's common for 2 protocols for my pmm init though

carmine nacelle May 15, 2026, 8:56 AM

#

twilit talon it is a good optimization

Yeah, I know

twilit talon May 15, 2026, 8:56 AM

#

yeah id have to do that too

carmine nacelle May 15, 2026, 8:56 AM

#

It's not that difficult

twilit talon May 15, 2026, 8:57 AM

#

yes

carmine nacelle May 15, 2026, 8:58 AM

#

But like my kernel doesn't need a separate kernel memmap entry, as long as it's in some kind of used region

#

Though multiboot2 is annoying because it doesn't do that

twilit talon May 15, 2026, 8:59 AM

#

i wouldnt use multiboot2 without a huge prekernel

carmine nacelle May 15, 2026, 9:00 AM

#

I wanted to implement it with an asm trampoline

#

I mean I had a prekernel before, but I've gotten rid of it...

carmine nacelle May 15, 2026, 9:07 AM

#

carmine nacelle I wanted to implement it with an asm trampoline

Like it shouldn't be too bad, I just need to filter e820, and initialize paging

carmine nacelle May 15, 2026, 5:05 PM

#

I need to figure out how to include a static library with a static library...

carmine nacelle May 15, 2026, 10:54 PM

#

I think I'm losing motivation again

carmine nacelle May 16, 2026, 2:37 PM

#

Do I call for contributors? thonk

earnest imp May 16, 2026, 2:39 PM

#

carmine nacelle Do I call for contributors? <:thonk:575445129863888896>

ive still got a few even without the tag heh

#

even more general helpers for stuff

#

You should throw on the tag though if you want

#

But you will still get them without it

carmine nacelle May 16, 2026, 2:41 PM

#

But idk I'm worried about it since atm basically all of the code is mine (except the external libraries, etc.)

earnest imp May 16, 2026, 2:41 PM

#

Just do code reviews and add a clang format etc

#

If you don’t like the code point stuff out etc

carmine nacelle May 16, 2026, 2:41 PM

#

I do have clang format

#

But it's broken I think

earnest imp May 16, 2026, 2:42 PM

#

earnest imp If you don’t like the code point stuff out etc

And talk to people when they are working on things etc

#

It helps a lot

carmine nacelle May 18, 2026, 11:36 AM

#

I've updated the post

carmine nacelle May 22, 2026, 7:13 PM

#

Ok, I said I was gonna leave pmOS for some time, but I'm suddenly in a mood to add mb2 support trl

carmine nacelle May 22, 2026, 9:37 PM

#

How am I having this skill issue?

check_exception old: 0xffffffff new 0xd
748: v=0d e=03f8 i=0 cpl=0 IP=0018:000000000000000f pc=000000000000000f SP=0020:0000000000064f5c env->regs[R_EAX]=00000000e85250d6
EAX=e85250d6 EBX=0000234a ECX=00071000 EDX=000003f0
ESI=00000004 EDI=00000001 EBP=00000000 ESP=00064f5c
EIP=0000000f EFL=00000003 [------C] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
CS =0018 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
DS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
FS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
GS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
LDT=0000 00000000 00000000 00008200 DPL=0 LDT
TR =0038 00000000 00000000 00008900 DPL=0 TSS32-avl
GDT= 1fe75000 00000047
IDT= 00000000 000003ff
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=000000d6 CCD=ffffff32 CCO=SUBB
EFER=0000000000000000
check_exception old: 0xd new 0xd
749: v=08 e=0000 i=0 cpl=0 IP=0018:000000000000000f pc=000000000000000f SP=0020:0000000000064f5c env->regs[R_EAX]=00000000e85250d6
EAX=e85250d6 EBX=0000234a ECX=00071000 EDX=000003f0
ESI=00000004 EDI=00000001 EBP=00000000 ESP=00064f5c
EIP=0000000f EFL=00000003 [------C] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
CS =0018 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
DS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
FS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
GS =0020 00000000 ffffffff 00cf9300 DPL=0 DS [-WA]
LDT=0000 00000000 00000000 00008200 DPL=0 LDT
TR =0038 00000000 00000000 00008900 DPL=0 TSS32-avl
GDT= 1fe75000 00000047
IDT= 00000000 000003ff
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=000000d6 CCD=ffffff32 CCO=SUBB
EFER=0000000000000000
check_exception old: 0x8 new 0xd

#

This is protected mode without paging

twilit talon May 22, 2026, 9:38 PM

#

Looks like you're executing code at 0

carmine nacelle May 22, 2026, 9:39 PM

#

Yes, because I have no IDT

#

Or no...

twilit talon May 22, 2026, 9:39 PM

#

No, thats the first exception

carmine nacelle May 22, 2026, 9:39 PM

#

yeah

#

I'm dumb

#

Or no

#

Nevermind

#

time for bochs coolmeme

#

gdb refuses to work in protected mode for some reason

#

Nevermind, I fixed it lol

carmine nacelle May 23, 2026, 3:08 PM

#

Why am I having such a hard time writing x86 assembly?

#

Having so little registers is unbearable

carmine nacelle May 25, 2026, 5:25 PM

#

Ok, this stuff is almost working

#

I've gotten to the higher half, but it seems like my (self trl ) elf loader is broken

#

Or paging

carmine nacelle May 25, 2026, 7:46 PM

#

Cool, this casual assembly insanity has gotten to higher half/C++

#

(Also, I've learned that gnu toolchain exposes symbols, which let you get pheaders for yourself without requesting it from the bootloader)

toxic torrent May 25, 2026, 9:19 PM

#

what were you doing?

carmine nacelle May 25, 2026, 9:19 PM

#

Adding multiboot2 support trl

#

Which ended up being 1k+ lines of assembly just to get to C++?

plain jungle May 26, 2026, 8:17 AM

#

wtf

carmine nacelle May 26, 2026, 8:18 AM

#

I'm not doing a prekernel

twilit talon May 26, 2026, 8:18 AM

#

sounds totally maintainable

carmine nacelle May 26, 2026, 8:18 AM

#

Also, the plan it to support all three protocols with the same binary

#

(I mean, it's kinda working, but Limine and Ultra have stopped booting, likely after my linker scritp changes)

plain jungle May 26, 2026, 8:26 AM

#

even w/o a prekernel, it shouldn't take 1k lines to get from asm to C

#

also, from this progress thread I get the impression that you often have a ton of regressions halfmemeleft . maybe you should invest a bit of time to set up better automated testing

carmine nacelle May 26, 2026, 8:27 AM

#

I mean it's a bit of an exaggeration probably, I have a bunch of comments and empty lines

#

But there are like 1.2k lines of text

#

Actually, no, I was right

carmine nacelle May 26, 2026, 8:36 AM

#

plain jungle also, from this progress thread I get the impression that you often have _a ton_...

Jinx is broken KEKW

plain jungle May 26, 2026, 8:37 AM

#

carmine nacelle Actually, no, I was right

what does this code do? i'd probably just let it set up some initial pts and jump to C

carmine nacelle May 26, 2026, 8:39 AM

#

https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86/multiboot2.S?ref_type=heads
https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86_64/multiboot2.S?ref_type=heads

carmine nacelle May 26, 2026, 8:39 AM

#

plain jungle what does this code do? i'd probably just let it set up some initial pts and jum...

It does that

modest thistle May 26, 2026, 8:40 AM

#

oh it's 2 500 lines file

#

for 2 arches

#

lol

twilit talon May 26, 2026, 8:40 AM

#

Id KMS if I had to write so much at&t assembly

carmine nacelle May 26, 2026, 8:41 AM

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modest thistle for 2 arches

No, it's generic + x86_64 specific

modest thistle May 26, 2026, 8:41 AM

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oh

carmine nacelle May 26, 2026, 8:41 AM

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I don't have i686 trampoline yet

plain jungle May 26, 2026, 8:41 AM

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well

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it does a lot more than that

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why not just embed enough space for a few PTs in the BSS

carmine nacelle May 26, 2026, 8:41 AM

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It also prints to screen

plain jungle May 26, 2026, 8:41 AM

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yeah which is completely unnecessary

twilit talon May 26, 2026, 8:42 AM

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you know what its missing? a builtin kernel shell

carmine nacelle May 26, 2026, 8:42 AM

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plain jungle why not just embed enough space for a few PTs in the BSS

Because it's not a prekernel, and I want to reclain that memory

twilit talon May 26, 2026, 8:42 AM

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do u have something like a free-after-init section?

carmine nacelle May 26, 2026, 8:42 AM

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No...

twilit talon May 26, 2026, 8:42 AM

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😭

carmine nacelle May 26, 2026, 8:42 AM

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I was thinking about it, but didn't bother with it yet

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It feels like it's more trouble than what it's worth

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(In terms of memory consumption)

plain jungle May 26, 2026, 8:43 AM

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i think it's mostly a waste of effort but yeah a free-after-init (or just re-using the PTs) is probably way simpler than this

twilit talon May 26, 2026, 8:44 AM

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too late now

carmine nacelle May 26, 2026, 8:55 AM

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twilit talon you know what its missing? a builtin kernel shell

I can larp it once I have bash trl

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(Also, I had bzt's shell thing in my kernel in the past 💀)

kindred venture May 26, 2026, 9:51 AM

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carmine nacelle <https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86/multiboot2.S?ref_ty...

this seems incredibly overcomplicated and hard to maintain

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you don't need output, dynamic allocation, any of that

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just allocate a few page tables in .bss, map the lower 4G using 2M mappings, map the kernel image using __executable_start and _end without respecting phdr permissions, and call C

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that's like 100 instructions at most

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the C code can figure out the rest

carmine nacelle May 27, 2026, 3:05 PM

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carmine nacelle (I mean, it's kinda working, but Limine and Ultra have stopped booting, likely a...

Cool, it was broken because of a "broken" linker script, and now those two work, and multiboot can also remap itself

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The obnoxious part now is filtering the memory map...

carmine nacelle May 28, 2026, 1:48 PM

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limine is trolling trl

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#

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While the same exact binary does boot with limine protocol

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I need to check grub...

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Lol

carmine nacelle May 30, 2026, 8:06 AM

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Lol limine's trolling again trl

📎 message.txt

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Meanwhile multiboot2:

Multiboot e820:
0 - A0000 type 1
100000 - 800000 type 1
800000 - 808000 type 4
808000 - 80B000 type 1
80B000 - 80C000 type 4
80C000 - 811000 type 1
811000 - 900000 type 4
900000 - 1EAEC000 type 1
1EAEC000 - 1EC00000 type 2
1EC00000 - 1F8ED000 type 1
1F8ED000 - 1F9ED000 type 2
1F9ED000 - 1FAED000 type 2
1FAED000 - 1FB6D000 type 2
1FB6D000 - 1FB7F000 type 3
1FB7F000 - 1FBFF000 type 4
1FBFF000 - 1FEC1000 type 1
1FEC1000 - 1FEC5000 type 2
1FEC5000 - 1FEC7000 type 4
1FEC7000 - 1FEF4000 type 1
1FEF4000 - 1FF78000 type 2
1FF78000 - 20000000 type 4
E0000000 - F0000000 type 2
FD00000000 - 10000000000 type 2

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Or maybe not?

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bruh

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Wtf am I supposed to do with LIMINE_MEMMAP_RESERVED_MAPPED ???

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It's passed as reserved by multiboot2 and RAM by limine protocol...

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This is trolling

carmine nacelle May 30, 2026, 9:12 AM

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Omg, why did they have to make multiboot2 so obnoxious?

kindred venture May 30, 2026, 9:19 AM

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yeah I have no idea why they decided to pass a copy instead of a pointer

toxic torrent May 30, 2026, 10:30 AM

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carmine nacelle Omg, why did they have to make multiboot2 so obnoxious?

what

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do they mean RSDT?

kindred venture May 30, 2026, 10:45 AM

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nope

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they include copies of the rsdp

carmine nacelle May 30, 2026, 11:03 AM

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How am I supposed to use the palettes with flanterm??

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My kernel fully boots with mb2 now, but I'm missing the framebuffer

toxic torrent May 30, 2026, 11:14 AM

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carmine nacelle How am I supposed to use the palettes with flanterm??

you don't

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you pretty much need to assert that framebuffer_type == 1

carmine nacelle May 30, 2026, 12:09 PM

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bruh, even if you request modules to be page aligned, grub can allocate multiboot2 struct wherever it wants

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Why...

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and so it will intersect

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Now I'm only missing bash to larp a kernel shell trl

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(Also, how do I send it as a video?)

scarlet salmon May 30, 2026, 12:36 PM

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carmine nacelle (Also, how do I send it as a video?)

You likely need to convert it to a mp4.

carmine nacelle May 31, 2026, 8:49 PM

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Cool, my i686 binary can also boot with multiboot2 now

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trl

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Who said you can't use limine for ia32 trl

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A small change bruh

carmine nacelle Jun 20, 2026, 9:22 PM

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I'm done with exams and stuff so maybe not dead os trl

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But I kinda don't have motivation for this either

little smelt Jun 20, 2026, 9:33 PM

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carmine nacelle But I kinda don't have motivation for this either

https://tenor.com/view/school-system-school-dropshipping-dropship-school-system-failed-us-gif-12838652971328253285

Tenor

toxic torrent Jun 20, 2026, 10:10 PM

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W

modest thistle Jun 20, 2026, 10:33 PM

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little smelt https://tenor.com/view/school-system-school-dropshipping-dropship-school-system-...

i mean, pretty accurate

carmine nacelle Jun 26, 2026, 3:29 PM

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I think the time has come to implement lwp_park and unpark

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Which means I have to implement thread/task rights

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And I also need to move processes and signals to the kernel since what I have now is a mess

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Or I don't even know what to do at this point

carmine nacelle Jun 26, 2026, 3:42 PM

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carmine nacelle And I also need to move processes and signals to the kernel since what I have no...

Though managarm also has thread groups?

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I'm so lost

plain jungle Jun 26, 2026, 7:02 PM

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Managarm implements pthreads/processes/thread groups in userspace

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the kernel has a concept of threads but no concept of processes

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the kernel also doesn't have a concept of signals

carmine nacelle Jun 26, 2026, 7:17 PM

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My kernel is the same

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Now do you deliver signals?

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I've briefly looked at the code but didn't really get to it

carmine nacelle Jun 26, 2026, 7:19 PM

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plain jungle Managarm implements pthreads/processes/thread groups in userspace

The problem I had with this is tracking processes, and making sure there are no threads left hanging after the process dies, and so on...

plain jungle Jun 26, 2026, 7:20 PM

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signals are delivered by interrupting a thread, reading its register state, writing its register state to its stack, loading a new register state and resuming the thread

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that's done by posix-subsystem

carmine nacelle Jun 26, 2026, 7:21 PM

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I have a signal thread for it... But doesn't it make all of the signal stuff IPC and thus very slow?

#pmOS - microkernel OS for RISC-V, x86, and LoongArch