pmOS - microkernel OS for RISC-V, x86, and LoongArch | Operating System Development | Page 8

carmine nacelle Mar 13, 2025, 12:32 AM

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This is fishy

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Limine does .align 4?

vale hinge Mar 13, 2025, 12:38 AM

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carmine nacelle Limine does .align 4?

what's fishy?

carmine nacelle Mar 13, 2025, 12:39 AM

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PALEN-1:12?

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I don't know if the address has to be shifted by 12, or be aligned to 4K

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Like limine does this if I'm not missing something

vale hinge Mar 13, 2025, 12:41 AM

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.align 4 in non-x86 means shift by 4

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so that's probably wrong

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as per spec

carmine nacelle Mar 13, 2025, 12:43 AM

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yeah

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But I can't find what linux does

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Maybe the spec is wrong galaxybrain

vale hinge Mar 13, 2025, 12:44 AM

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probably the function happens to end up on a 4k boundary so that's why it works fine anyways?

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either that or the hardware doesn't actually care about alignment

carmine nacelle Mar 13, 2025, 12:46 AM

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Linux seems to align to 64k

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I guess I'll just align it to 4K then

carmine nacelle Mar 13, 2025, 12:47 AM

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vale hinge either that or the hardware doesn't actually care about alignment

Did someone try it on physical hardware?

vale hinge Mar 13, 2025, 12:47 AM

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yeah

carmine nacelle Mar 13, 2025, 12:48 AM

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and it didn't care..?

vale hinge Mar 13, 2025, 12:48 AM

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you can send a PR fixing this

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or send me a patch (made with git format-patch)

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if you want attribution for fixing this

carmine nacelle Mar 13, 2025, 12:50 AM

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Ok, I'll look into it tomorrow...

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(It's almost 2AM where I live)

vale hinge Mar 13, 2025, 1:39 AM

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i'll just do it myself then

vale hazel Mar 13, 2025, 10:56 AM

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carmine nacelle Ok, I'll look into it tomorrow...

boo

carmine nacelle Mar 13, 2025, 11:14 AM

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💀

carmine nacelle Mar 13, 2025, 11:48 AM

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mul.d is a vector instruction?

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carmine nacelle Mar 13, 2025, 12:03 PM

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clang is seriously trolling me...

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Ok, I need gdb...

carmine nacelle Mar 13, 2025, 12:59 PM

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carmine nacelle Ok, I need gdb...

(it was absolutely useless...)

carmine nacelle Mar 13, 2025, 1:33 PM

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Fun, apparently it does have 5 level paging...

carmine nacelle Mar 13, 2025, 7:38 PM

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Ok, I'm not detecting the skill issue, but the paging is refusing to work

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This is a bit strange...

twilit talon Mar 13, 2025, 7:45 PM

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loongarch?

carmine nacelle Mar 13, 2025, 7:46 PM

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Yeah

twilit talon Mar 13, 2025, 7:46 PM

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cool

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how hard is it

carmine nacelle Mar 13, 2025, 7:46 PM

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The kernel just pagefaults

carmine nacelle Mar 13, 2025, 7:46 PM

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twilit talon how hard is it

Basically like RISC-V but more Chinese

twilit talon Mar 13, 2025, 7:46 PM

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lol

carmine nacelle Mar 13, 2025, 7:47 PM

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The documentation is a bit difficult to comprehend at times

carmine nacelle Mar 13, 2025, 7:48 PM

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carmine nacelle The kernel just pagefaults

And I don't even have printf...

carmine nacelle Mar 13, 2025, 7:53 PM

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twilit talon how hard is it

But they have some interesting ideas I guess

twilit talon Mar 13, 2025, 7:54 PM

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which

carmine nacelle Mar 13, 2025, 7:57 PM

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Software refilled tlb/split paging/direct mapping regions for example

twilit talon Mar 13, 2025, 7:57 PM

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how does limine work if its software refilled

carmine nacelle Mar 13, 2025, 7:58 PM

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It has a special exception for TLB misses, where CPU drops into mode without paging and you refill it

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But like they give you special instructions which do it for you basically

twilit talon Mar 13, 2025, 7:59 PM

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interesting, is it really cheaper for chips to do this instead of handling it internally

carmine nacelle Mar 13, 2025, 7:59 PM

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But you can configure how many bits is each level and so on

carmine nacelle Mar 13, 2025, 8:00 PM

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twilit talon interesting, is it really cheaper for chips to do this instead of handling it in...

Idk, I guess

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But like otherwise it's normal page tables

twilit talon Mar 13, 2025, 8:02 PM

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so u can implement hhdm in software technically?

carmine nacelle Mar 13, 2025, 8:04 PM

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Yeah

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Limine does that

twilit talon Mar 13, 2025, 8:06 PM

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cool

carmine nacelle Mar 13, 2025, 9:17 PM

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Wait a second

carmine nacelle Mar 13, 2025, 10:16 PM

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Bruh I crashed gdb

carmine nacelle Mar 13, 2025, 11:34 PM

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I don't get it

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Page invalid exception for fetch operation: This exception is triggered when the virtual address of the
fetch operation finds a match in the TLB with V=0.

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How am I messing up my page tables like that

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It has to be something absolutely dumb...

carmine nacelle Mar 14, 2025, 12:10 AM

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Ok, my 3rd level has shit in it

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thonk

carmine nacelle Mar 14, 2025, 12:29 AM

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I think my tlb configuration is off

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lddir $t0, $t0, 2 is trolling me

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wait, what the fuck, it's loading the page from 0x80001ff1

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So I'm not supposed to be setting any bits in page directories?

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Ok, this is really fucked

carmine nacelle Mar 14, 2025, 1:20 AM

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I don't get how it works, but I think I have paging...

carmine nacelle Mar 14, 2025, 11:57 AM

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This is interesting...

carmine nacelle Mar 14, 2025, 2:20 PM

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I think I've gotten paging to work...

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Now I need to figure out the direct map thing...

carmine nacelle Mar 14, 2025, 4:01 PM

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So, DMW0 is choosing to troll me...

carmine nacelle Mar 14, 2025, 4:18 PM

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Good documentation

The hit is determined as follows: the highest 8 bits of the virtual address ([63:60] bits) are equal to the VSEG field in the configuration window register, and the current privilege level is available.

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Someone is high

exception: 72 (Address error for Memory access)
(documentation doesn't mention anything about it, or I'm blind )

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It was this...

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ADdress error Exception (ADE): when the program has a functional error that causes the address of the instruction fetch or memory access instruction to appear illegal (such as the instruction fetch address
is not aligned on 4-byte boundaries, and the privileged address space is accessed), ADdress error Exception for Fetching instructions (ADEF) or ADdress error Exception for Memory access instructions 13 (ADEM) will be triggered.

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Cool

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Why does it get triggered though meirl

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Like this address should be ok 90000000ebf8a000

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I don't get it, why does it not work

For example, if PALEN is equal to 48 and DMWO is set to 0x9000000000000011, virtual address space
0x9000000000000000-0x9000FFFFFFFFFFFF will be directly mapped to physical address space 0x0-
0xFFFFFFFFFFFF at the PLV0 privilege level, the memory access type of which is consistent and
cacheable.

carmine nacelle Mar 14, 2025, 4:47 PM

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carmine nacelle Like this address should be ok `90000000ebf8a000`

I do asm volatile("csrwr %0, %1" ::"r"(0x9000000000000011), "i"(CSR_DMW0)); and this faults

carmine nacelle Mar 14, 2025, 5:04 PM

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Linux docs are contradicting themselves...

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Unless...

left dew Mar 14, 2025, 5:08 PM

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linux docs are linux docs

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good resource until they aren't

carmine nacelle Mar 14, 2025, 5:12 PM

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I think it time to read qemu source

carmine nacelle Mar 14, 2025, 5:49 PM

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thonk https://elixir.bootlin.com/qemu/v9.2.2/source/target/loongarch/cpu_helper.c#L217

cpu_helper.c - target/loongarch/cpu_helper.c - Qemu ...

Elixir Cross Referencer - source code of Qemu v9.2.2: target/loongarch/cpu_helper.c

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QEMU bug?

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@toxic torrent can you test an image?

toxic torrent Mar 14, 2025, 5:50 PM

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sure

carmine nacelle Mar 14, 2025, 5:52 PM

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carmine nacelle <:thonk:575445129863888896> https://elixir.bootlin.com/qemu/v9.2.2/source/target...

There are 3 possibilities, with the same probability of being right:

Documentation is wrong
QEMU is dumb
I'm insane

toxic torrent Mar 14, 2025, 5:52 PM

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always assume qemu is broken

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though with loongarch this is sometimes actually the case

carmine nacelle Mar 14, 2025, 5:54 PM

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carmine nacelle <:thonk:575445129863888896> https://elixir.bootlin.com/qemu/v9.2.2/source/target...

No, this is clearly a bug

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Does Linux not use DMWs?

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It's checking bits [63:48] to be canonical, which is like not what you're supposed to do according to manual

carmine nacelle Mar 14, 2025, 5:55 PM

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toxic torrent sure

📎 pmOS.iso

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It should show something and probably panic

toxic torrent Mar 14, 2025, 5:56 PM

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gimme a command

carmine nacelle Mar 14, 2025, 5:57 PM

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carmine nacelle <:thonk:575445129863888896> https://elixir.bootlin.com/qemu/v9.2.2/source/target...

Wait, I can't read

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Not a bug

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Nevermind

carmine nacelle Mar 14, 2025, 5:57 PM

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toxic torrent gimme a command

?

toxic torrent Mar 14, 2025, 5:57 PM

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qemu command

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-cdrom doesn't work

carmine nacelle Mar 14, 2025, 5:57 PM

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I use this qemu-system-loongarch64 -m 2G -cdrom limine/pmOS.iso -smp 4 -serial stdio -bios ovmf-riscv64/RELEASELOONGARCH64_QEMU_EFI.fd -device ramfb -d int

toxic torrent Mar 14, 2025, 5:58 PM

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can i has ovmf pls

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https://tenor.com/view/ts-pmo-ngl-gif-11910576611451267173

Tenor

carmine nacelle Mar 14, 2025, 6:07 PM

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I'm on a train with bad internet and discord is taking an eternity to upload files

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📎 RELEASELOONGARCH64_QEMU_EFI.fd

carmine nacelle Mar 14, 2025, 6:09 PM

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carmine nacelle <:thonk:575445129863888896> https://elixir.bootlin.com/qemu/v9.2.2/source/target...

I think this is the only line that could be throwing this exception

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I have an idea

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(well, not an idea, but a plan)

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galaxybrain

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What the fuck

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I think C++ is trolling me, except I've looked at assembly and it looked fine

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So the top bit somehow does not get set??

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ffffffff8000c0b8: 05 44 80 03      ori    $a1, $zero, 17
ffffffff8000c0bc: a5 00 24 03      lu52i.d    $a1, $a1, -1792
;     asm volatile("csrwr %0, %1" ::"r"(0x9000000000000011), "i"(CSR_DMW0));
ffffffff8000c0c0: 25 00 06 04      csrwr    $a1, 384

To me this is setting 0x180 to 0x9000000000000011

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I am definetely setting it

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The CSRWR instruction writes the old value of the general register rd to the specified CSR and updates the old value of the specified CSR to the general register rd
Oh, fun, very intuitive instruction name

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bootlin elixir broken as usual

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(I need to redo my exception handlers...)

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Fun, almost missed my stop...

carmine nacelle Mar 14, 2025, 8:52 PM

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(I need to redo my exception handlers...)

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(anyway)

carmine nacelle Mar 14, 2025, 11:30 PM

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I have something

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My assembly is just UB

toxic torrent Mar 14, 2025, 11:37 PM

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guh

carmine nacelle Mar 14, 2025, 11:40 PM

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and it just pagefaults

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but I maybe have flanterm

carmine nacelle Mar 14, 2025, 11:40 PM

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carmine nacelle and it just pagefaults

during pmm init

carmine nacelle Mar 15, 2025, 12:06 AM

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I've tried to fix framebuffer and it only made it worse, so I think I'm gonna proceed to getting the rest working and pretend it isn't broken

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This just pagefaults for no reason...

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I think the kernel really doesn't want to be running on this arch...

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(should have ported to ARM first)

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I have a theory on why this is happening...

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Yeah ```
loongarch_cpu_do_interrupt enter: pc ffffffff8000af2c ERA 000000000d4cca60 TLBRERA ffffffff8000af1d exception: 2 (Page invalid exception for store)
loongarch_cpu_do_interrupt: PC 00000000ebe18000 ERA ffffffff8000af2d cause 2(refill)
, ESTAT 0000000000000000 EXCFG 0000000000000800 BADVA ffff800000218820BADI 0000000029812085 SYS_NUM 12288 cpu 0 asid 00000000000a0000
helper_ertn: TLBRERA ffffffff8000af2c
loongarch_cpu_do_interrupt enter: pc ffffffff8000af1c ERA 000000000d4cca60 TLBRERA ffffffff8000af2c exception: 2 (Page invalid exception for store)
loongarch_cpu_do_interrupt: PC 0000000000000000 ERA ffffffff8000af1c cause 2
, ESTAT 0000000000020000 EXCFG 0000000000000800 BADVA ffff800000219020BADI 00000000298080c5 SYS_NUM 3215360 cpu 0 asid 00000000000a0000

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(The key here is BADVA ffff800000218820 in first exception and BADVA ffff800000219020 in the second)

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I think I'm being destroyed by loongarch caching invalid TLB entries

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(and it's also why flanterm breaks if I fix it...)

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I think I'll fix it tomorrow

carmine nacelle Mar 15, 2025, 3:34 PM

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So I've decided to add early exceptions...

carmine nacelle Mar 15, 2025, 4:45 PM

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carmine nacelle I think I'm being destroyed by loongarch caching invalid TLB entries

I've kinda half fixed it

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I fixed the framebuffer...

carmine nacelle Mar 15, 2025, 5:54 PM

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So the kernel is trolling me

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Something is trashing $tp

left dew Mar 15, 2025, 5:58 PM

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how do you store the per cpu data ptr on loomgarch?

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im doing loongarch too but i havent had the time to read the manual yet :^)

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is there a csr you can use to restore it when entering the kernel from user space?

carmine nacelle Mar 15, 2025, 6:00 PM

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$s0 (aka $r23 has garbage)

carmine nacelle Mar 15, 2025, 6:00 PM

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left dew is there a csr you can use to restore it when entering the kernel from user spac...

It has 1-16 saved CSRs

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Linux uses 8 of them

left dew Mar 15, 2025, 6:00 PM

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ah, interesting

carmine nacelle Mar 15, 2025, 6:00 PM

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RISC-V only has one, so I did the same thing

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csrwr swaps the csr with the given general register, so you can save the thread-local stuff there

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So it's like kernel gs base in some sense

left dew Mar 15, 2025, 6:02 PM

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i thought thats what csrxchg was for

carmine nacelle Mar 15, 2025, 6:02 PM

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carmine nacelle It has 1-16 saved CSRs

1 is mandatory

left dew Mar 15, 2025, 6:02 PM

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or something like that

carmine nacelle Mar 15, 2025, 6:02 PM

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carmine nacelle > The CSRWR instruction writes the old value of the general register rd to the s...

left dew Mar 15, 2025, 6:02 PM

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lol real

carmine nacelle Mar 15, 2025, 6:02 PM

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left dew or something like that

I also though that initially, but it's like csrwr, but with a bitmask

left dew Mar 15, 2025, 6:02 PM

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thanks for explanation

carmine nacelle Mar 15, 2025, 6:04 PM

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not doing rd = csr, csr = rj

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More like

temp = csr & rj;
csr &= ~rj | rd;
rd = temp;

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idk

carmine nacelle Mar 15, 2025, 6:06 PM

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left dew i thought thats what csrxchg was for

do you have experience with risc-v?

left dew Mar 15, 2025, 6:06 PM

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nope

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i only have experience with x86

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but i want riscv too in my new kernel

carmine nacelle Mar 15, 2025, 6:08 PM

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carmine nacelle It has 1-16 saved CSRs

they have cpucfg which is like x86's CPUID which tells you a bunch of stuff about the CPU, including how many of saved CSRs you have

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Also machine check and tlb refill exceptions have their own save CSRs

left dew Mar 15, 2025, 6:11 PM

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how do you access kernel data structures from within the tlb refill handler?

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since it switches to physical address mode

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and kernel data structures use virtual addresses, or they should at least

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maybe im overthinking

carmine nacelle Mar 15, 2025, 6:13 PM

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left dew how do you access kernel data structures from within the tlb refill handler?

you don't

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(or through pc-relative instructions)

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I guess

carmine nacelle Mar 15, 2025, 6:14 PM

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left dew how do you access kernel data structures from within the tlb refill handler?

They give you a page table layout and instructions which refill the tub from page tables for you

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So you basically have normal page tables (with bad names for their fields in the manual)

carmine nacelle Mar 15, 2025, 6:14 PM

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carmine nacelle you don't

like you probably don't need to

carmine nacelle Mar 15, 2025, 6:31 PM

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carmine nacelle $s0 (aka $r23 has garbage)

This was destroying it

carmine nacelle Mar 15, 2025, 6:48 PM

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Very good documentation

kindred venture Mar 15, 2025, 6:50 PM

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what's wrong with those docs? seems perfectly fine to me

carmine nacelle Mar 15, 2025, 6:50 PM

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what is hint?

kindred venture Mar 15, 2025, 6:53 PM

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instruction category probably? it seems like the same kinda thing as the tables at the top of instruction docs in the x86 sdm, and its format is probably documented elsewhere in the manual

carmine nacelle Mar 15, 2025, 6:54 PM

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Maybe it's a me problem, but I didn't find it

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Like for other instructions it's explained in their documentation

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(Maybe I'm just spoiled by Intel docs)

kindred venture Mar 15, 2025, 6:58 PM

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oh hmm

carmine nacelle Mar 15, 2025, 7:00 PM

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I guess it's just an instruction encoding thing and only 0 is allowed

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(since loongarch has 32 bit instructions a bit like risc-v)

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(with fixed encoding formats)

carmine nacelle Mar 15, 2025, 8:26 PM

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I think I've reached userspace!

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(after fixing some brainrot)

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(can't even blame copilot for stupid code now cope )

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(astral negative influence)

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It's actually userspace and timer interrupt I think?

carmine nacelle Mar 15, 2025, 9:18 PM

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It was a timer interrupt

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The documentation is a bit confusing...

left dew Mar 15, 2025, 9:48 PM

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writing la assembly is an experience

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am i dumb or is the right way of moving data between two registers add.d $t0, $t1, $zero

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risc architectures are so cruel :(

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where's my mov $t0, $t1 nooo

hexed acorn Mar 15, 2025, 10:00 PM

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interesting that the assembler doesn't have a pseudoinstruction for that

left dew Mar 15, 2025, 10:20 PM

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im not sure if it does honestly, i just know that the manual does not specify one

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also llvm-objdump says there's move but idk what it does

hexed acorn Mar 15, 2025, 10:20 PM

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inb4 rep movsb

left dew Mar 15, 2025, 10:21 PM

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https://blog.xen0n.name/en/posts/tinkering/loongarch-faq/

The register move pseudo-instruction is called move, like MIPS. (Different from x86 or RISC-V; mov or mv are not recognized.)

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hmm

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might be exactly what im looking for

hexed acorn Mar 15, 2025, 10:23 PM

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{ 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */

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from a binutils patch

left dew Mar 15, 2025, 10:24 PM

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+ { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */

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oh lol

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we had the same idea

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anyway, nice! good to know

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replaced my add.d with move, so much cleaner now that i dont have to explicitly use $zero lol

carmine nacelle Mar 16, 2025, 12:10 AM

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left dew where's my `mov $t0, $t1` <:nooo:750466870993223750>

You have move

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Ok, I've gotten to userspace doing syscalls

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oof

carmine nacelle Mar 16, 2025, 12:11 AM

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left dew replaced my add.d with move, so much cleaner now that i dont have to explicitly ...

I think there are a bunch of other pseudo-instructions, like on RISC-V

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But I didn't find a good list

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(also, I'm pushing changes to dev branch all the time)

left dew Mar 16, 2025, 12:13 AM

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carmine nacelle But I didn't find a good list

like qookie said, the binutils patch is a good source :^)

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or not said but linked

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and not a singular patch but rather the binutils source in general

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the patch just tells you where to look

carmine nacelle Mar 16, 2025, 1:06 AM

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How did I miss that loongarch has a sane timer?

carmine nacelle Mar 16, 2025, 1:24 AM

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So, I need vector instructions...

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By the look of things, the userspace is alive

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(I think I'll figure that out tomorrow...)

carmine nacelle Mar 16, 2025, 10:21 AM

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So Linux does lazy saving of fp context? https://elixir.bootlin.com/linux/v6.13.6/source/arch/loongarch/kernel/traps.c#L507

hexed knot Mar 16, 2025, 10:31 AM

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huh?

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thats interesting

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its probably only on user/kernel reschedules though

carmine nacelle Mar 16, 2025, 11:52 AM

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Gotta love vscode...

carmine nacelle Mar 16, 2025, 3:17 PM

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https://elixir.bootlin.com/linux/v6.13.6/source/arch/loongarch/include/asm/asmmacro.h#L242 is it me, or is this broken?

asmmacro.h - arch/loongarch/include/asm/asmmacro.h - ...

Elixir Cross Referencer - source code of Linux v6.13.6: arch/loongarch/include/asm/asmmacro.h

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https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/memory/

carmine nacelle Mar 16, 2025, 4:13 PM

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What the fuck is this code

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Ok, the kernel is trolling me

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Something is corrupting memory...

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thonk

carmine nacelle Mar 16, 2025, 5:13 PM

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nevermind, it was a bug in my interrupt handler

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Omg

carmine nacelle Mar 16, 2025, 5:42 PM

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So what's crashing is Rust...

carmine nacelle Mar 16, 2025, 10:25 PM

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I think I'm in a mood of adding support for interrupt controllers...

carmine nacelle Mar 16, 2025, 11:30 PM

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(I think my interrupt handling mess needs to go)

carmine nacelle Mar 17, 2025, 12:21 AM

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Wow, my ns16550 driver just half-worked without touching anything

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(I'm missing the interrupt memes)

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Picking stuff up from ACPI

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(also, I don't know how to handle them yet)

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Like there is no obvious way to "return to userspace with interrutps on"

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(although I guess I can just mask them)

carmine nacelle Mar 17, 2025, 12:46 AM

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the interrupts are too galaxybrain for me and are refusing to work...

carmine nacelle Mar 17, 2025, 1:47 AM

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PIC is just refusing to work

carmine nacelle Mar 17, 2025, 12:09 PM

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Time to figure out how to trace it I guess...

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I don't get it; I think qemu doesn't bother to set up iocsr access to liointc?

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https://elixir.bootlin.com/qemu/v9.2.2/source/hw/intc/loongson_liointc.c#L234 ?

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Am I supposed to get this from AML?

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(anyway, I think I'm just gonna support this for the time being...)

carmine nacelle Mar 17, 2025, 1:35 PM

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So QEMU wants BIO PIC...

pearl narwhal Mar 17, 2025, 2:23 PM

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carmine nacelle PIC is just refusing to work

loongarch has dual 8259 PIC confirmed?

carmine nacelle Mar 17, 2025, 2:23 PM

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no

pearl narwhal Mar 17, 2025, 2:23 PM

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jk

carmine nacelle Mar 17, 2025, 2:24 PM

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it has hpet though

pearl narwhal Mar 17, 2025, 2:24 PM

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lol really?

carmine nacelle Mar 17, 2025, 2:39 PM

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i haven't looked at it in depth, but the manual mentions hpet, and it seems to be very similar to x86

carmine nacelle Mar 17, 2025, 5:21 PM

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The ACPI is being weird

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It says that BIO PIC GSI starts at 48...

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I wonder if there's some sort of interrupt override thing

#

(Or I need to change the ACPI interrupt model)

carmine nacelle Mar 17, 2025, 5:31 PM

#

carmine nacelle (Or I need to change the ACPI interrupt model)

nope, this is x86 only thing

carmine nacelle Mar 17, 2025, 6:18 PM

#

So, through my rigorous investigation (a bunch of printfs), I have concluded that QEMU has EIO PIC, BIO PIC and MSI PIC

#

Now, I am completely clueless how I'm supposed to get it to work

#

Since Linux has decided to use different names for things https://docs.kernel.org/arch/loongarch/irq-chip-model.html

#

Like ugh what do I do with this bruh

#

(So EIO PIC is the Loongson 3A5000 controller, and BIO PIC is 7A1000 controller)

twilit talon Mar 17, 2025, 6:28 PM

#

Did you figure it out

twilit talon Mar 17, 2025, 6:28 PM

#

carmine nacelle Like ugh what do I do with this <:bruh:761542241381908491>

Which table is this?

carmine nacelle Mar 17, 2025, 7:04 PM

#

MADT

carmine nacelle Mar 17, 2025, 7:14 PM

#

twilit talon Did you figure it out

But I don't get what I'm supposed to do with the node ID

twilit talon Mar 17, 2025, 7:24 PM

#

carmine nacelle But I don't get what I'm supposed to do with the node ID

it's probably the numa node id?

#

in your case you have only one

carmine nacelle Mar 17, 2025, 7:37 PM

#

What I don't quite get is why it doesn't give me address

twilit talon Mar 17, 2025, 7:38 PM

#

Base Address?

carmine nacelle Mar 17, 2025, 7:38 PM

#

Yeah

#

I've tried to use the one provided in the manual and nothing hallpened

#

(But with legacy controller)

#

Maybe QEMU doesn't implement it at all?

twilit talon Mar 17, 2025, 7:39 PM

#

git grep

carmine nacelle Mar 17, 2025, 7:39 PM

#

I'll try to figure it out

#

https://elixir.bootlin.com/qemu/v9.2.2/source/hw/intc/loongarch_extioi.c

carmine nacelle Mar 17, 2025, 7:47 PM

#

carmine nacelle https://elixir.bootlin.com/qemu/v9.2.2/source/hw/intc/loongarch_extioi.c

This is EIO PIC

#

#

I mean except the cascade vector, this is what I expected

#

Time to add more pritnfs to qemu...

twilit talon Mar 17, 2025, 7:54 PM

#

is this where ur reading from?

carmine nacelle Mar 17, 2025, 7:55 PM

#

I'm trying to use iocsr instructions

carmine nacelle Mar 17, 2025, 7:56 PM

#

twilit talon

Also, this is different from manual

twilit talon Mar 17, 2025, 7:56 PM

#

carmine nacelle Time to add more pritnfs to qemu...

there's already a trace_loongarch_extioi_readw

carmine nacelle Mar 17, 2025, 10:42 PM

#

twilit talon there's already a `trace_loongarch_extioi_readw`

It's just quiet

#

I'm probably doing it wrong then

carmine nacelle Mar 17, 2025, 11:02 PM

#

Idk, I want to get over with it, but I'm just feeling unwell and don't understand anything

#

(I think I'm getting close to a burnout, which is suboptimal)

carmine nacelle Mar 17, 2025, 11:18 PM

#

carmine nacelle It's just quiet

I think it just wants me to use the extended mechanism

#

I'll just panic if I detect legacy only system

#

The kernel first identifies the extended interrupt mode support by CSR[0x8][3], and then enables the
extended interrupt mode by register CSR[0x420][48].

#

Ok, I am writing to the right place, at least

carmine nacelle Mar 18, 2025, 12:25 AM

#

thonk

#

It's not showing byte-width accesses

#

Is it what's messing everything up?

#

#

I am dumb

#

The dumbness has been ratified

#

I still have no interrupts nooo

#

This is just trolling

#

Maybe it needs to be level-triggered...

#

Like this is the only thing which might be broken

#

death

carmine nacelle Mar 18, 2025, 12:56 AM

#

carmine nacelle This is just trolling

(the addresses are relative to 0x1400, so I'm setting interrupt enable to 1, and CPU mask to 0x01, which should be correct...)

#

and it's impossible to debug because of pagefaults

twilit talon Mar 18, 2025, 7:07 AM

#

carmine nacelle

Is it because your access width was wrong?

carmine nacelle Mar 18, 2025, 8:21 AM

#

twilit talon Is it because your access width was wrong?

I've changed it to use 32 and 64 bit reads and writes

carmine nacelle Mar 18, 2025, 9:22 AM

#

So linux is doing some weirdness with its interrupts

#

Am I supposed to be using both of the controllers? https://docs.kernel.org/arch/loongarch/irq-chip-model.html

#

Like UART is still conected to lioint

#

In newer generation Loongson CPUs, Extend I/O Programmable Interrupt Controller (EIO PIC) replaces the combination
of HT PIC and part of LIO PIC, and routes interrupts from BIO PIC and MSI PIC to CORE PIC directly. The
format of the EIO PIC structure is shown in the following table.

#

"part of LIO PIC"

carmine nacelle Mar 18, 2025, 9:59 AM

#

I think qemu has no LIO PIC

#

What am I missing?

carmine nacelle Mar 18, 2025, 10:20 AM

#

bruh

#

It was not 0

#

https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/serial-port-console-redirection-table

Serial Port Console Redirection Table (SPCR) - Windows drivers

The Serial Port Console Redirection Table that is used to indicate whether a serial port or a non-legacy UART interface is available for use with Microsoft® Windows® Emergency Management Services (EMS).

#

I think this SPCR is invalid?

#

I'm gonna add #ifdef to it

#

Nope, still no interrupts...

carmine nacelle Mar 18, 2025, 10:56 AM

#

Desperate times call for desperate measures (I've added more printfs to QEMU)

#

This looks wrong

#

Yeah, it should 66 and not 112

#

This is broken

#

(except it's not)

carmine nacelle Mar 18, 2025, 11:23 AM

#

I don't get it, this seems to be broken https://elixir.bootlin.com/qemu/v9.2.2/source/hw/intc/loongarch_extioi.c#L128

#

Nevermind, I can't read

carmine nacelle Mar 18, 2025, 1:35 PM

#

Maybe I do need BIO PIC after all...

#

Yeah, I think UART is connected to it

#

thonk

carmine nacelle Mar 18, 2025, 2:26 PM

#

I think I'm starting to see the parallels

#

The EIO PIC is like LAPIC, and GIO PIC is like IOAPIC

carmine nacelle Mar 18, 2025, 3:32 PM

#

Lol, they literally call it IO-APIC

carmine nacelle Mar 18, 2025, 3:59 PM

#

I think the time has come to finally move interrupt allocation to the kernel

#

This sounds like lapic

In addition to being compatible with the legacy I/O interrupt method, the 3A5000 supports extended I/O
interrupts, which are used to distribute 256-bit interrupts on the HT bus directly to each processor core
instead of forwarding them through the HT interrupt line, increasing the flexibility of I/O interrupt usage.

carmine nacelle Mar 18, 2025, 6:41 PM

#

Through breaking interrupts, I now have serial console...

carmine nacelle Mar 18, 2025, 7:02 PM

#

carmine nacelle I think the time has come to finally move interrupt allocation to the kernel

The manual says that the kernel should write to BIO PIC to ack interrupts...

carmine nacelle Mar 18, 2025, 8:21 PM

#

(Time to add a new syscall)

carmine nacelle Mar 18, 2025, 10:28 PM

#

What the fuck

carmine nacelle Mar 18, 2025, 11:50 PM

#

Ok, so the interrupt controllers situation is insane

#

on loongarch

toxic torrent Mar 19, 2025, 12:09 AM

#

where is it not tbh

carmine nacelle Mar 19, 2025, 12:11 AM

#

Ok RISC-V you can just risc and use PLIC and don't think about it

carmine nacelle Mar 19, 2025, 12:38 AM

#

I think I'm liking the new interrupts interface...

left dew Mar 19, 2025, 12:43 AM

#

why result2

#

is it a different result than result? lol

carmine nacelle Mar 19, 2025, 12:44 AM

#

Different type

#

because not Rust

left dew Mar 19, 2025, 12:45 AM

#

why is it a different type

#

anyway that looks pretty nice

carmine nacelle Mar 19, 2025, 12:45 AM

#

because it returns result + vector from the kernel

#

it's a struct

left dew Mar 19, 2025, 12:45 AM

#

ah, well you don't seem to use it though meme

carmine nacelle Mar 19, 2025, 12:45 AM

#

(my kernel always returns int64_t result and uint64_t value)

#

yeah

#

It should be the same as vector

left dew Mar 19, 2025, 12:46 AM

#

you can also docpp if (auto res = ...; !res) { // ... }

carmine nacelle Mar 19, 2025, 12:46 AM

#

I know

#

(sad that C doesn't have it)

left dew Mar 19, 2025, 12:46 AM

#

you can emulate that

#

somewhat easily

#

if (({ int res = ...; res != 0; })) {
  // ...
}```

#

you can probably macro it away

carmine nacelle Mar 19, 2025, 12:49 AM

#

but that's gcc extension

left dew Mar 19, 2025, 12:50 AM

#

so what lol

#

who writes real C anyway

#

embrace GNU gnuslashtroll

carmine nacelle Mar 19, 2025, 12:51 AM

#

carmine nacelle Through breaking interrupts, I now have serial console...

So I've programmed the second controller, but interrupts still refuse to work nooo

#

The writes don't get to the controller

#

I'm going to sleep

carmine nacelle Mar 19, 2025, 12:54 AM

#

carmine nacelle The writes don't get to the controller

(qemu trace doesn't show writes to the registers)

left dew Mar 19, 2025, 12:57 AM

#

sounds like you aren't writing the registers

carmine nacelle Mar 19, 2025, 12:57 AM

#

Or maybe qemu is insane

#

(https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/loongarch64/pic.cc?ref_type=heads#L271)

GitLab

kernel/arch/loongarch64/pic.cc · dev · Mikhail Kovalev / pmOS · Git...

GitLab.com

carmine nacelle Mar 19, 2025, 9:28 AM

#

What am I doing wrong kms

carmine nacelle Mar 19, 2025, 9:51 AM

#

Could ACPI be just wrong?

#

Since Linux doesn't use it

#

(or does it? thonk )

twilit talon Mar 19, 2025, 9:55 AM

#

carmine nacelle (or does it? <:thonk:575445129863888896>)

carmine nacelle Mar 19, 2025, 9:56 AM

#

Is there a way to see where qemu places this in memory? https://elixir.bootlin.com/linux/v6.14-rc6/source/drivers/irqchip/irq-loongson-pch-pic.c

irq-loongson-pch-pic.c - drivers/irqchip/irq-loongson...

Elixir Cross Referencer - source code of Linux v6.14-rc6: drivers/irqchip/irq-loongson-pch-pic.c

#

(wrong source)

#

This https://elixir.bootlin.com/qemu/v9.2.2/source/hw/intc/loongarch_pch_pic.c

twilit talon Mar 19, 2025, 9:57 AM

#

well the address is definitely fetched from madt https://elixir.bootlin.com/linux/v6.14-rc6/source/drivers/irqchip/irq-loongson-eiointc.c#L376

irq-loongson-eiointc.c - drivers/irqchip/irq-loongson...

Elixir Cross Referencer - source code of Linux v6.14-rc6: drivers/irqchip/irq-loongson-eiointc.c

carmine nacelle Mar 19, 2025, 9:58 AM

#

I had been bitten by ACPI tables being broken in QEMU

#

On RISC-V

#

I don't know why it doesn't work

twilit talon Mar 19, 2025, 10:00 AM

#

tbh i have no idea where qemu assigns memory to these regions

carmine nacelle Mar 19, 2025, 10:01 AM

#

thonk I don't have memory clobbers on inline assembly...

#

The assembly looks different

#

nope, still broken

carmine nacelle Mar 19, 2025, 1:53 PM

#

Brain damage

#

(see line 337 and 357)

#

I think it's somewhat working...

twilit talon Mar 19, 2025, 1:58 PM

#

carmine nacelle Brain damage

Wtf

carmine nacelle Mar 19, 2025, 2:00 PM

#

I forgot an ~

#

This looks better

#

But still no interrupts nooo

#

(except that the enable bit is not what it should be)

#

(why am I failing so badly at this?)

#

I can't believe it...

carmine nacelle Mar 19, 2025, 3:13 PM

#

So this is basically PLIC with extra complications...

carmine nacelle Mar 19, 2025, 3:53 PM

#

I think I have interrupts!

#

Or not...

carmine nacelle Mar 19, 2025, 4:18 PM

#

So it works, but I'm getting an interrupt storm

twilit talon Mar 19, 2025, 4:23 PM

#

now do the ged thing

carmine nacelle Mar 19, 2025, 4:25 PM

#

I want to fix interrupts nooo

carmine nacelle Mar 19, 2025, 4:29 PM

#

carmine nacelle So this is basically PLIC with extra complications...

I wonder if they want me to disable the interrupt flag

carmine nacelle Mar 19, 2025, 4:50 PM

#

I am too dumb for this...

#

Either I don't understand something (very likely) or QEMU dgaf about interrupt masking

carmine nacelle Mar 19, 2025, 5:02 PM

#

carmine nacelle So this is basically PLIC with extra complications...

The spec says that you do have to mask them if you don't use HT

carmine nacelle Mar 19, 2025, 5:04 PM

#

carmine nacelle So this is basically PLIC with extra complications...

Like this implies that the interrupts are edge triggered?

#

Why is it spamming the interrupts then?

#

Ok, it works with the terrible thing...

carmine nacelle Mar 19, 2025, 5:27 PM

#

carmine nacelle Ok, it works with the terrible thing...

I'm sticking with it

carmine nacelle Mar 19, 2025, 6:48 PM

#

What the fuck is this assembly

;     la     $t0, on_failure
ffffffff80003098: 8c 09 00 1a      pcalau12i    $t0, 76
ffffffff8000309c: 8c c1 d0 28      ld.d    $t0, $t0, 1072
;     st.d   $t0, $tp, 48 # CPU_Info::jumpto_func
ffffffff800030a0: 4c c0 c0 29      st.d    $t0, $tp, 48

carmine nacelle Mar 19, 2025, 7:04 PM

#

carmine nacelle I am too dumb for this...

It's probably broken because I'm setting level triggered interrupt as edge triggered

#

But SPCR does tell me the interrupt level

#

Which is fun

#

Though it shouldn't matter

carmine nacelle Mar 19, 2025, 8:24 PM

#

(reference to myself https://reviews.llvm.org/D138021)

#

Also, doesn't limine do GOT relocations?

carmine nacelle Mar 19, 2025, 10:13 PM

#

Omg, I think I know why fork is broken on RISC-V

#

(this was making the loongarch build hang)

eager rose Mar 19, 2025, 10:16 PM

#

carmine nacelle What the fuck is this assembly ```mips ; la $t0, on_failure ffffffff8000...

ahh yes. pcalau12i $t0, 76.

carmine nacelle Mar 19, 2025, 10:16 PM

#

I've discovered that la is la.got by default

#

And my GOT is broken?

carmine nacelle Mar 19, 2025, 10:19 PM

#

carmine nacelle Omg, I think I know why fork is broken on RISC-V

I have no idea how x86 builds weren't crashing...

#

(I think I need a reschedule defer mechanism...)

carmine nacelle Mar 19, 2025, 10:33 PM

#

carmine nacelle (I think I need a reschedule defer mechanism...)

For context: since I don't switch contexts, the rescheduling could be a race condition since the task could appear on the other CPU, so on these syscalls, I set the result to success before the copy to user is completed, which overwrites the arguments on loongarch, risc-v and i686...

#

(which switches the task inside it)

#

But I think the loongarch build kinda fully works now

#

I just need to fix the other builds and also change the interrupt registering stuff

twilit talon Mar 19, 2025, 10:41 PM

#

Does it have an _S5 btw

carmine nacelle Mar 19, 2025, 10:42 PM

#

I haven't checked

#

I'm feeling very burnt out

twilit talon Mar 19, 2025, 10:43 PM

#

Take your time to chill

carmine nacelle Mar 19, 2025, 10:44 PM

#

And I have exams next week

#

I think I'll finish/fix the other ports parts so it's presentable enough to be in the main branch and doesn't linger on me, and take a break for a couple of weeks

carmine nacelle Mar 19, 2025, 10:46 PM

#

carmine nacelle But I think the loongarch build kinda fully works now

By kinda fully working I mean basically complete, except the (platform independent) interrupt API changes induced stuff which I need to fix

carmine nacelle Mar 20, 2025, 2:14 PM

#

I think I'll fix RISC-V memes...

carmine nacelle Mar 20, 2025, 2:46 PM

#

(note to myself: qemu-system-loongarch64 -m 2G -cdrom limine/pmOS.iso -smp 4 -serial stdio -bios ovmf-riscv64/RELEASELOONGARCH64_QEMU_EFI.fd -device ramfb)

#

Uncool

#

It's trolling me

#

I'm not returning nullptr there...

carmine nacelle Mar 20, 2025, 6:50 PM

#

Cool, my brain is fried from the loongarch assembly

#

I can't write RISC-V one anymore

carmine nacelle Mar 20, 2025, 7:56 PM

#

(so I almost have fast syscalls on risc-v)

plain jungle Mar 20, 2025, 8:07 PM

#

fast syscalls?

carmine nacelle Mar 20, 2025, 8:08 PM

#

Basiccally doing memcpy on user memory and catching pagefaults

#

Instead of walking the page tables every time I copy from user

left dew Mar 20, 2025, 8:08 PM

#

holy ☠️

#

how have u went so far without a proper user memcpy

twilit talon Mar 20, 2025, 8:08 PM

#

carmine nacelle Instead of walking the page tables every time I copy from user

thats not safe at all

carmine nacelle Mar 20, 2025, 8:09 PM

#

twilit talon thats not safe at all

But it worked

carmine nacelle Mar 20, 2025, 8:09 PM

#

left dew how have u went so far without a proper user memcpy

It's proper, just very slow

twilit talon Mar 20, 2025, 8:09 PM

#

if u lock the address space

#

then its fine

carmine nacelle Mar 20, 2025, 8:09 PM

#

I do

left dew Mar 20, 2025, 8:09 PM

#

i mean yeah i guess, but it's kinda badddd

twilit talon Mar 20, 2025, 8:10 PM

#

thats literally more lines of code than just catching a fault

carmine nacelle Mar 20, 2025, 8:10 PM

#

It was a design skill issue

#

I'm trying to catch them now

#

Besides, it works on x86 and loongarch already

twilit talon Mar 20, 2025, 8:10 PM

#

if loongarch is so good, wheres loongerarch

carmine nacelle Mar 20, 2025, 8:12 PM

#

MIPS? trl

carmine nacelle Mar 20, 2025, 8:12 PM

#

carmine nacelle It was a design skill issue

I was setting on all interrupts, so the kernel couldn't preempt itself properly

carmine nacelle Mar 20, 2025, 8:13 PM

#

twilit talon thats literally more lines of code than just catching a fault

So like it was not galaxybrain

twilit talon Mar 20, 2025, 8:15 PM

#

btw u should support smap/smep etc

carmine nacelle Mar 20, 2025, 8:16 PM

#

Yeah

#

I even have hooks for them

#

I do support them on RISC-V

carmine nacelle Mar 20, 2025, 10:03 PM

#

The kernel is choosing violence

#

I think everything is calling exit again nooo

#

No?

#

The screen and ns16550 drivers are just refuse to work...

carmine nacelle Mar 20, 2025, 11:15 PM

#

actual brainrot

#

(this should be a0-a2)

#

so by the looks of things, the RISC-V port is also fully working now...

carmine nacelle Mar 21, 2025, 9:16 AM

#

So the plan is to

Fix x86 port, and by that I mean moving IOAPIC code to kernel
Change the drivers to use that

carmine nacelle Mar 21, 2025, 4:53 PM

#

Nice code

carmine nacelle Mar 21, 2025, 9:21 PM

#

How did not know that this was in C? https://en.cppreference.com/w/c/language/generic

#

Cool, using auto in C feels magical...

#

the kernel is trolling me

#

It's tripple faulting

#

I think I need to take a break

#

It is trolling me hard

#

It's casually faulting with error 0 with instruction ... cmpq %rdi, 0x10

carmine nacelle Mar 21, 2025, 10:08 PM

#

thonk

carmine nacelle Mar 22, 2025, 10:50 AM

#

Fun, the kernel ooms and dies if I enable LAPICs nooo

carmine nacelle Mar 22, 2025, 11:54 AM

#

This makes absolutely no sense

#

What the fuck

#

It has to be something extremely dumb

carmine nacelle Mar 22, 2025, 12:30 PM

#

So somehow this is just broken...

#

I think I've caught it

#

There is no such thing as too many asserts

#

I was missing a ~ again

carmine nacelle Mar 22, 2025, 3:06 PM

#

IOAPIC in kernel finally seems to be working...

#

bruh

carmine nacelle Mar 22, 2025, 3:46 PM

#

fun, the 32 bit x86 port is dead for some reason...

#

it's not dead but interrupts are broken nooo

#

(Even though it shares the interrupt code with x86_64)

carmine nacelle Mar 22, 2025, 4:29 PM

#

RISC-V and LoongArch are fully working

#

I think I'll fix the ia32 port (after taking a nap) and then push loongarch stuff to main

#

And maybe I'll write the GED driver after that

carmine nacelle Mar 22, 2025, 8:04 PM

#

uACPI server hangs?

#

(probably a skill issue)

#

Or like doesn't hang, but it doesn't ack the interrupt for some reason

#

Maybe I broke something

carmine nacelle Mar 22, 2025, 8:25 PM

#

carmine nacelle uACPI server hangs?

It doesn't

carmine nacelle Mar 22, 2025, 8:46 PM

#

bruh

carmine nacelle Mar 22, 2025, 9:10 PM

#

EC stopped working??

#

i think the kernel is panicking...

#

Anyway, I merged the changes to main

#

Unfun...

carmine nacelle Mar 22, 2025, 10:29 PM

#

Ok, I fixed it

#

But my Lenovo laptop still seems to be unable to recieve EC interrupts...

#

I have a suspicion my com driver is misconfiguring the baud rate...

#

interrupts are very broken

carmine nacelle Mar 22, 2025, 10:57 PM

#

i have no idea why

#

and have very little motivation to fix them

#

(or do anything)

#

nooo

#

(maybe it's kernel panic)

#

Maybe I should announce my OS on Reddit trl

lunar orchid Mar 23, 2025, 1:30 AM

#

👀👀👀

carmine nacelle Mar 23, 2025, 10:46 AM

#

The kernel is hardcore trolling me

#

I've put a printfs around it, and there are no interrupts, at all

#

on physical hardware

#

like not even apic timer interrupt

carmine nacelle Mar 23, 2025, 11:59 AM

#

Cool, the ns16550 driver has started working on my PC

#

In i686 build...

#

I have no clue of what's going on...

#

Still no SCI

carmine nacelle Mar 23, 2025, 12:00 PM

#

carmine nacelle Cool, the ns16550 driver has started working on my PC

But this does use interrupts...

twilit talon Mar 23, 2025, 1:00 PM

#

carmine nacelle Cool, the ns16550 driver has started working on my PC

Why the hell is hpet under root

carmine nacelle Mar 23, 2025, 1:02 PM

#

Probably for the same reason that firmware remaps LAPICs

carmine nacelle Mar 23, 2025, 1:54 PM

#

I think I've fixed SCIs...

carmine nacelle Mar 23, 2025, 2:30 PM

#

So, I think I have kinda completed what I wanted (LoongArch port) and it would be best for me to take a break from osdev

#

The only thing missing from it compared to other platforms (x86, RISC-V) is SMP (since it's not supported by Limine), and I also wanted to write an ACPI GED driver for it, but I feel like I'm too burnt out to do it now

#

The next plan would be to write the proper init server, which would include listening to pmbus events and starting drivers, as they are discovered by ACPI/PCI/other buses, then finish the ext4 driver (in Rust) and try to get bash working

carmine nacelle Mar 24, 2025, 9:02 PM

#

But I want to do GED...

carmine nacelle Mar 25, 2025, 2:03 PM

#

I've decided to write an init server

restive junco Mar 25, 2025, 2:05 PM

#

carmine nacelle How did not know that this was in C? https://en.cppreference.com/w/c/language/ge...

this one's really nice

carmine nacelle Mar 25, 2025, 2:11 PM

#

carmine nacelle I've decided to write an init server

Maybe I should move processes to the kernel after all? thonk

twilit talon Mar 25, 2025, 2:12 PM

#

you've just discovered the idea of a monolithic kernel!

carmine nacelle Mar 25, 2025, 2:13 PM

#

no

#

process as a collection of threads

#

Idk what to do nooo

#

I'm in a design limbo

#

Like the issue is that I want to track processes in my init server, but I need process server for that, which can't then be tracked by init

#

Maybe I should merge them into one server trl

#

this would solve all of my problems galaxybrain

#

The only issue is that my init server is in C, and my processes server is in C++

#

And I don't like C

carmine nacelle Mar 25, 2025, 2:19 PM

#

carmine nacelle I've decided to write an init server

Since I also want that to eventually be able to catch failing servers and restart them

inland temple Mar 25, 2025, 4:06 PM

#

systemd troll

carmine nacelle Mar 25, 2025, 4:54 PM

#

inland temple systemd <:troll:796858892985434152>

Can it listen to (p)mbus?

inland temple Mar 25, 2025, 4:54 PM

#

if you integrate it meme

#

not sure

carmine nacelle Mar 25, 2025, 4:58 PM

#

I'm planning my init server to do it

inland temple Mar 25, 2025, 5:00 PM

#

on managarm, once devices show up on mbus, posix creates the sysfs stuff for them, and they show up on udev

#

from where on out we use udev rules for starting servers

#

for systemd, we have a service that awaits for a keyboard, mouse and DRM card to be available before continuing to launch weston/kmscon

#

depends on how you define "integration" ig

twilit talon Mar 25, 2025, 5:07 PM

#

inland temple from where on out we use udev rules for starting servers

Thats pretty smart

carmine nacelle Mar 25, 2025, 5:09 PM

#

yeah I guess that's cool

#

But too much work

covert apex Mar 25, 2025, 5:09 PM

#

inland temple for systemd, we have a service that awaits for a keyboard, mouse and DRM card to...

Technically that’s a binary that waits for it and we execute it as ExecStartPre

carmine nacelle Mar 25, 2025, 10:12 PM

#

I think I'll merge the init and POSIX servers into one...

carmine nacelle Mar 25, 2025, 11:39 PM

#

What if I want to port to ARM?

carmine nacelle Mar 26, 2025, 1:07 PM

#

carmine nacelle I think I'll merge the init and POSIX servers into one...

And for that I think I'll implement IPC handles/capabilities

carmine nacelle Mar 27, 2025, 12:39 AM

#

My vmm is deciding to troll me nooo

#

I think it's broken

carmine nacelle Mar 27, 2025, 9:30 AM

#

I've found various bugs in my vmm

#

I have no idea how it didn't crash before

carmine nacelle Mar 27, 2025, 9:56 AM

#

VMM now works properly KEKW

fringe grove Mar 27, 2025, 11:52 AM

#

carmine nacelle VMM now works properly <:KEKW:913708372329644042>

no it doesnt

#

you think it does

#

but it doesnt

#

never belive the vmm

#

it only knows how to lie to you

carmine nacelle Mar 27, 2025, 11:52 AM

#

I've put a bunch of printfs and it did seem correct

fringe grove Mar 27, 2025, 11:52 AM

#

seem!!!!

#

not 100%

#

smh

#

https://cdn.discordapp.com/emojis/1348767893084569771.gif?size=48&animated=true&name=RosBouncy

carmine nacelle Mar 27, 2025, 3:35 PM

#

Small update: I've decided to move the port resolution by name into bootstrap server as well, and I think I can hook it into init server as well, which is pretty interesting I guess...

carmine nacelle Mar 27, 2025, 3:51 PM

#

pmOS - microkernel OS for RISC-V, x86, and LoongArch

inland temple Mar 27, 2025, 4:16 PM

#

mlibc is getting loongarch support soon™️

#

when switch to mlibc?

#

meme

carmine nacelle Mar 27, 2025, 10:55 PM

#

my libc and kernel supports loongarch without soon™️

toxic torrent Apr 6, 2025, 6:43 PM

#

@carmine nacelle did you have to do anything special to port gcc to loongarch?

#

it's giving me this bullshit

#

my honest reaction

carmine nacelle Apr 6, 2025, 6:46 PM

#

I'm just using clang ultrameme

#

I haven't tried it, I need to check

toxic torrent Apr 6, 2025, 6:47 PM

#

lmfao

#

im tempted to just switch to clang as well

carmine nacelle Apr 6, 2025, 6:47 PM

#

Like it and rust just worked no questions asked

#

(clang + lld+ libc++)

toxic torrent Apr 6, 2025, 6:48 PM

#

that's crazy

#

got a link to your fork/patch?

carmine nacelle Apr 6, 2025, 6:48 PM

#

It's in my gitlab

toxic torrent Apr 6, 2025, 6:48 PM

#

kk

carmine nacelle Apr 6, 2025, 6:49 PM

#

https://gitlab.com/mishakov/llvm-pmos

#

I think binutils also had just worked

#

(at least it compiled and GCC worked with "no issues" (except ocasional segafults))

toxic torrent Apr 6, 2025, 6:51 PM

#

neat

#

do you define a dynamic linker anywhere?

carmine nacelle Apr 6, 2025, 6:53 PM

#

I don't support it

toxic torrent Apr 6, 2025, 6:53 PM

#

ah

carmine nacelle Apr 6, 2025, 6:53 PM

#

(I need to work on it)

#

But I think you define it in os-specific C++ class thing

toxic torrent Apr 6, 2025, 6:53 PM

#

yea

#

i think that's so much nicer

#

than whatever gcc is doing

#

also spec 🤢

carmine nacelle Apr 6, 2025, 6:54 PM

#

somewhere here https://gitlab.com/mishakov/llvm-pmos/-/blob/main/clang/lib/Driver/ToolChains/pmOS.cpp?ref_type=heads

toxic torrent Apr 6, 2025, 6:54 PM

#

okay yay it's building with the weird ass hack

carmine nacelle Apr 6, 2025, 6:55 PM

#

toxic torrent i think that's so much nicer

yeah, it's just a bunch of C++ which takes care of everything

toxic torrent Apr 6, 2025, 6:55 PM

#

fyi i had to do this shit

carmine nacelle Apr 6, 2025, 6:55 PM

#

in gcc?

toxic torrent Apr 6, 2025, 6:55 PM

#

ye

#

cursed

carmine nacelle Apr 6, 2025, 6:56 PM

#

isn't it what you're supposed to do?

toxic torrent Apr 6, 2025, 6:56 PM

#

no

#

well not for the other archs

carmine nacelle Apr 6, 2025, 6:56 PM

#

(I mean I don't use mlibc so that's what I was doing as well)

toxic torrent Apr 6, 2025, 6:56 PM

#

only loongarch has this garbage hack

carmine nacelle Apr 6, 2025, 6:56 PM

#

ok, idk

#

I don't have motivation to touch my gcc stuff right now

toxic torrent Apr 6, 2025, 6:57 PM

#

don't bother

#

i think my llvm toolchain works as well so far, except it doesn't have a dynamic linker for some reason

#

like no interp

kindred venture Apr 6, 2025, 6:57 PM

#

that all seems pretty standard, i imagine the only reason you didn't have to do it for anything else would be if mlibc support for those targets was upstreamed into gcc

toxic torrent Apr 6, 2025, 6:58 PM

#

hm

#

it's weird they hardcoded this though

#

like, ever other target doesn't have this switch

carmine nacelle Apr 6, 2025, 6:58 PM

#

kindred venture that all seems pretty standard, i imagine the only reason you didn't have to do ...

Wait, when did that happen?

kindred venture Apr 6, 2025, 6:59 PM

#

i don't know if it is, i just don't know any other reason why that wouldn't be required for other targets

#

or well, the top hunk seems standard, the triplet_os=... thing is weird

toxic torrent Apr 6, 2025, 7:00 PM

#

yes

#

that's what i mean

kindred venture Apr 6, 2025, 7:00 PM

#

ah ok

toxic torrent Apr 6, 2025, 7:01 PM

#

#

they unset the target for some reason

carmine nacelle Apr 7, 2025, 12:58 AM

#

Small update: after a week being unmotivated and debugging it with no printf, I've managed to move "named ports" stuff to bootstrap daemon, and will be removing it from kernel shortly

#

after which the plan is to finally add handles/capabilities/whatever the name is to the IPC

#

I don't know how to name it so it's not too confusing

#

Right now I have ports, and I want to be giving out send "capabilities"/whatever I decide to call it

#

Mach calls it rights?

carmine nacelle Apr 7, 2025, 7:48 AM

#

thonk I've looked at Mach docs and it talks about port rights namespace, which gave me an idea...

#

I have task groups, so I thought about associating port rights to them, but didn't want to do that because I would have to look up the task group, verify that the task is part of it, and then look up to port/right inside the tak group...

#

What I think I'll do instead is I'll have add a way to set the default task group for ports, which will just be a pointer, which kinda solves all the problems

#

So the libc will probably just set it to be the task group of the process, but you're free to redefine it if you want to...

#

But first I have to replace this atrocity (shared pointers for task groups) with RCU

#

(too many things to do nooo )

bitter wasp Apr 7, 2025, 8:12 AM

#

carmine nacelle But first I have to replace this atrocity (shared pointers for task groups) with...

wouldnt be that atrocious if it were an rwlock

carmine nacelle Apr 7, 2025, 8:47 AM

#

the lock isn't the problem, I can easily replace it

#

My shared pointers impl is kinda bad and I'm trying to get rid of it

carmine nacelle Apr 9, 2025, 12:18 PM

#

bruh my ports already used RCU...

#

(which is convenient I guess)

#

I think I know how I would implement the rights thing

#

Mach has a refcount, but I don't like it, I'll just have one right per task (group)

carmine nacelle Apr 9, 2025, 12:23 PM

#

carmine nacelle But first I have to replace this atrocity (shared pointers for task groups) with...

This is why it's not an rwlock (I've been using splay trees galaxybrain )

toxic torrent Apr 9, 2025, 12:45 PM

#

awesome highlighting

carmine nacelle Apr 9, 2025, 1:24 PM

#

average vscode experience

carmine nacelle Apr 9, 2025, 5:04 PM

#

Nice types

carmine nacelle Apr 9, 2025, 5:46 PM

#

carmine nacelle But first I have to replace this atrocity (shared pointers for task groups) with...

So I've converted this to RCU, but I now have a feeling that it's use after free/double free minefield...

toxic torrent Apr 9, 2025, 5:59 PM

#

what's an RCU

carmine nacelle Apr 9, 2025, 6:16 PM

#

Read copy update

plain jungle Apr 9, 2025, 6:34 PM

#

an algorithm to manage lifetimes in concurrent programs

#

say, if you have a lock free linked list and you delete an element. you can only truly release the memory when no other thread can still have a pointer to it

#

and that's what RCU ensures

carmine nacelle Apr 9, 2025, 7:52 PM

#

thonk I think I more or less have the idea of how I'm going to implement the rights thing...

#

and the interface should also be relatively nice, I'm going to add a (atomic) syscall, which allows to set the task group for the rights namespace by the thread, and I'm going to limit it to the caller thread and the task group it is in, so there will not be a need to use locks, or check permissions...

#

And for the kernel stuff, I'm going to create a task group, which would have the idle (and if I add them, general kernel) threads

#

Which could also be used for other stuff, like for example, at the moment I use the task groups to track threads in processes, and detect when a thread exits unexpectedly

carmine nacelle Apr 10, 2025, 8:05 AM

#

I think I know how I'm gonna handle notifications about rights being closed (on the other side)

#

Don't know it it's the best solution, but I'll insert all the rights into a tree in the parent port (with my intrusive BST class), keyed by some internal ID, and I'll allow duplicate nodes there and do count() on their deletion

#

I like this better than keeping some common data structure (if that makes sense)

#

The send once rights (which I anticipate to be the most common/created and deleted the most I guess) will not have to do this

carmine nacelle Apr 10, 2025, 10:32 AM

#

(also, I think this will solve the IPC balancing in multithreaded processes thonk )

carmine nacelle Apr 10, 2025, 1:41 PM

#

What the fuck

toxic torrent Apr 10, 2025, 1:43 PM

#

carmine nacelle What the fuck

did you include the .cc on accident?

carmine nacelle Apr 10, 2025, 1:43 PM

#

no

#

thonk

#

I think one is in global namespace, and the other is in kernel::sched

#

(I've just decided to add namesapces to kernel)

modest thistle Apr 10, 2025, 2:20 PM

#

lol

carmine nacelle Apr 11, 2025, 9:11 AM

#

Nice formatting again

fringe grove Apr 11, 2025, 10:25 AM

#

carmine nacelle Nice formatting again

lmao

#

but why you use light mode???????

#

are you ok?

carmine nacelle Apr 11, 2025, 10:32 AM

#

I've gotten bored of dark mode

fringe grove Apr 11, 2025, 10:33 AM

#

carmine nacelle I've gotten bored of dark mode

you hate life

carmine nacelle Apr 11, 2025, 3:48 PM

#

Cool

#

I think I'm finally ready to implement rights...

#

oof

carmine nacelle Apr 20, 2025, 10:52 PM

#

Small (not) update: I think I've burnt myself out, so there has been very little progress, and probably won't be for a few weeks

carmine nacelle Apr 20, 2025, 10:53 PM

#

carmine nacelle I think I'm finally ready to implement rights...

I've kinda started implementing this, and in my head it should all work out quite well

#

But on an unrelated note, I've ordered an ARM board, which should have UEFI support, so I think I will do an ARM port once I get myself together...

fringe grove Apr 21, 2025, 11:41 AM

#

FakeNitroEmoji~3

#

vibe

carmine nacelle Apr 22, 2025, 4:56 PM

#

I think I'm going to drop Rust

#

Maybe I'll use it for stuff like NVMe

#

drivers

toxic torrent Apr 22, 2025, 4:59 PM

#

https://tenor.com/view/developer-we-have-a-bug-gif-9159002844106963379

Tenor

carmine nacelle Apr 22, 2025, 5:00 PM

#

The issue is that clang doesn't support some architecture I'm considering targeting

toxic torrent Apr 22, 2025, 5:02 PM

#

which

carmine nacelle Apr 22, 2025, 5:03 PM

#

sh4

toxic torrent Apr 22, 2025, 5:03 PM

#

never heard

carmine nacelle Apr 22, 2025, 5:03 PM

#

Dreamcast

toxic torrent Apr 22, 2025, 5:05 PM

#

when ppc

carmine nacelle Apr 22, 2025, 5:06 PM

#

I've looked at it and it gave me MIPS vibes

carmine nacelle Apr 22, 2025, 5:06 PM

#

toxic torrent when ppc

When someone writes a bootloader for it

toxic torrent Apr 22, 2025, 5:06 PM

#

uboot

carmine nacelle Apr 22, 2025, 5:06 PM

#

(someone could be me, but I can't be bothered)

toxic torrent Apr 22, 2025, 5:06 PM

#

aarch64

carmine nacelle Apr 22, 2025, 5:07 PM

#

toxic torrent uboot

But that uses Linux protocol?

toxic torrent Apr 22, 2025, 5:07 PM

#

so?

carmine nacelle Apr 22, 2025, 5:07 PM

#

toxic torrent aarch64

Infy set it's boring trl

#

I will target it

carmine nacelle Apr 24, 2025, 1:45 PM

#

average C++

modest thistle Apr 24, 2025, 1:45 PM

#

lol what is that XD

carmine nacelle Apr 24, 2025, 1:46 PM

#

C++

modest thistle Apr 24, 2025, 1:46 PM

#

why do you even need a ref to a pointer?

carmine nacelle Apr 24, 2025, 1:46 PM

#

who said it was a pointer? trl

#

I mean I am getting a pointer

modest thistle Apr 24, 2025, 1:47 PM

#

oh wait

#

you are getting the value

#

and then getting a pointer to it again

carmine nacelle Apr 24, 2025, 1:47 PM

#

yes

modest thistle Apr 24, 2025, 1:47 PM

#

that's cursed

carmine nacelle Apr 24, 2025, 1:48 PM

#

modest thistle Apr 24, 2025, 1:49 PM

#

the lambda is even more cursed

#

wtf

carmine nacelle Apr 24, 2025, 1:49 PM

#

why

modest thistle Apr 24, 2025, 1:50 PM

#

never saw a lambda like that

carmine nacelle Apr 24, 2025, 1:50 PM

#

modest thistle wtf

No, this is wrong

#

modest thistle Apr 24, 2025, 1:51 PM

#

oh XD

#

why not keep r tho?

carmine nacelle Apr 24, 2025, 1:51 PM

#

(tbh I could just return iterator here)

carmine nacelle Apr 24, 2025, 1:51 PM

#

modest thistle why not keep r tho?

wdym

modest thistle Apr 24, 2025, 1:51 PM

#

like, remove &*

#

isn't it the same?

carmine nacelle Apr 24, 2025, 1:51 PM

#

yeah I could do it

#

tecnically not quite but yes

carmine nacelle Apr 24, 2025, 1:52 PM

#

modest thistle like, remove &*

it makes it a pointer

dense carbon Apr 24, 2025, 2:08 PM

#

carmine nacelle average C++

classic iterator to pointer conversion

carmine nacelle Apr 24, 2025, 2:08 PM

#

(I basically have my own intrusive tree type)

lunar island Apr 24, 2025, 11:04 PM

#

carmine nacelle *

wtf is -><error type> and that auto kernel::proc:... thing

#

thats not valid C++

carmine nacelle Apr 24, 2025, 11:04 PM

#

vscode shenanigans

#

It's just auto

lunar island Apr 24, 2025, 11:05 PM

#

ah the coloring is confusing

fast bolt Apr 25, 2025, 3:40 AM

#

carmine nacelle sh4

That's a little odd arch, XD registers is by far the best part of it

left dew Apr 25, 2025, 7:12 AM

#

inline type hints provided by the language server

#

i agree the color scheme is terrible

carmine nacelle Apr 25, 2025, 11:16 AM

#

Cool, my rights thing is becoming a concurrency nightmare

#

I think I'll be having to hold up to 6 locks at the same time ultrameme

#

(in one function)

lunar island Apr 25, 2025, 11:58 AM

#

Why not just use a bitmap

#

and have a handle table

carmine nacelle Apr 25, 2025, 12:05 PM

#

?

#

I want to allow sending up to 4 rights + reply right with each meesage

#

And the only feasable way to do it that I've come up with is by protecting each right with a lock

#

(Since I want them to do a bunch of stuff)

#

I'm not very clear where I could use bitmap in there

lunar island Apr 25, 2025, 12:06 PM

#

Ah ok nvm

#

Yea I would just do one right per message

#

And one reply

carmine nacelle Apr 25, 2025, 12:07 PM

#

I want at least two

#

I mean reply + right

lunar island Apr 25, 2025, 12:07 PM

#

carmine nacelle And the only feasable way to do it that I've come up with is by protecting each ...

You can just lock the table though

#

No?

carmine nacelle Apr 25, 2025, 12:07 PM

#

The rights are per reciever chanel

#

And tied to the task group on the other end

lunar island Apr 25, 2025, 12:07 PM

#

yeah

carmine nacelle Apr 25, 2025, 12:07 PM

#

So they are not in a global namespace

carmine nacelle Apr 25, 2025, 12:08 PM

#

carmine nacelle I mean reply + right

I also thought about limiting it to these initially, but it also had some issue with concurrency

#

(I don't remember which)

#

And since I'm having to take locks on both of them anyway (to pass ownership from right to a message), I might as well expand it to four

#

Since it would also be useful for drivers, where I can have a reply right, "service right" (e.g. so that the server can communicate with the driver), and some sort of public facing right, so that stuff can communicate with server directly

#

Idk

#

Maybe it's not needed thonk

#

But at least two should be nice

#

Anyway, I think it's going to be a neat system

#

I'm planning to have send once and send many rights, with ability to explicitly revoke them, some sort of notification to the sender if the right disappears, and notification to the reciever if sender closes it as well

#

So it should solve the permission issues and the issue of servers dying unexpectedly and not replying to messages

carmine nacelle Apr 25, 2025, 12:17 PM

#

carmine nacelle And since I'm having to take locks on both of them anyway (to pass ownership fr...

I remembered, I need to check the right I use to send (to avoid sending message twice on a send once right) + the right I am sending (to check for the similar problem), besides the newly created right, so it's still 3 locks

carmine nacelle Apr 25, 2025, 12:19 PM

#

carmine nacelle I think I'll be having to hold up to 6 locks at the same time <:ultrameme:729026...

This in theory should not be a big issue, since it's 'just' 6 rbtree removals inside the lock

#

(at most)

#

(maybe I have too many locks in the kernel)

carmine nacelle Apr 25, 2025, 12:43 PM

#

thonk

#

I think I need to finaly add continuations to the kernel...

#

Or maybe not trl

carmine nacelle Apr 25, 2025, 1:21 PM

#

No, I do absolutely need some queue for them

#

Eventually

carmine nacelle Apr 25, 2025, 8:34 PM

#

New fun problem/design decision, I can send rights, but how do I accept them? thonk

carmine nacelle Apr 27, 2025, 3:04 PM

#

Somehow my rights stuff is working??

carmine nacelle Apr 27, 2025, 9:14 PM

#

I guess now I just need to rewrite everything to use it...

fringe grove Apr 28, 2025, 9:59 AM

#

yippe

#

that sounds like so much fun

carmine nacelle May 3, 2025, 5:04 PM

#

My ARM hardware has arrived...

#

I think I'll steal NVMe drive from my old laptop

carmine nacelle May 3, 2025, 5:39 PM

#

Cool

toxic torrent May 3, 2025, 6:47 PM

#

oh shit

#

that's the rk3588-edk2 right?

#

i have the same for my rock 5b+

carmine nacelle May 3, 2025, 6:54 PM

#

yes

#

so debian had installed itself, but had broken repos, and ubuntu installer is just refusing to boot?

carmine nacelle May 5, 2025, 10:35 PM

#

ok, my os is completely destroyed after the IPC rewrite...

plain jungle May 6, 2025, 6:13 AM

#

what are you changing?

carmine nacelle May 6, 2025, 7:22 AM

#

I'm adding IPC writes

plain jungle May 6, 2025, 9:02 PM

#

IPC writes?

carmine nacelle May 6, 2025, 9:02 PM

#

Autocorrect bruh

carmine nacelle May 6, 2025, 9:02 PM

#

plain jungle IPC writes?

rights*

plain jungle May 6, 2025, 9:02 PM

#

rights in the sense of capabilities?

#

or access control bits?

carmine nacelle May 6, 2025, 9:03 PM

#

Capabilities

#

Something like send rights in Mach

#

(but simpler)

carmine nacelle May 13, 2025, 3:17 PM

#

I think my libc is really falling apart...

plain jungle May 14, 2025, 6:51 AM

#

time to merge your libc into mlibc :^)

carmine nacelle May 14, 2025, 6:53 AM

#

Yeah

#

I've been looking at mlibc recently

#

(though I have exams soon and don't have time to do this now)

#

But how does it handle os-specific libraries and stuff?

carmine nacelle May 14, 2025, 6:54 AM

#

carmine nacelle I've been looking at mlibc recently

Briefly

#

Like since my kernel API is weird and a lot of my stuff goes through IPC

twilit talon May 14, 2025, 7:17 AM

#

carmine nacelle Like since my kernel API is weird and a lot of my stuff goes through IPC

So does managarm

left dew May 14, 2025, 8:08 AM

#

carmine nacelle But how does it handle os-specific libraries and stuff?

not sure what you mean by "os-specific libraries" but you can just do whatever you need to/want to in your sysdep's meson.build file

#

and sysdeps are of course a way for mlibc to call into your kernel to allocate memory, open files or whatever

carmine nacelle May 14, 2025, 8:09 AM

#

twilit talon So does managarm

Yeah, I've seen it, but it has a bunch of stuff in managarm namespace, and I didn't find it

left dew May 14, 2025, 8:09 AM

#

they map pretty closely to libc functions

carmine nacelle May 14, 2025, 8:09 AM

#

(but didn't really search much)

carmine nacelle May 14, 2025, 8:14 AM

#

left dew and sysdeps are of course a way for mlibc to call into your kernel to allocate m...

To open files and stuff, I need a lot of library code + I have a bunch of functions in my library which is not in libc

#

idk how to explain it

left dew May 14, 2025, 8:18 AM

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well, as long as you can link against it from c++ code you should be just fine

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you're gonna have to make it available to meson somehow

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a simple meson.build to build them as a static library should do

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so you can pull it in through a subproject and have it work with meson of course

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again, managarm itself is a good example of how to do it since they rely on libraries from the managarm repo in mlibc

carmine nacelle May 14, 2025, 8:21 AM

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So like it's better to make it a separate library?

left dew May 14, 2025, 8:21 AM

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well, that's what i assumed it was already

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alternatively, if you don't plan on using it outside (m)libc, and you want to replace your libc with mlibc, you can just copy the code into your sysdep directory and use it like that

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i see include/pmos/ has the headers you probably need but i don't know where to find the actual sources lol

carmine nacelle May 14, 2025, 8:27 AM

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lib/libc

left dew May 14, 2025, 8:27 AM

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well, that's libc

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that's not what i was looking for

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but i don't think i need to look at it anyway

carmine nacelle May 14, 2025, 8:56 AM

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I don't have a separate library for it, but I should probably make it be so

toxic torrent May 14, 2025, 9:23 AM

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carmine nacelle To open files and stuff, I need a lot of library code + I have a bunch of functi...

you can put that into your sysdeps

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mlibc can install custom headers as part of the headers_only build target

carmine nacelle May 14, 2025, 9:25 AM

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Maybe I want to have it as a separate library

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if I want to have 2 c libraries for some reason...

toxic torrent May 14, 2025, 9:27 AM

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carmine nacelle Maybe I want to have it as a separate library

then just dylink against it in the build script idk

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though that probably won't work in upstream

plain jungle May 14, 2025, 11:01 AM

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It's also probably worth checking if it makes sense to integrate parts of your libc into mlibc

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There may be areas where your libc is more complete

carmine nacelle May 14, 2025, 11:02 AM

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The issue is that my libc is in pure C

left dew May 14, 2025, 11:03 AM

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doesn't matter

carmine nacelle May 14, 2025, 11:04 AM

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Though yeah, this benefits everyone

left dew May 14, 2025, 11:04 AM

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code can be copied

carmine nacelle May 14, 2025, 11:04 AM

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I'll take a look

left dew May 14, 2025, 11:04 AM

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and adjusted to be c++

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it's not that big of a deal

hexed knot May 14, 2025, 11:04 AM

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or just not adjusted

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C is usually a subset of C++

left dew May 14, 2025, 11:04 AM

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aren't there some things that aren't valid c++ that are valid c?

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i was mainly talking about that

hexed knot May 14, 2025, 11:04 AM

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i said usually

kindred venture May 14, 2025, 11:04 AM

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those are very very minor

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things like implicit void pointer casting

hexed knot May 14, 2025, 11:04 AM

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and yeah very minor edge cases

left dew May 14, 2025, 11:04 AM

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yeah i know, that's why i said it's not a big deal to adjust it

carmine nacelle May 14, 2025, 11:05 AM

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But with C++ you need exception safety and stuff like that

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?

hexed knot May 14, 2025, 11:05 AM

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not really

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especially if you compile with -fno-exceptions

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which mlibc probably does?

left dew May 14, 2025, 11:06 AM

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iirc it does, yeah

plain jungle May 14, 2025, 11:13 AM

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yes

carmine nacelle May 19, 2025, 10:22 AM

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Fun, I'm trying to write nothrow C++ wrappers for my IPC stuff, and it's really obnoxious with stl

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I wonder if I should roll my own vector (again)

carmine nacelle May 19, 2025, 9:01 PM

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I think most of the OS compiles with the new IPC functions?
I just need to fix Rust rust

carmine nacelle May 20, 2025, 5:50 PM

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Somehow this is promising

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By the look of things, this is a blatent nullptr deref?

carmine nacelle May 20, 2025, 6:29 PM

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Somehow it's not in the order that I expected it to be?

twilit talon May 20, 2025, 6:32 PM

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this is ub lol

carmine nacelle May 20, 2025, 6:32 PM

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nah

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it was in the right order

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I was just dereferencing nullptr

twilit talon May 20, 2025, 6:33 PM

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the order of evaluation is undefined here

carmine nacelle May 20, 2025, 6:33 PM

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I though that functions were evaluated from right to left?

twilit talon May 20, 2025, 6:33 PM

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wrong lol

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same reason why a++ + ++a is ub

carmine nacelle May 20, 2025, 6:34 PM

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fun

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Ok, now everything just fails

kindred venture May 20, 2025, 6:48 PM

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carmine nacelle I though that functions were evaluated from right to left?

Almost 0 operators (including function calls) in C/C++ define their evaluation order

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With && and || being the obvious exceptions

hexed acorn May 20, 2025, 7:01 PM

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order of argument evaluation is undefined

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oh i was scrolled up

hexed acorn May 20, 2025, 7:02 PM

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kindred venture With && and || being the obvious exceptions

operator, :^)

carmine nacelle May 21, 2025, 12:22 PM

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I think I'm getting somewhere...

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I'm dumb

carmine nacelle May 21, 2025, 12:56 PM

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ok, both the kernel and userspace are trolling me now

carmine nacelle May 21, 2025, 10:59 PM

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brain damage detected

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Now this is fun...

carmine nacelle May 21, 2025, 11:29 PM

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Now I actually have no words

toxic torrent May 22, 2025, 6:26 AM

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carmine nacelle Now I actually have no words

what

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is not a keyword

carmine nacelle May 22, 2025, 7:25 AM

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It is

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It was supposed to be one not

modest thistle May 22, 2025, 8:59 AM

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toxic torrent is not a keyword

not = !

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same as "and" = &&, "or" = ||

twilit talon May 22, 2025, 9:00 AM

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carmine nacelle Now I actually have no words

me when i write too much python

modest thistle May 22, 2025, 9:00 AM

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it does recognise it tho

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it just negates the negation

twilit talon May 22, 2025, 9:01 AM

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there's a c++ header that adds a macro for not

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for users that dont have ! on their keyboard

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its not an official keyword

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dont use it

modest thistle May 22, 2025, 9:01 AM

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ik and and or do not require any header

twilit talon May 22, 2025, 9:02 AM

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really? thats cool

modest thistle May 22, 2025, 9:04 AM

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unless it's a c23 only feature

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bc rn i am using them with no header

carmine nacelle May 22, 2025, 9:06 AM

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I think it is official C++ https://en.cppreference.com/w/cpp/language/operator_alternative

cpp/language/operator alternative

carmine nacelle May 22, 2025, 12:06 PM

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What if I do a GPU driver?

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thonk

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(I've gotten myself an ARC card)

carmine nacelle May 22, 2025, 1:23 PM

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carmine nacelle Now I actually have no words

Ok, the rights thing is a bit of a hell to debug now nooo

carmine nacelle May 22, 2025, 2:01 PM

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Clang is being dumb...

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Very silly compiler

carmine nacelle May 22, 2025, 3:02 PM

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carmine nacelle Ok, the rights thing is a bit of a hell to debug now <:nooo:750466870993223750>

(actually, maybe I take my words back)

carmine nacelle May 22, 2025, 7:45 PM

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I'm starting to suspect that it might be a deadlock

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(I need a watchdog timer...)

carmine nacelle May 22, 2025, 8:12 PM

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I'm losing my mind

carmine nacelle May 22, 2025, 10:05 PM

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It looks like the userspace is at fault...

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(pointer infestation)

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(I've no idea what's going on)

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The userspace has gone insane

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and the assembly looks sane

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(I think I kinda know what's going on)

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bruh

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Insanity

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(instead of loader_port_name, it should be create_result.right)

carmine nacelle May 23, 2025, 5:37 PM

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After a lot of printfs, I think I have userspace back...

carmine nacelle May 23, 2025, 6:16 PM

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Now I just actually need coroutine abstractions around my IPC nooo

carmine nacelle May 29, 2025, 9:31 PM

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I think that excluding the printf weirdness, my IPC rights thing is fully working?

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this feels like it's readin from heap or something

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(I think I know what's up)

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That were non null terminated strings

carmine nacelle May 29, 2025, 11:21 PM

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thonk maybe I want to get 32 bit risc-v userspace working?

carmine nacelle May 30, 2025, 10:15 AM

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brain damage

carmine nacelle Jun 7, 2025, 9:55 AM

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Ok, the loongarch port is not as dead as I expected

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I think it's a skill issue of my libc...

carmine nacelle Jun 7, 2025, 10:00 AM

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carmine nacelle I think it's a skill issue of my libc...

Yeah

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"But Rust is memory safe"

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Cool, it jumps to 0 in panic

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And I really don't feel like debugging that right now

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I think my printf is not returning the right size

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(that's my suspicion)

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Maybe I should check ia32 build first

carmine nacelle Jun 17, 2025, 8:37 PM

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So, I'm done with studying

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Which means it's time to fix Rust

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And then add more stuff

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I think the top priority would be the init server

carmine nacelle Jun 18, 2025, 8:30 AM

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Cool, Rust is just trolling me

toxic torrent Jun 18, 2025, 10:16 AM

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when is it not xd

carmine nacelle Jun 18, 2025, 11:20 PM

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thonk maybe Rust isn't the issue??

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I think this is a C skill issue

#pmOS - microkernel OS for RISC-V, x86, and LoongArch