pmOS - microkernel OS for RISC-V, x86, and LoongArch | Operating System Development | Page 7

plain jungle Feb 24, 2025, 10:31 PM

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But having the pointer is allowed (see the definition of reinterpret_cast -- there is no requirement around alignment)

hexed knot Feb 24, 2025, 10:31 PM

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okay but having a pointer itself is fine

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yeah

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so its also not UB if you do it via C++

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its also not ub via rust aiui

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still UB to use though

kindred venture Feb 24, 2025, 10:32 PM

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plain jungle But having the pointer is allowed (see the definition of reinterpret_cast -- the...

getting a misaligned pointer via casting another pointer in c is also undefined behavior so C++ is a bit looser there

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but interesting

hexed knot Feb 24, 2025, 10:34 PM

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huh i have found something even more cursed

plain jungle Feb 24, 2025, 10:35 PM

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The wording in the C standard only applies to object ptr to object ptr casts

hexed knot Feb 24, 2025, 10:35 PM

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int x(int* p, int* q) { return (p+100)-q; }
int z() { int a[4]; return x(a, a); }
``` this is UB in C and rust (in rust if you use a normal add() or offset() but not wrapping_add()) but not in C++

plain jungle Feb 24, 2025, 10:35 PM

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int to object is allowed regardless of alignment

hexed knot Feb 24, 2025, 10:36 PM

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afaict

kindred venture Feb 24, 2025, 10:37 PM

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plain jungle But having the pointer is allowed (see the definition of reinterpret_cast -- the...

i found this:

An object pointer can be explicitly converted to an object pointer of a different type.64 When a prvalue v of
object pointer type is converted to the object pointer type “pointer to cv T”, the result is static_cast<cv
T*>(static_cast<cv void*>(v)). [Note: Converting a prvalue of type “pointer to T1” to the type “pointer
to T2” (where T1 and T2 are object types and where the alignment requirements of T2 are no stricter than
those of T1) and back to its original type yields the original pointer value. — end note]
this doesn't explicitly mention it, but the note seems to imply that if T2 is more strictly aligned than T1 the round-trip is not preserved, which would only make sense if getting a misaligned pointer this way is UB/ID

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i wonder if it's more explicitly mentioned anywhere

plain jungle Feb 24, 2025, 10:44 PM

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The note is non-normative

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It refers to this part of static_cast

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If the original pointer value represents the address A of a byte in memory and A does not satisfy the alignment requirement of T, then the resulting pointer value ([basic.compound]) is unspecified.

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The wording in the note is more strict than required by static_cast: it is enough that the object is properly aligned, not that the type's alignment is stricter (though the latter implies the former)

kindred venture Feb 24, 2025, 10:46 PM

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ah ok

plain jungle Feb 24, 2025, 10:46 PM

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But it is correct that non-aligned casts between object pointers are not guaranteed to preserve round trips afaict

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A compiler would be allowed to zero the alignment bits, for example

hexed knot Feb 24, 2025, 10:52 PM

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plain jungle But it is correct that non-aligned casts between object pointers are not guarant...

only if the type is not a struct, i think

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ah maybe not, maybe always

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it can't do that for incomplete types, though

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hmm

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actually what are the semantics on that

plain jungle Feb 24, 2025, 10:54 PM

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No idea

plain jungle Feb 24, 2025, 10:55 PM

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plain jungle A compiler would be allowed to zero the alignment bits, for example

I guess what's more realistic is that if you turn a word ptr into a char ptr and read from it, the compiler is still allowed to generate word sized loads

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due to this provision

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That's probably the intention

hexed knot Feb 24, 2025, 11:05 PM

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yeah 100%

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its probably for the memcpy case specifically, too

carmine nacelle Feb 25, 2025, 2:32 PM

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I think llvm is confused again with my assembly...
movl %eax, %eax

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Is this not correct?

inline uint32_t io_readl(uint32_t *ptr)
{
    uint32_t data;
    asm volatile ("movl %1, %k0" : "=a"(data) : "o"(*ptr) : "memory");
    return data;
}

inline void io_writel(uint32_t *ptr, uint32_t data)
{
    asm volatile("movl %k0, %1" :: "a"(data), "o"(*ptr) : "memory");
}

carmine nacelle Feb 25, 2025, 2:37 PM

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carmine nacelle I think llvm is confused again with my assembly... `movl %eax, %eax`

Nevermind, it does look correct...

toxic torrent Feb 25, 2025, 2:47 PM

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carmine nacelle I think llvm is confused again with my assembly... `movl %eax, %eax`

what about it

carmine nacelle Feb 25, 2025, 2:48 PM

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carmine nacelle Is this not correct? ```C inline uint32_t io_readl(uint32_t *ptr) { uint32_t...

I get a pagefault in this

toxic torrent Feb 25, 2025, 2:50 PM

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check ptr for null meme

carmine nacelle Feb 25, 2025, 3:19 PM

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The thing is it's not null

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Ok I'm dumb

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I'm blaming uACPI's vibes-based types meme

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I was returning wrong thing in uacpi_kernel_pci_device_open

hexed knot Feb 25, 2025, 7:26 PM

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carmine nacelle I'm blaming uACPI's vibes-based types <:meme:575445094589661215>

⚡⚡⚡ vibe driven typing ⚡⚡⚡

carmine nacelle Feb 26, 2025, 12:34 PM

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bruh

carmine nacelle Feb 26, 2025, 5:23 PM

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I've reached long mode waking up from S3

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(took me too long for some reason)

hoary moat Feb 26, 2025, 5:32 PM

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letsgo

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do u register wake vectors?

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or just depend on qemu

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@carmine nacelle

carmine nacelle Feb 26, 2025, 5:43 PM

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wdym

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I've registered it to 0x9e000

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(which is whatever my PMM decided)

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(I'm in a lecture)

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This is what I do (there is a lot of stuff missing)
https://gitlab.com/mishakov/pmos/-/blob/dev/devicesd/generic/acpi/acpi.c?ref_type=heads#L318
https://gitlab.com/mishakov/pmos/-/blob/dev/kernel/arch/x86_64/wakeup_vec.S?ref_type=heads
It reaches jmp _64bitst
@hoary moat

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(like I'm missing all the stuff to save/restore state of things)

hoary moat Feb 26, 2025, 5:54 PM

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carmine nacelle I've registered it to 0x9e000

you do know that you need to register wake gpes, right

carmine nacelle Feb 26, 2025, 5:54 PM

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?

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Run a bunch of aml you mean?

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Probably...

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I need to get back to userspace first

hoary moat Feb 26, 2025, 5:56 PM

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carmine nacelle Run a bunch of aml you mean?

no

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before sleeping you need to register GPEs for wake

carmine nacelle Feb 26, 2025, 5:57 PM

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I haven't done that I think

hoary moat Feb 26, 2025, 5:57 PM

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it won't work on 100% of real hardware

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until you do

carmine nacelle Feb 26, 2025, 5:58 PM

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I'll get to it

carmine nacelle Feb 26, 2025, 10:25 PM

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(I have C++)

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Fun, I'm getting pagefault in ltr

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With error 0x48 bruh

twilit talon Feb 26, 2025, 10:51 PM

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Initializing TSS... FAIL

carmine nacelle Feb 26, 2025, 10:52 PM

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But it makes no sense

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Wtf

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It just doesn't work

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It must be something dumb

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Like I just copy-pasted my smp init code, it can't be broken

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And tss descriptor is FFFF8000208B018E000068

carmine nacelle Feb 26, 2025, 11:18 PM

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Initializing TSS... SUCCESS

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Now I just need to restore (or rather save it correctly) userspace context (since I'm entering S3 from Ring 3), think about SMP bringup (idk how to expose it to userspace, I think I won't? But cpuidle would be nice to support, though idk if that depends on userspace, but I also wanted to have userspace schedulers...), save/restore ACPI NVS (?) memory (this should be another syscall), and write an interface for drivers to suspend/resume (above all I want ns16550 server for logs)

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But like in theory, the kernel should be fully working with one core already

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If I remove the panic

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The difficulty with SMP bring up is my TLB shootdown code, which is just a bit unsound

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Though I should probably also save and restore TSC?

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And lapic timer

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(though it shouldn't matter)

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Yeah, lapic should already be fully working

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For IOAPICs I've decided to add a variable which mirrors them, so it should also be trivial

twilit talon Feb 26, 2025, 11:25 PM

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carmine nacelle Though I should probably also save and restore TSC?

Tsc ticks when in S3 (sometimes trl )

carmine nacelle Feb 26, 2025, 11:25 PM

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bruh

carmine nacelle Feb 26, 2025, 11:25 PM

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twilit talon Tsc ticks when in S3 (sometimes <:trl:829316641191886888> )

If it's invariant?

kindred venture Feb 26, 2025, 11:26 PM

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if it's marked invariant in cpuid it's guaranteed i believe

carmine nacelle Feb 26, 2025, 11:26 PM

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If it's not I don't use it trl

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So nothing to do?

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Cool

kindred venture Feb 26, 2025, 11:26 PM

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sdm says it ticks in all P, C, T states

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idk about S states

carmine nacelle Feb 26, 2025, 11:26 PM

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S is when CPU is off

carmine nacelle Feb 26, 2025, 11:26 PM

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kindred venture sdm says it ticks in all P, C, T states

These are only S0

eager rose Feb 26, 2025, 11:27 PM

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I'm sure I've heard of some separate TSC_CONSTANT or something. maybe that has something to do with it

kindred venture Feb 26, 2025, 11:27 PM

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yeah

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as i said, idk about S

carmine nacelle Feb 26, 2025, 11:27 PM

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The ACPI spec explicitly says (iirc) that S1-5 are different to those 3

eager rose Feb 26, 2025, 11:27 PM

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$$P, C, T \in S0$$?

solemn sageBOT Feb 26, 2025, 11:27 PM

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david

$$P, C, T \in S0$$?

eager rose Feb 26, 2025, 11:29 PM

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kindred venture sdm says it ticks in all P, C, T states

why are there so many states lol? like there are P substates and the S1...5 states, which ought to be enough™️

carmine nacelle Feb 26, 2025, 11:30 PM

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P, C, T are for changing CPU frequency while the system is on

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S1-5 is when the CPU clock is not on

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Idk I've read a nice article about it

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Also there are D states trl

eager rose Feb 26, 2025, 11:31 PM

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yeah lol

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imo we should make a clearer distinction between the machine state (G0, G1[S1...S5] etc.) and CPU power state (C0...Cn)

carmine nacelle Feb 26, 2025, 11:36 PM

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carmine nacelle P, C, T are for changing CPU frequency while the system is on

I think P is for turbo boost, T is for throttling with PWM, and C is various states of CPU sleeping

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Like how much cache is maintained on hlt

carmine nacelle Feb 27, 2025, 10:23 AM

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What if I ported pmOS to aarch64?

plain jungle Feb 27, 2025, 10:25 AM

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does suspend/resume work reliably?

carmine nacelle Feb 27, 2025, 10:27 AM

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Not yet

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I enter the kernel

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But now I need to get to userspace

toxic torrent Feb 27, 2025, 12:27 PM

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carmine nacelle What if I ported pmOS to aarch64?

zased

carmine nacelle Feb 27, 2025, 2:16 PM

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Ok, I've entered userspace/devicesd server (which runs uACPI) but I now have an issue that the stack is destroyed (kinda as expected) and I need something which could do longjmp in kernel

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Explicitly

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And at this point I might just implement callbacks in kernel istead of doing it by userspace thread

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(basically making a good API for it)

left dew Feb 27, 2025, 2:20 PM

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why is the stack destroyed?

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memory content is preserved when you wake up from sleep

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isn't it?

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so the stack should still be there, as long as you know where it is

twilit talon Feb 27, 2025, 2:25 PM

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left dew why is the stack destroyed?

because the cpu stops working in the middle of a function call

left dew Feb 27, 2025, 2:26 PM

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oh, is there no way to like, go back to where it left off?

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unlucky

twilit talon Feb 27, 2025, 2:26 PM

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linux uses an asm stub i think

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to preserve stack

left dew Feb 27, 2025, 2:27 PM

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does it matter? if you just free the stack and take off from a different execution point?

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should the "sleep" function return back to the caller once the system wakes up?

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i guess it depends on the design lol

plain jungle Feb 27, 2025, 2:28 PM

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yeah this seems like a weird problem

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just use a different stack when writing to the sleep vector

twilit talon Feb 27, 2025, 2:29 PM

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or that

left dew Feb 27, 2025, 2:29 PM

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i guess you could have something like

void sleep() {
  event_t wake_event;
  create_thread([](void *arg) {
    event_t *wake_event = (event_t *)arg;
    uacpi_enter_sleep(...);
    // ...
  }, &wake_event);
  wait_for_event(&wake_event);
  // we woke up from sleep !!!
}```

plain jungle Feb 27, 2025, 2:29 PM

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that's also how Managarm's idle task works

left dew Feb 27, 2025, 2:30 PM

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something liek that would be fun

plain jungle Feb 27, 2025, 2:30 PM

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        [[noreturn]] void invoke() override {
            runOnStack([] (Continuation) {
                if(logIdle)
                    infoLogger() << "System is idle" << frg::endlog;
                suspendSelf();
                __builtin_trap();
            }, getCpuData()->idleStack.base());
            __builtin_trap();
        }

left dew Feb 27, 2025, 2:30 PM

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but idk how you'd get from waking up back to after uacpi_enter_sleep

plain jungle Feb 27, 2025, 2:31 PM

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you'd switch to a new stack + record the old stack

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then program the reset vector to essentially return to the old stack

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then write to the sleep register

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I'd still advise against doing the reset vector in usermode

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that seems incredibly broken

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especially since it'll be woken up in kernel mode

left dew Feb 27, 2025, 2:32 PM

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waking up in kernel mode and then resuming the thread that initiated the sleep seems like the best idea

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with my "event" approach you could also just signal the event from kernel mode

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and basically forget about the thread you spun off

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assuming you can properly clean up the resources allocated to it

carmine nacelle Feb 27, 2025, 2:39 PM

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left dew why is the stack destroyed?

https://gitlab.com/mishakov/pmos/-/blob/dev/devicesd/generic/acpi/acpi.c?ref_type=heads#L332
This syscall is when the registers are saved, I walked it with a debugger, it returns correctly to after syscall instruction, and rets to 0, probably because of other function calls

carmine nacelle Feb 27, 2025, 2:41 PM

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left dew waking up in kernel mode and then resuming the thread that initiated the sleep s...

Surprisingly, I had no problems with kernel stacks

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Since I don't store anything on them

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I just enter the kernel as normal, and return to userspace

carmine nacelle Feb 27, 2025, 2:42 PM

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carmine nacelle https://gitlab.com/mishakov/pmos/-/blob/dev/devicesd/generic/acpi/acpi.c?ref_typ...

I guess I could wrap it into asm so return address is saved elsewhere

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(I'm talking about ret in here https://gitlab.com/mishakov/pmos/-/blob/dev/lib/libc/src/arch/x86_64/syscalls_asm.S?ref_type=heads#L49)

carmine nacelle Feb 27, 2025, 2:47 PM

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plain jungle that's also how Managarm's idle task works

My idle task is just like userspace task, but runnning in ring 0

plain jungle Feb 27, 2025, 2:47 PM

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Sounds cursed

carmine nacelle Feb 27, 2025, 2:48 PM

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In a bad way?

plain jungle Feb 27, 2025, 2:49 PM

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But yea my main point is that it's possible to handle the situation that you can get killed at any time (e.g. by suspend or exiting the idle task) even in C (no assembly required)

carmine nacelle Feb 27, 2025, 2:49 PM

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So just kill the thread?

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I'm not understanding

plain jungle Feb 27, 2025, 2:50 PM

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well yes, but make sure it runs on a stack that you can just discard

carmine nacelle Feb 27, 2025, 2:50 PM

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I think I'll just do longjmp meme

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Again, the problem is with userspace stack

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Not the kernel

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I don't like killing threads

carmine nacelle Feb 27, 2025, 3:11 PM

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I think the easiest solution would be to do a raw syscall and save the return address to thread-local variables

plain jungle Feb 27, 2025, 3:39 PM

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if you're writing the registers from the kernel, I don't see how the suspend syscalls differs from any other syscall from userspace's perspective

carmine nacelle Feb 27, 2025, 3:48 PM

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    .text
    .globl syscall_prepare_sleep
    .type syscall_prepare_sleep, @function
syscall_prepare_sleep:
    popq %fs:return_addr@tpoff

    shlq $8, %rdx
    orq $14, %rdx
    xchgq %rdx, %rdi
    xchgq %rsi, %rdx

    movq %rcx, %r10
    syscall

    jmpq *%fs:return_addr@tpoff


    .section .tdata,"awT",@progbits   # TLS data section for initialized thread-local data
    .align 8                         # Ensure proper alignment for a 64-bit variable
return_addr:
    .quad 0

carmine nacelle Feb 27, 2025, 3:50 PM

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plain jungle if you're writing the registers from the kernel, I don't see how the suspend sys...

it doesn't

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Ok, something is trolling me an making syscalls

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(My first uneducated guess would be uACPI)

carmine nacelle Feb 27, 2025, 8:09 PM

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bruh

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(this is getpid basically)

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get_thread_id

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Appartently I've been calling it on mutex lock

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bruh

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Big time bruh

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why

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Which also means slower uACPI score

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I forgor about it

left dew Feb 27, 2025, 8:25 PM

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you should cache getpid/gettid/getppid results

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and of course clear/re-cache them on fork

carmine nacelle Feb 27, 2025, 8:56 PM

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I can just use pthread_self

plain jungle Feb 27, 2025, 9:57 PM

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~~just use mlibc~~

carmine nacelle Feb 27, 2025, 10:00 PM

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Does mlibc support library threads?

plain jungle Feb 27, 2025, 10:03 PM

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what are library threads?

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mlibc supports pthreads, yes

left dew Feb 27, 2025, 10:05 PM

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of course it does

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that god damn thing runs chromium meme

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-# and almost systemd

carmine nacelle Feb 27, 2025, 10:08 PM

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plain jungle what are library threads?

I have a library thread for signals and process management

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So every process has at least two threads

plain jungle Feb 27, 2025, 10:09 PM

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ah

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there's nothing preventing that from working

carmine nacelle Feb 27, 2025, 10:09 PM

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I guess...

carmine nacelle Feb 27, 2025, 10:10 PM

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carmine nacelle Appartently I've been calling it on mutex lock

Ok, this has been ratified. Now I have a problem of pagefaults ultrameme

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(almost as if I actually need a proper abstraction)

twilit talon Feb 27, 2025, 10:13 PM

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left dew that god damn thing runs chromium <:meme:575445094589661215>

Wellll

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Does it tho trl

left dew Feb 27, 2025, 10:13 PM

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yeah it does

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port has bitrotten but it did run

twilit talon Feb 27, 2025, 10:15 PM

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True

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I've seen the screenshot

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Although it mightve been photoshopped trl

carmine nacelle Feb 27, 2025, 10:30 PM

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carmine nacelle Ok, this has been ratified. Now I have a problem of pagefaults <:ultrameme:72902...

I think I have a (terrible) plan

left dew Feb 27, 2025, 10:33 PM

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twilit talon Although it mightve been photoshopped <:trl:829316641191886888>

nah i was there

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it was epic

twilit talon Feb 27, 2025, 10:34 PM

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Damn

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Hopefully we get it back

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Along with kde

plain jungle Feb 27, 2025, 10:37 PM

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afaik KDE apps work

twilit talon Feb 27, 2025, 10:37 PM

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I mean the DE that comes with it

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Kdewin or whatever

plain jungle Feb 27, 2025, 10:39 PM

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ah

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not sure if anybody ever tried that

left dew Feb 27, 2025, 10:40 PM

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we did try gnome

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we got to the screen which says that gnome encountered an error

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not sure if it was gnome session or not

twilit talon Feb 27, 2025, 10:41 PM

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plain jungle not sure if anybody ever tried that

It needs all the session and systemd stuff

left dew Feb 27, 2025, 10:41 PM

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but it did have graphical output

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which is so fucking cool

twilit talon Feb 27, 2025, 10:41 PM

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Nice

left dew Feb 27, 2025, 10:41 PM

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considering all the gobject-introspection we had to go through

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its not very nice stuff

plain jungle Feb 27, 2025, 10:41 PM

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why didn't you merge this though?

twilit talon Feb 27, 2025, 10:41 PM

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How was that worked around again

plain jungle Feb 27, 2025, 10:42 PM

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does somebody still have that code?

left dew Feb 27, 2025, 10:42 PM

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we had this

left dew Feb 27, 2025, 10:42 PM

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plain jungle does somebody still have that code?

dennis, maybe meme

twilit talon Feb 27, 2025, 10:42 PM

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Lol

left dew Feb 27, 2025, 10:42 PM

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it was a while back

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it was really hacky

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like most stuff, but most stuff is also upstreamable

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this absolutely wasn't

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also, hijacking pmos thread lfgg

carmine nacelle Feb 27, 2025, 10:46 PM

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twilit talon It needs all the session and systemd stuff

How does Gnome work on Hurd?

vale hinge Feb 27, 2025, 10:51 PM

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gnu magic

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same way as glibc works on it

left dew Feb 27, 2025, 10:52 PM

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same way as glibc will work on ironclad (🙏)

vale hinge Feb 27, 2025, 10:52 PM

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lol no

dense carbon Feb 28, 2025, 9:36 AM

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twilit talon It needs all the session and systemd stuff

It can get by without

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That's how freebsd etc have the latest gnome and kde

pearl narwhal Feb 28, 2025, 4:15 PM

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no idea about gnome but kde itself has a significant upstream effort for running on BSDs iirc

dense carbon Feb 28, 2025, 5:35 PM

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pearl narwhal no idea about gnome but kde itself has a significant upstream effort for running...

For gnome it's as easy as this

left dew Feb 28, 2025, 5:36 PM

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gobject-inteospection is a bitch though, still

carmine nacelle Feb 28, 2025, 6:18 PM

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Very not nice thing about Rust: it's difficult to compile while on a train

wide spruce Feb 28, 2025, 6:20 PM

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thats what I really like about jinx

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I can just develop it offline once downloaded

lunar island Feb 28, 2025, 6:21 PM

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can't xbstrap not do this

wide spruce Feb 28, 2025, 6:21 PM

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yeah

plain jungle Feb 28, 2025, 6:21 PM

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it can

lunar island Feb 28, 2025, 6:21 PM

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this is more of a cargo thing than anything

wide spruce Feb 28, 2025, 6:22 PM

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me liking something from jinx doesnt mean xbstrap cannot do it too

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xbstrap and jinx are more or less the same thing

lunar island Feb 28, 2025, 6:22 PM

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I mean

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its the equivalent of just

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compiling stuff with deps installed

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lol

wide spruce Feb 28, 2025, 6:22 PM

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true

dense carbon Feb 28, 2025, 6:28 PM

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carmine nacelle Very not nice thing about Rust: it's difficult to compile while on a train

This is why I hate carGo

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Not everyone has the privilege of always on broadband

kindred venture Feb 28, 2025, 6:33 PM

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cargo does have an offline mode

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i haven't used it so i don't know how effective it is though

vale hinge Feb 28, 2025, 6:44 PM

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dense carbon This is why I hate carGo

car go?

hexed acorn Feb 28, 2025, 6:45 PM

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car stop

plain jungle Feb 28, 2025, 6:54 PM

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yeah cargo seems to make the common case easy while not caring about advanced use cases at all

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try to make it apply a patch to a transitive dependency that is imported by your Rust package

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if you want to have some "fun"

carmine nacelle Feb 28, 2025, 6:57 PM

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Ok, qemu is really trolling me (totally not because my code is broken)

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But luckily I'm arriving to a PC which supports S3 and has a COM port (so it's actually 2 PCs trl ) in 20 minutes...

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It wakes up but still says paused, and doesn't want to sleep again...

kindred venture Feb 28, 2025, 6:59 PM

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plain jungle try to make it apply a patch to a transitive dependency that is imported by your...

isn't that pretty easy? just add a [patch] section to the global cargo.toml

carmine nacelle Feb 28, 2025, 7:01 PM

#

Pointing to the patched repo/source

kindred venture Feb 28, 2025, 7:02 PM

#

or even just passing it with --config

plain jungle Feb 28, 2025, 7:02 PM

#

I don't remember the exact issues but IIRC it was not possible to do this reliably within Managarm without overwriting $CARGO_HOME

kindred venture Feb 28, 2025, 7:03 PM

#

is there a reason overwriting CARGO_HOME would be undesirable?

plain jungle Feb 28, 2025, 7:04 PM

#

ah there was also this issue reported by vinc: https://github.com/rust-lang/cargo/issues/9470

GitHub

Cargo update ignores --precise in some cases when using `[patch]` ·...

Problem When [patch]ing a crate foo of version x.y.z (where x.y.z is not the most up-to-date version), running cargo update -p foo --precise x.y.z twice causes foo to be updated to the latest versi...

#

still not fixed after 4 years meme

carmine nacelle Feb 28, 2025, 7:52 PM

#

Fun, the physical PC bootloops..?

left dew Feb 28, 2025, 7:53 PM

#

something tells me... something is broken

#

not sure tho

#

meme

carmine nacelle Feb 28, 2025, 7:53 PM

#

Time for while 1 debugging meme

left dew Feb 28, 2025, 7:53 PM

#

binary search time

carmine nacelle Feb 28, 2025, 7:53 PM

#

This PC decided to place init vector at 0x7000

#

It also can't turn on...

#

like until i unplug it from wall

carmine nacelle Feb 28, 2025, 7:58 PM

#

carmine nacelle Time for while 1 debugging <:meme:575445094589661215>

Ok, while 1 says that it gets to real mode

#

btw this shit is fun meme

left dew Feb 28, 2025, 8:01 PM

#

mov al, 0x69
out 0x80, al```

#

🙏

plain jungle Feb 28, 2025, 8:03 PM

#

what does the manual say for E3?

carmine nacelle Feb 28, 2025, 8:03 PM

#

Idk

carmine nacelle Feb 28, 2025, 8:04 PM

#

left dew ``` mov al, 0x69 out 0x80, al```

This will be the best thing ever if It works

#

Like for debugging

carmine nacelle Feb 28, 2025, 8:26 PM

#

nice

#

@left dew

eager rose Feb 28, 2025, 8:26 PM

#

letsgo

left dew Feb 28, 2025, 8:29 PM

#

lmaooo that's amazing

eager rose Feb 28, 2025, 8:29 PM

#

and incredibly useful

left dew Feb 28, 2025, 8:29 PM

#

i meannn

#

is it?

#

he has serial ;^)

eager rose Feb 28, 2025, 8:29 PM

#

oh

#

yeah right

carmine nacelle Feb 28, 2025, 8:30 PM

#

i have serial in long mode

#

this was printed from real mode

eager rose Feb 28, 2025, 8:30 PM

#

a polling driver (that would work in real mode :^)) is quite simple though

left dew Feb 28, 2025, 8:31 PM

#

yep, you can just poke into 0x3f8 and poll tx ready or whatever

#

its like 5-6 lines of code

#

(assembly)

kindred venture Feb 28, 2025, 8:32 PM

#

serial may not be particularly hard to implement in asm but it's not really suitable as just "insert these one or two easily memorable instructions wherever you want and you now have one byte of output"

#

imo

carmine nacelle Feb 28, 2025, 8:33 PM

#

fine i'll implement serial

#

the problem with this is that it's too fast

#

Bruh this PC's PSU is making really scary noises

left dew Feb 28, 2025, 8:35 PM

#

don't worry

carmine nacelle Feb 28, 2025, 8:35 PM

#

And it's shitty

left dew Feb 28, 2025, 8:35 PM

#

it's not like it will explode or anything

#

right..? meme

carmine nacelle Feb 28, 2025, 8:35 PM

#

left dew it's not like it will explode or anything

It can

#

These PSUs have a history of doing that

#

I think I'll just stick to while 1 binary search

#

For some reason it gets to line 29 and then tripple faults

kindred venture Feb 28, 2025, 8:52 PM

#

i'm having a hard time figuring out why this worked on qemu and bochs in the first place

#

you're converting segments to their actual linear addresses in 16 bit registers

#

that's gonna overflow immediately

#

also when enabling protected mode, the far jump is supposed to be the very first instruction after the write to cr0

carmine nacelle Feb 28, 2025, 8:56 PM

#

Yeah this prints 0x01

#

writes

#

shows

#

idk

carmine nacelle Feb 28, 2025, 8:56 PM

#

kindred venture i'm having a hard time figuring out why this worked on qemu and bochs in the fir...

AMD CPU?

carmine nacelle Feb 28, 2025, 8:56 PM

#

kindred venture that's gonna overflow immediately

Why

#

Segment's values are >> 4

#

They're 16 bit registers

kindred venture Feb 28, 2025, 8:56 PM

#

the segment registers themselves yes

#

but you're converting them into their linear addresses, which are 20-bit values

#

you're essentially discarding the top 4 bits of the seg regs

carmine nacelle Feb 28, 2025, 8:57 PM

#

QEMU does not do that

#

And bochs

kindred venture Feb 28, 2025, 8:57 PM

#

then qemu's emulating incorrectly

#

which i doubt

carmine nacelle Feb 28, 2025, 8:57 PM

#

And bochs?

kindred venture Feb 28, 2025, 8:58 PM

#

bochs too

carmine nacelle Feb 28, 2025, 8:58 PM

#

Like I've walked over it and it was how that worked

kindred venture Feb 28, 2025, 8:58 PM

#

if they're emulating correctly, this will essentially discard the top 4 bits of cs, leaving the truncated linear address in cx

#

same for what you're doing further down

carmine nacelle Feb 28, 2025, 8:59 PM

#

they did not

carmine nacelle Feb 28, 2025, 8:59 PM

#

kindred venture if they're emulating correctly, this will essentially discard the top 4 bits of ...

I don't get it

#

what would be discarded

#

That's why I'm doing two stores

kindred venture Feb 28, 2025, 9:00 PM

#

let's say cs=0x9e00 (aka wakeup vec is at 0x9e000)

bx = cs  # bx = 0x9e00
cx = bx  # cx = 0x9e00
cx <<= 4 # cx = 0xe000

carmine nacelle Feb 28, 2025, 9:01 PM

#

yes

kindred venture Feb 28, 2025, 9:01 PM

#

oh wait you're working around it in a weird way slightly further down

left dew Feb 28, 2025, 9:01 PM

#

carmine nacelle Yeah this prints 0x01

you aren't actually in pm until you do a far jump

carmine nacelle Feb 28, 2025, 9:01 PM

#

wait a second

carmine nacelle Feb 28, 2025, 9:01 PM

#

left dew you aren't actually in pm until you do a far jump

but it tripple faults

#

I need to read AMD manual

#

It must be that

kindred venture Feb 28, 2025, 9:02 PM

#

carmine nacelle but it tripple faults

fyi having any instructions between mov-to-cr0 and ljmp is UB

carmine nacelle Feb 28, 2025, 9:03 PM

#

ok, firmware in combination with limine is trolling me

#

Limine because it refuses to boot randomly and firmware because it refuses to output image randomly

#

Wtf, it doesn't enter ACPI mode now?

#

nvm, this PC just enters S3 too quickly

carmine nacelle Feb 28, 2025, 9:07 PM

#

kindred venture oh wait you're working around it in a weird way slightly further down

I'm thinking about moving this mess to C++ eventually

kindred venture Feb 28, 2025, 9:07 PM

#

like relocating the trampoline in c++ before using it?

#

that seems like a good idea

carmine nacelle Feb 28, 2025, 9:07 PM

#

Yes

#

But there's more insanity

#

#

This stuff is in data trl

kindred venture Feb 28, 2025, 9:08 PM

#

i mean that's fine

#

it's essentially just a template

carmine nacelle Feb 28, 2025, 9:08 PM

#

i think i'm in pmode

#

#

pmos - protected mode Operating System

#

Time for a reddit post

#

anyway

#

(i really need a pxe server)

#

like I've already got openwrt router which can host it...

#

(I'm digressing)

#

This seems promissing

#

(but suboptimal)

#

(I really need SMP trampoline)

#

It could've been really nice if limine had an option for disabling smp...

#

(anyway)

#

Yeah this is failing because it's not bsp

#

more fun stuff

#

I think my PMM is destroyed

#

(i'm blaming cache stuff)

carmine nacelle Feb 28, 2025, 9:51 PM

#

I've no idea what's going on but something is allocating like a million pages

kindred venture Feb 28, 2025, 9:51 PM

#

carmine nacelle It could've been really nice if limine had an option for disabling smp...

wdym?

carmine nacelle Feb 28, 2025, 9:52 PM

#

idk an option for not giving smp reply

#

so it's only one cpu

kindred venture Feb 28, 2025, 9:52 PM

#

just don't have the smp request?

#

limine only starts the aps if you ask for it

carmine nacelle Feb 28, 2025, 9:53 PM

#

No but so I can quickly test without smp without recompiling kernel

kindred venture Feb 28, 2025, 9:53 PM

#

ah

carmine nacelle Feb 28, 2025, 9:55 PM

#

ok, ignoring pmm, it looks like i'm waking up but getting no interrupts

#

This is weird...

carmine nacelle Feb 28, 2025, 10:17 PM

#

I've added volatile to asm (wbinvd) and now it's failing in a different place

#

which should never fail

carmine nacelle Mar 1, 2025, 9:02 AM

#

Ok, I think I'll work on an SMP trampoline

#

Which could also apply to 32 bits

#

And maybe I'll support Hyper on AMD64 builds as well...

carmine nacelle Mar 1, 2025, 12:51 PM

#

Ok, I have CPU parking...

#

I have an idea

#

What if I make drivers explicitly unregister interrupt handlers before sleeping?

#

thonk

left dew Mar 1, 2025, 1:12 PM

#

Parking cpu 3000000

#

Lots of cpus

modest thistle Mar 1, 2025, 1:16 PM

#

3M cpus

#

lol

plain jungle Mar 1, 2025, 2:08 PM

#

carmine nacelle What if I make drivers explicitly unregister interrupt handlers before sleeping?

What is that going to achieve?

carmine nacelle Mar 1, 2025, 2:09 PM

#

left dew Parking cpu 3000000

It's lapic id 3

carmine nacelle Mar 1, 2025, 2:09 PM

#

plain jungle What is that going to achieve?

No missed interrupts

#

Idk

#

I seem to have no interrupts after waking up, for some reason

left dew Mar 1, 2025, 2:10 PM

#

carmine nacelle It's lapic id 3

is this the 32-bit destination from the icr?

#

looks like 3<<24

#

which would make sense actually

plain jungle Mar 1, 2025, 2:10 PM

#

Don't you need to reinitialize devices anyway?

carmine nacelle Mar 1, 2025, 2:25 PM

#

left dew is this the 32-bit destination from the icr?

yes

#

Because I just store it as 32 bit int for x2apic compat

carmine nacelle Mar 1, 2025, 2:25 PM

#

plain jungle Don't you need to reinitialize devices anyway?

You do, but like I keep ioapics and stuff

#

I don't know why, but I've moved relocations to C++ and now my wakeup vector throws #GP when entering protected mode

#

I don't know what I'm missing...

#

check_exception old: 0xffffffff new 0xd
  1300: v=0d e=0018 i=0 cpl=0 IP=9e00:000000000000002a pc=000000000009e02a SP=0000:0000000000000f70 env->regs[R_EAX]=0000000000000000
EAX=00000000 EBX=00009e00 ECX=00000009 EDX=00000001
ESI=00000000 EDI=00000000 EBP=00000000 ESP=00000f70
EIP=0000002a EFL=00000007 [-----PC] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0000 00000000 ffffffff 008f9300 DPL=0 DS16 [-WA]
CS =9e00 0009e000 ffffffff 008f9b00 DPL=0 CS16 [-RA]
SS =0000 00000000 ffffffff 008f9300 DPL=0 DS16 [-WA]
DS =0000 00000000 ffffffff 008f9300 DPL=0 DS16 [-WA]
FS =0000 00000000 ffffffff 008f9300 DPL=0 DS16 [-WA]
GS =0000 00000000 ffffffff 008f9300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT=     0009e0b0 0000001f
IDT=     00000000 000003ff
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
DR6=00000000ffff0ff0 DR7=0000000000000400
CCS=00000005 CCD=00000009 CCO=EFLAGS
EFER=0000000000000000

#

On the far jump intstruction

left dew Mar 1, 2025, 2:28 PM

#

what's selector 0x18?

#

make sure the gdt is accessible and intact

carmine nacelle Mar 1, 2025, 2:32 PM

#

It looks sane

carmine nacelle Mar 1, 2025, 2:32 PM

#

left dew what's selector 0x18?

What I'm trying to load

#

32 bit code

left dew Mar 1, 2025, 2:33 PM

#

well, apparently the gdt is not so sane

carmine nacelle Mar 1, 2025, 3:10 PM

#

I've no idea what was happening

#

I undid everything and did it again and now it works...

carmine nacelle Mar 1, 2025, 3:20 PM

#

plain jungle Don't you need to reinitialize devices anyway?

You do

carmine nacelle Mar 1, 2025, 6:05 PM

#

I think I have SMP?

#

(idk why logs are broken)

#

(after waking up that is)

plain jungle Mar 1, 2025, 6:12 PM

#

carmine nacelle You do

but then a missed irq should be irrelevant anyway, right?

#

you're supposed to shut down + re-init all devices anyway

carmine nacelle Mar 1, 2025, 6:38 PM

#

Yes

#

thonk

#

I'm not getting ACPI interrupts though

#

But I'm getting LVT0 interrupt

carmine nacelle Mar 1, 2025, 6:40 PM

#

carmine nacelle I think I have SMP?

Ok, it's kinda maybe semi-reliable

#

I think I'll fix interrupts

#

Then fix the 32 bit build

#

Then fix RISC-V

#

Then get fix AHCI

#

Then merge to main

carmine nacelle Mar 2, 2025, 11:16 AM

#

Ok, I'm getting tired of S3 stuff

#

It semi-works

#

So I think I'll implement it in i686 build (among with adding SMP support, which it doesn't have now)

#

(Since I think I should kinda be able to just translate it from x86_64 build/trampoline)

#

And then I'll work on adding "handles" to IPC

#

And fixing timers maybe

#

(before writing a proper driver interface for suspend/resume)

#

Also, I still need to fix fork() on RISC-V...

#

(too many things to do)

carmine nacelle Mar 2, 2025, 11:21 AM

#

carmine nacelle And then I'll work on adding "handles" to IPC

Which should help with drivers

twilit talon Mar 2, 2025, 11:28 AM

#

carmine nacelle It semi-works

lol

#

what does that mean

carmine nacelle Mar 2, 2025, 11:36 AM

#

It seems to wake up properly (including SMP), but it's kinda difficult to know since screen nor serial work and other drivers are also broken

carmine nacelle Mar 2, 2025, 11:36 AM

#

carmine nacelle (before writing a proper driver interface for suspend/resume)

Hence this

#

And I'm undermotivated to write this now

plain jungle Mar 2, 2025, 11:37 AM

#

why is fork() arch specific?

#

fork on managarm has zero arch specific code

carmine nacelle Mar 2, 2025, 11:38 AM

#

carmine nacelle It seems to wake up properly (including SMP), but it's kinda difficult to know s...

Bochs does show picture though and the userspace seems to continue to initialize though

carmine nacelle Mar 2, 2025, 11:38 AM

#

plain jungle why is fork() arch specific?

It's not arch-specific, but I have an issue where processes call exit (which is syscall id 0) immediately after forking, and I think I'm messing up the registers somehow

#

on risc-v specifically

#

And I'm using a0 for both passing the syscall id and returning the result

twilit talon Mar 2, 2025, 11:43 AM

#

carmine nacelle It seems to wake up properly (including SMP), but it's kinda difficult to know s...

serial should work after resume just fine

carmine nacelle Mar 2, 2025, 12:09 PM

#

It does, but my userspace driver is broken and only works in QEMU for some reason

twilit talon Mar 2, 2025, 12:10 PM

#

lol

carmine nacelle Mar 2, 2025, 2:23 PM

#

Fun, llvm is trolling me again

#

oof

carmine nacelle Mar 2, 2025, 4:24 PM

#

Average ia32 assembly

#

Ok I need vdso...

#

(What if I implemented dynamic linking?)

#

(ok, I'm getting distracted)

#

Bruh I broke something in i686 builds

#

(ok, I urgently need the symbol table memes trl )

#

(what the fuck)

#

(the best way to debug asserts is to add more asserts galaxybrain )

modest thistle Mar 2, 2025, 5:03 PM

#

XD

carmine nacelle Mar 2, 2025, 5:03 PM

#

Ok, my userspace was dumb and my kernel wasn't cheking it

#

ia32 build works

#

And also Rust just worked

#

(Or did it?)

carmine nacelle Mar 2, 2025, 5:05 PM

#

carmine nacelle And also Rust just worked

Nevermind, Rust is broken

#

It just failed silently

#

On the other hand PS/2 had suddenly decided to work...

#

Ok, I'm dumb

#

It's trying to load x86_64 executable on i386 for some reason

#

Wtf

#

How did that even compile?

modest thistle Mar 2, 2025, 5:09 PM

#

lol what

carmine nacelle Mar 2, 2025, 5:11 PM

#

My Makefiles are trolling me

#

Oh yeah, I forgot I rm -rf *'ed over it

#

This is better

#

Ugh

pearl narwhal Mar 2, 2025, 5:19 PM

#

carmine nacelle This is better

why are you putting an arch triple in your toolchain name lol

#

you can just name it pmos-dev or smth

#

cuz you know toolchains can have multiple targets

pearl narwhal Mar 2, 2025, 5:20 PM

#

pearl narwhal you can just name it pmos-dev or smth

but no idea if rustup will let you do that

#

i don't see why it couldn't, toolchain name is just the name of a directory afaik

carmine nacelle Mar 2, 2025, 5:21 PM

#

pearl narwhal you can just name it pmos-dev or smth

Idk I copied it from osdev wiki

pearl narwhal Mar 2, 2025, 5:21 PM

#

oki

carmine nacelle Mar 2, 2025, 5:21 PM

#

pearl narwhal but no idea if rustup will let you do that

It does

#

Like dev-x86_64-unknown-pmos compiler x86_64, i686 and riscv64gc

#

It's like clang/llvm

#

Which is nice

pearl narwhal Mar 2, 2025, 5:22 PM

#

yep that's the entire idea

carmine nacelle Mar 2, 2025, 5:24 PM

#

Somehow this is what's failing https://gitlab.com/mishakov/pmos/-/blob/dev/rust/pmos/src/ipc.rs?ref_type=heads#L81

#

Which makes no sense

#

This is the C side https://gitlab.com/mishakov/pmos/-/blob/dev/lib/libc/src/generic/syscalls.c?ref_type=heads#L205

#

Oof

#

Ok, it's severely broken

#

This is very sus

#

I'm blaming this

modest thistle Mar 2, 2025, 5:37 PM

#

why?

carmine nacelle Mar 2, 2025, 5:37 PM

#

It just returns int64_t

#

And it's passing it as implicit argument

#

I needed repr transparent

#

Yeah, repr(transparent) worked

#

Ok, time for SMP on i686

carmine nacelle Mar 3, 2025, 12:02 AM

#

Ok, smp kinda almost works in i686 port...

#

(By kinda almost I mean that I have garbage in cr3, and it pagefaults)

#

Initcheck_exception old: 0xffffffff new 0xe
     0: v=0e e=0000 i=0 cpl=0 IP=0008:0000606b pc=0000606b SP=0010:00000000 CR2=0000606b
EAX=80000001 EBX=00000000 ECX=00000000 EDX=00000001
ESI=00000000 EDI=00000000 EBP=00000000 ESP=00000000
EIP=0000606b EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
CS =0008 00000000 ffffffff 00cf9a00 DPL=0 CS32 [-R-]
SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT=     00006098 00000017
IDT=     00000000 0000ffff
CR0=80000011 CR2=0000606b CR3=f000ff53 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
CCS=00000000 CCD=00000001 CCO=LOGICL
EFER=0000000000000000

carmine nacelle Mar 3, 2025, 12:19 AM

#

Ok, I've fixed garbage cr3, but now I have garbage in cr4 galaxybrain

#

classic

#

Ok, I officially have SMP on i686 builds

carmine nacelle Mar 3, 2025, 12:53 AM

#

and it just trippel faults on real hardware nooo

carmine nacelle Mar 3, 2025, 1:23 AM

#

Ok, I'm blaming Ultra

#

It tripple faults on physical hardware, even if I place infinite loop at kernel's entrypoint

#

#

Ok, I'm dumb

#

I forgot I nuked my repo and it was this #1277232930317537341 message

carmine nacelle Mar 3, 2025, 1:32 AM

#

carmine nacelle Ok, I officially have SMP on i686 builds

And it works on physical hardware...

manic girder Mar 3, 2025, 1:38 AM

#

very cool

#

so you support i686, x86_64 and riscv64 now?

carmine nacelle Mar 3, 2025, 1:53 AM

#

Yeah

#

I've had i686 working for some time now, but without SMP

#

I think I'll implement ACPI sleep stuff on it tomorrow

#

(it's almost 3 am bruh )

carmine nacelle Mar 3, 2025, 1:55 AM

#

carmine nacelle I've had i686 working for some time now, but without SMP

I've made a generic function for parking CPUs, so bringing up APs after sleep will use the same code/mechanism as SMP init on first boot

carmine nacelle Mar 3, 2025, 1:57 AM

#

carmine nacelle I've made a generic function for parking CPUs, so bringing up APs after sleep wi...

(which is shared with x86_64)

carmine nacelle Mar 3, 2025, 10:10 AM

#

I think I need multilib support...

plain jungle Mar 3, 2025, 10:10 AM

#

for the kernel?

#

or userspace?

carmine nacelle Mar 3, 2025, 10:19 AM

#

userspace

#

I mean both

#

Idk, so I can compile 32 and 64 bit userspace binaries in one go

#

the kernel already supports compat mode

plain jungle Mar 3, 2025, 10:22 AM

#

why do you want to run 32 bit apps though?

carmine nacelle Mar 3, 2025, 10:23 AM

#

My 32 bit kernel doesn't boot in bochs

#

(because its bios is broken and I haven't figured out how to update it)

#

So that I can debug 32 bit aplications with 64 bit kernel...

#

(I think it's an X Y problem)

carmine nacelle Mar 3, 2025, 10:25 AM

#

plain jungle why do you want to run 32 bit apps though?

Also it's cool

#

Also for convenience

#

I have to recompile libc++ and friends every time I want to target a different architecture

#

(But maybe it's just a bad build system)

plain jungle Mar 3, 2025, 10:28 AM

#

just have different build dirs for different targets

carmine nacelle Mar 3, 2025, 10:29 AM

#

carmine nacelle Idk, so I can compile 32 and 64 bit userspace binaries in one go

By that I mean that I need to figure out how to point lld to $SYSROOT/usr/lib/$ARCH instead of plain $SYSROOT/usr/lib

modest thistle Mar 3, 2025, 10:29 AM

#

can't you just do that with env vars?

hexed knot Mar 3, 2025, 10:29 AM

#

you can probably patch it

#

to teach it about your new /lib location

carmine nacelle Mar 3, 2025, 10:30 AM

#

carmine nacelle By that I mean that I need to figure out how to point lld to `$SYSROOT/usr/lib/$...

But I'm building everything in-source

carmine nacelle Mar 3, 2025, 10:30 AM

#

hexed knot you can probably patch it

I already use patched clang

carmine nacelle Mar 3, 2025, 10:30 AM

#

modest thistle can't you just do that with env vars?

I do that already

carmine nacelle Mar 3, 2025, 10:31 AM

#

carmine nacelle By that I mean that I need to figure out how to point lld to `$SYSROOT/usr/lib/$...

And also compile my libc and stuff 3 times for different architectures

modest thistle Mar 3, 2025, 10:32 AM

#

can't you make a script that copies the bin into the target folder then?

carmine nacelle Mar 3, 2025, 10:32 AM

#

this is not the issue

modest thistle Mar 3, 2025, 10:32 AM

#

why?

carmine nacelle Mar 3, 2025, 10:32 AM

#

like i already do that

modest thistle Mar 3, 2025, 10:33 AM

#

then you should not need to recompile every time

carmine nacelle Mar 3, 2025, 10:37 AM

#

the issue is with libraries

carmine nacelle Mar 3, 2025, 12:32 PM

#

Ugh

#

Ok, time for 1: jmp 1b

#

I'm having a skill issue with this now...

    ljmpl *%cs:(acpi_vec_jump_pmode - acpi_trampoline)
acpi_trampoline_jump_pmode:

#

Fun, ia32 builds are broken in bochs

#

thonk

#

I think framebuffer just isn't working

#

Nope, the whole userspace is broken

#

(but kernel didn't crash)

#

Timers are just broken

carmine nacelle Mar 3, 2025, 3:01 PM

#

my pagefault handling is broken for some reason?

carmine nacelle Mar 3, 2025, 6:59 PM

#

Ok, I have no clue why, but bochs just doesn't wake up

#

And QEMU triple faults

#

With nonsense

twilit talon Mar 3, 2025, 7:02 PM

#

btw triple has one p

carmine nacelle Mar 3, 2025, 7:07 PM

#

I need to get checked for dyslexia

#

I know why it's failing...

#

bruh

#

I crashed qemu

#

Nope

#

The whole WSL2

#

Ok, this looks like kernel address

carmine nacelle Mar 3, 2025, 7:12 PM

#

carmine nacelle I know why it's failing...

I was missing .code16

#

Of course it's this

twilit talon Mar 3, 2025, 7:19 PM

#

are you saying..

#

IDT init... FAIL?

kindred venture Mar 3, 2025, 7:22 PM

#

TSS init... FAIL

carmine nacelle Mar 3, 2025, 7:34 PM

#

busy tss

carmine nacelle Mar 3, 2025, 7:49 PM

#

Bruh

#

TSS init.. SUCCESS

#

But something pagefaulted, which kinda isn't nice I guess

#

#

Even SMP works...

#

Ok, i686 port is officially better that x86_64

carmine nacelle Mar 4, 2025, 10:53 AM

#

What the fuck

toxic torrent Mar 4, 2025, 11:47 AM

#

normal

carmine nacelle Mar 4, 2025, 12:40 PM

#

I'm semi-satisfied with S3 semi-working on x86_64 and i686 (the latter crashes on physical hardware for some reason during pthread creation?), so my plan is to write an ACPI (internal) bus thing in devicesd server, add a driver for RISC-V QEMU thing, and I'll probably merge it to main, before continuing with proper init server/driver management stuff

#

(at which point I'll add an interface for callbacks for sleep/resume)

#

And I'll probably implement IPC handles/permission system/whatever

#

I'm envisioning how the interface could look for Rust/C++ coroutines with IPC

#

(and C I guess)

plain jungle Mar 4, 2025, 2:05 PM

#

What's "RISC-V qemu thing"?

carmine nacelle Mar 4, 2025, 2:11 PM

#

The QEMU device for delivering ACPI events on hardware reduced platforms (ARM, RISC-V, loongarch)

#

The one that @ infy mentioned in uACPI thread a few days ago

carmine nacelle Mar 4, 2025, 8:06 PM

#

bruh

twilit talon Mar 4, 2025, 8:08 PM

#

could be an OOM since u use LTO

carmine nacelle Mar 4, 2025, 8:10 PM

#

Nope

#

Broken assembly

twilit talon Mar 4, 2025, 8:10 PM

#

lol

carmine nacelle Mar 4, 2025, 8:11 PM

#

I'm sure nobody just tested it

#

(since elf tls stuff is a bit fucked)

twilit talon Mar 4, 2025, 8:11 PM

#

what did u do

carmine nacelle Mar 4, 2025, 8:12 PM

#

ntpoff is IA32 thing only apparently

#

On AMD64 tpoff is already negtive

#

Time to test new EC stuff...

#

I've changed its initialization to ACPI bus

#

Fun fact: I think my interrupts are broken on x86_64 in general, not just after waking up

#

i guess my pci driver is severely broken...

#

yep

twilit talon Mar 4, 2025, 8:24 PM

#

vendor cece

carmine nacelle Mar 4, 2025, 8:25 PM

#

Where

twilit talon Mar 4, 2025, 8:25 PM

#

carmine nacelle i guess my pci driver is severely broken...

here lol

carmine nacelle Mar 4, 2025, 8:26 PM

#

Yeah, PCI is reading garbage

twilit talon Mar 4, 2025, 8:26 PM

#

your pci driver is cooked

carmine nacelle Mar 4, 2025, 8:26 PM

#

Maybe I should just hardcode 0x3fc lol

#

It's broken on 3 laptops

twilit talon Mar 4, 2025, 8:27 PM

#

well pci may be accessed during namespace load

carmine nacelle Mar 4, 2025, 8:27 PM

#

(or I could fix ECAM)

twilit talon Mar 4, 2025, 8:27 PM

#

before u are able to access _CRS

#

so yes u have to hardcode it

#

but check linux

carmine nacelle Mar 4, 2025, 8:29 PM

#

Linux's source is unreadable

#

Macro hell

twilit talon Mar 4, 2025, 8:29 PM

#

nah its easy

#

let me look for you

carmine nacelle Mar 4, 2025, 8:29 PM

#

I think they just hardcode it

twilit talon Mar 4, 2025, 8:31 PM

#

https://elixir.bootlin.com/linux/v6.13.5/source/arch/x86/pci/early.c

early.c - arch/x86/pci/early.c - Linux source code v...

Elixir Cross Referencer - source code of Linux v6.13.5: arch/x86/pci/early.c

#

https://elixir.bootlin.com/linux/v6.13.5/source/arch/x86/pci/acpi.c#L494

acpi.c - arch/x86/pci/acpi.c - Linux source code v6....

Elixir Cross Referencer - source code of Linux v6.13.5: arch/x86/pci/acpi.c

#

_CRS is parsed later here, read the comment above ^

carmine nacelle Mar 4, 2025, 8:36 PM

#

So just hardcode it?

twilit talon Mar 4, 2025, 8:37 PM

#

tldr yes

carmine nacelle Mar 4, 2025, 8:54 PM

#

thonk

#

I guess MacBook wants ecam

twilit talon Mar 4, 2025, 8:57 PM

#

does it not work correctly without ecam?

carmine nacelle Mar 4, 2025, 8:58 PM

#

#

What does that even mean?

twilit talon Mar 4, 2025, 9:00 PM

#

this means u returned UACPI_STATUS_NOT_FOUND

carmine nacelle Mar 4, 2025, 9:01 PM

#

twilit talon Mar 4, 2025, 9:02 PM

#

yeah u hit line 295

#

read this comment pls https://github.com/uACPI/uACPI/blob/4ab3a78006a930e2cda5a92f33fc84e1ec6b4a3d/include/uacpi/kernel_api.h#L36

carmine nacelle Mar 4, 2025, 9:04 PM

#

I know about that

#

but

#

I'm doing this

#

It returns any device

twilit talon Mar 4, 2025, 9:05 PM

#

soo how does it fail

carmine nacelle Mar 4, 2025, 9:06 PM

#

I'll add printfs

#

My PCI driver is having a skill issue with finding segment 0

twilit talon Mar 4, 2025, 9:12 PM

#

bruh

carmine nacelle Mar 4, 2025, 9:15 PM

#

wtf

#

how did ecam even work?

#

This has to be something very dumb

#

Wait a second

#

So I have to have PCI before uacpi_namespace_load?

carmine nacelle Mar 4, 2025, 9:21 PM

#

twilit talon https://elixir.bootlin.com/linux/v6.13.5/source/arch/x86/pci/early.c

So before I init PCI, I have to basically provide it for bus 0 through 0xcf8?

#

What the fuck is this? https://elixir.bootlin.com/linux/v6.13.5/source/arch/x86/kernel/cpu/amd.c#L585

twilit talon Mar 4, 2025, 9:27 PM

#

carmine nacelle So before I init PCI, I have to basically provide it for bus 0 through 0xcf8?

Yes

twilit talon Mar 4, 2025, 9:28 PM

#

carmine nacelle What the fuck is this? https://elixir.bootlin.com/linux/v6.13.5/source/arch/x86/...

Lol

carmine nacelle Mar 4, 2025, 9:47 PM

#

fin, my EC driver didn't survive

#

This assembly is funky...

#

(brainrot)

#

(I think my code quality did in fact decrease after disabling copilot)

#

Do MacBooks report lid opening degree/position or something?

twilit talon Mar 4, 2025, 9:57 PM

#

Lol that's interesting

#

Yeah probably

#

Does it send a proper lid notify as well if you close it entirely?

carmine nacelle Mar 4, 2025, 10:00 PM

#

My lenovo laptop seems to also mostly be working

twilit talon Mar 4, 2025, 10:00 PM

#

carmine nacelle Do MacBooks report lid opening degree/position or something?

BTW that AHCI controller info looks bogus

carmine nacelle Mar 4, 2025, 10:00 PM

#

twilit talon BTW that AHCI controller info looks bogus

It is completely bogus because the drivers only support ECAM

#

And the kernel only uses legacy IO

twilit talon Mar 4, 2025, 10:01 PM

#

Oh

carmine nacelle Mar 4, 2025, 10:01 PM

#

Because I'm planning to make PCI accesses an IPC call

#

Since I don't have shared mutexes

#

(too many things to do)

carmine nacelle Mar 4, 2025, 10:02 PM

#

twilit talon Does it send a proper lid notify as well if you close it entirely?

It does

#

I think it has an accelerometer

twilit talon Mar 4, 2025, 10:02 PM

#

carmine nacelle My lenovo laptop seems to also mostly be working

Nice

carmine nacelle Mar 4, 2025, 10:03 PM

#

Time for the QEMU device I guess...

twilit talon Mar 4, 2025, 10:03 PM

#

carmine nacelle I think it has an accelerometer

You can probably read the angle via some method

carmine nacelle Mar 4, 2025, 10:03 PM

#

Like if I just move the laptop it also spams those events

#

Idk why apple would have that

#

It's reasonable for tablets and 2 in 1s

twilit talon Mar 4, 2025, 10:04 PM

#

carmine nacelle My lenovo laptop seems to also mostly be working

BTW why does it fail to publish pci

carmine nacelle Mar 4, 2025, 10:04 PM

#

Idk

twilit talon Mar 4, 2025, 10:04 PM

#

carmine nacelle Idk why apple would have that

No idea

carmine nacelle Mar 4, 2025, 10:04 PM

#

twilit talon BTW why does it fail to publish pci

Rust and C disagreements

twilit talon Mar 4, 2025, 10:05 PM

#

Lol

carmine nacelle Mar 4, 2025, 10:06 PM

#

(I basically have something akin to mbus written in Rust, and it's publishing to there)

#

Also, am I supposed to install devices before uacpi_finalize_gpe_initialization?

twilit talon Mar 4, 2025, 10:08 PM

#

carmine nacelle Also, am I supposed to install devices before uacpi_finalize_gpe_initialization?

Nah

carmine nacelle Mar 4, 2025, 10:09 PM

#

carmine nacelle My lenovo laptop seems to also mostly be working

"EINVAL"

twilit talon Mar 4, 2025, 10:09 PM

#

We talked about this error, its cosmetic

carmine nacelle Mar 4, 2025, 10:09 PM

#

I remember that

twilit talon Mar 4, 2025, 10:09 PM

#

carmine nacelle My lenovo laptop seems to also mostly be working

No ec?

carmine nacelle Mar 4, 2025, 10:09 PM

#

twilit talon No ec?

No, it seems to be fully working

#

Including AMD GPIO

#

Mostly because of that PCI error

twilit talon Mar 4, 2025, 10:10 PM

#

Ah nice, you just didn't include it in the vid

carmine nacelle Mar 4, 2025, 10:11 PM

#

I've basically copy-pasted code from osdev wiki

#

So the internal devices are also using ACPI bus thing now

#

(same with GPIO)

#

Time for the kernel to completely destroy me

#

(I think I'll do it tomorrow)

twilit talon Mar 4, 2025, 10:22 PM

#

carmine nacelle So the internal devices are also using ACPI bus thing now

Nice

toxic torrent Mar 5, 2025, 8:40 AM

#

carmine nacelle Time for the kernel to completely destroy me

troll

carmine nacelle Mar 5, 2025, 1:55 PM

#

fun

toxic torrent Mar 5, 2025, 2:16 PM

#

why i8

carmine nacelle Mar 5, 2025, 2:26 PM

#

Kernel takes uint8_t *

toxic torrent Mar 5, 2025, 2:27 PM

#

as it should

carmine nacelle Mar 5, 2025, 2:29 PM

#

Wait, no, it should be c_char

#

idk, I'm just dumb

#

it's i8 on x86 and u8 on risc-v

#

It's refusing to link for some reason...

#

Do I just do big time stubbing?

hexed knot Mar 5, 2025, 2:33 PM

#

carmine nacelle it's i8 on x86 and u8 on risc-v

yeah

#

you can make rustc use u8 somehow

#

idk how

#

and to make the C abi match you can build with -funsigned-char

carmine nacelle Mar 5, 2025, 2:36 PM

#

I've just set it to libc::c_char trl

#

Kernel shouldn't care anyway

#

But why isn't it optimizing it out like on x86?

#

(I mean there was a flag to allow undefined symbols)

#

trl

hexed knot Mar 5, 2025, 2:50 PM

#

carmine nacelle But why isn't it optimizing it out like on x86?

probably rng?

carmine nacelle Mar 5, 2025, 2:51 PM

#

?

hexed knot Mar 5, 2025, 2:51 PM

#

like it just didnt optimize out

#

because of luck

#

or yeah a compiler flag that made it ignore the errors

carmine nacelle Mar 5, 2025, 2:52 PM

#

But I'm definitely not using opendir and stuff

#

Like it doesn't want it with C++

#

Ok, I need an ARM port to see if it's RISC-V skill issue or not being x86 skill issue

carmine nacelle Mar 6, 2025, 10:57 PM

#

So RISC-V port is alive, and I've fixed ECAM

#

But there is a but

#

for some reason uACPI just quietly fails...

#

What the fuck

#

(I can smell UB and insane optimizations by clang)

#

@twilit talon

#

uACPI returns 7 (UACPI_STATUS_INVALID_ARGUMENT) in uacpi_finalize_gpe_initialization()

#

On RISC-V

#

Imma check x86 build just in case...

carmine nacelle Mar 6, 2025, 11:44 PM

#

carmine nacelle <:trl:829316641191886888>

I think clang compiles libunwind as a shared library

carmine nacelle Mar 6, 2025, 11:49 PM

#

carmine nacelle On RISC-V

And recompiling for x86, it fully works

#

It's not ECAM

#

I'm gonna look at it again tomorrow

twilit talon Mar 7, 2025, 6:57 AM

#

carmine nacelle uACPI returns 7 (UACPI_STATUS_INVALID_ARGUMENT) in uacpi_finalize_gpe_initializa...

There is no gpe on reduced hw

#

That said I should probably make it just return ok in this case

carmine nacelle Mar 7, 2025, 9:28 AM

#

Do I ifndef UACPI_REDUCED_HARDWARE?

twilit talon Mar 7, 2025, 9:36 AM

#

no

#

UACPI_REDUCED_HARDWARE is designed so that u dont have to ifndef anythign

#

u can just call finalize_gpe_initialization

#

I should just mark this as ALWAYS_OK

#

although what's interesting is ACPICA also does this

#

linux just doesnt check the return value

twilit talon Mar 7, 2025, 9:39 AM

#

carmine nacelle Do I ifndef `UACPI_REDUCED_HARDWARE`?

i'd still compile with UACPI_REDUCED_HARDWARE on risc-v

carmine nacelle Mar 7, 2025, 9:40 AM

#

I was calling it before and it was not returning error

twilit talon Mar 7, 2025, 9:40 AM

#

before what

carmine nacelle Mar 7, 2025, 9:42 AM

#

Before updates...

#

Maybe I wasn't noticing it wasn't working though

twilit talon Mar 7, 2025, 9:42 AM

#

yes

#

it cant possibly return OK on risc-v, never has

#

so tldr:

on riscv, compile with UACPI_REDUCED_HARDWARE to strip useless code
either don't call finalize_gpe_initialization on risc-v, or ignore its return value

#

because u cant finalize initialization of something that doesnt exist KEKW

carmine nacelle Mar 7, 2025, 11:05 AM

#

But it shouldn't be invalid argument then (?)

#

UACPI_STATUS_NOT_FOUND meme

#

Ok, Rust also just worked on RISC-V

twilit talon Mar 7, 2025, 11:22 AM

#

carmine nacelle `UACPI_STATUS_NOT_FOUND` <:meme:575445094589661215>

i have COMPILED_OUT

carmine nacelle Mar 7, 2025, 12:17 PM

#

Maybe I'll add aarch64

#

I'm in mood for that

#

Can't be too difficult

twilit talon Mar 7, 2025, 12:18 PM

#

same as risc-v except u have 99999999999 instructions for manipulating caches

carmine nacelle Mar 7, 2025, 12:18 PM

#

(inb4 I get destroyed by non 4K pages)

twilit talon Mar 7, 2025, 12:18 PM

#

it has 4k pages

plain jungle Mar 7, 2025, 12:18 PM

#

aarch64 is quite different from riscv

twilit talon Mar 7, 2025, 12:18 PM

#

it's the hard mode risc-v

carmine nacelle Mar 7, 2025, 12:21 PM

#

Loongarch seems to be similar

carmine nacelle Mar 7, 2025, 12:21 PM

#

carmine nacelle Maybe I'll add aarch64

But also I have arm hardware

#

(Raspberry Pi 4 and 1)

#

And raspberry pi 4 is systemready certified

twilit talon Mar 7, 2025, 12:31 PM

#

it's obviously different from risc-v, but a lot of risc-v code on linux is just adopted cp arm/x.c .

plain jungle Mar 7, 2025, 12:31 PM

#

what parts exactly?

twilit talon Mar 7, 2025, 12:31 PM

#

but all regs and stuff are different ofc

twilit talon Mar 7, 2025, 12:32 PM

#

plain jungle what parts exactly?

most memory related stuff i think

#

idk, ive looked at the port a while ago

twilit talon Mar 7, 2025, 12:34 PM

#

plain jungle what parts exactly?

#

there's a ton more btw

#

this is like 30% of the output

carmine nacelle Mar 7, 2025, 12:35 PM

#

twilit talon it's obviously different from risc-v, but a lot of risc-v code on linux is just ...

This sounds like a Linux devs skill issue

twilit talon Mar 7, 2025, 12:35 PM

#

yeah if u can just straight up copy most stuff maybe it's not abstracted away very well

carmine nacelle Mar 7, 2025, 12:42 PM

#

carmine nacelle (inb4 I get destroyed by non 4K pages)

And weak ordering

carmine nacelle Mar 7, 2025, 1:07 PM

#

(sounds fun)

plain jungle Mar 7, 2025, 1:17 PM

#

It's not only weak ordering but caching in general

plain jungle Mar 7, 2025, 1:45 PM

#

On aarch64 you can't just do unaligned accesses to devices or access mmio through page mappings with default cacheability etc

carmine nacelle Mar 7, 2025, 2:37 PM

#

plain jungle On aarch64 you can't just do unaligned accesses to devices or access mmio throug...

It's the same story on RISC-V

#

But I think that RISC-V's memory ordering is stronger

plain jungle Mar 7, 2025, 2:55 PM

#

on risc-v the firmware is supposed to configure device memory using PMAs

twilit talon Mar 7, 2025, 2:57 PM

#

we all know firmware can be trusted with that trl

plain jungle Mar 7, 2025, 3:04 PM

#

well, this is the same on x86, really

twilit talon Mar 7, 2025, 3:04 PM

#

yes but on x86 at least it generally works

#

on risc-v on the other hand, see limine framebuffer on risc-v

plain jungle Mar 7, 2025, 3:05 PM

#

is that fixed?

#

the limine framebuffer?

twilit talon Mar 7, 2025, 3:05 PM

#

nope

plain jungle Mar 7, 2025, 3:05 PM

#

then you don't know if it's firmware misbehaving or not

twilit talon Mar 7, 2025, 3:05 PM

#

we do because like

#

you can tell it's incorrect caching settings

#

some cache lines get flushed, others dont

#

also i remember someone mentioning u have to manually mess with PMA-related stuff on real boards

#

but maybe it's some other issue shrug

plain jungle Mar 7, 2025, 3:08 PM

#

you can't mess with PMAs on real boards

#

because they're accessible to M mode only

twilit talon Mar 7, 2025, 3:09 PM

#

Maybe I was lied to nooo

plain jungle Mar 7, 2025, 3:09 PM

#

also, if the limine framebuffer thing is caching related, it should be easy to fix, right?

#

just map as uncached

#

didn't somebody try that already?

twilit talon Mar 7, 2025, 3:10 PM

#

No clue, I think Marvin never got around to it

plain jungle Mar 7, 2025, 3:20 PM

#

I can probably take a look at this when i get access to a board with a non-broken uefi

carmine nacelle Mar 8, 2025, 9:46 AM

#

I've decided that I'll finally write an init server, which would listen to pmbus and start the drivers...

#

(among other things)

#

what I'm thinking about is how to store/represent properties, and I think I'll use tree for it, and yaml for config

carmine nacelle Mar 9, 2025, 11:21 AM

#

(the plans have changed)

#

I'm porting to loongarch!

#

It's basically RISC-V...

toxic torrent Mar 9, 2025, 11:54 AM

#

carmine nacelle I'm porting to loongarch!

KEKW

carmine nacelle Mar 9, 2025, 11:55 AM

#

libc is almost compiling

#

https://www.tomshardware.com/news/russia-alt-os-linux-china-loongson-loongarch bruh

Tom's Hardware

Russia pivots to Chinese CPUs that aren't subject to US sanctions —...

First Russian Linux OS ported to LoongArch.

twilit talon Mar 9, 2025, 12:01 PM

#

carmine nacelle https://www.tomshardware.com/news/russia-alt-os-linux-china-loongson-loongarch b...

what does that even mean

#

"ported to loongarch"

#

linux has had a loongarch port since forever

carmine nacelle Mar 9, 2025, 12:02 PM

#

Don't they have their own kernel fork?

twilit talon Mar 9, 2025, 12:02 PM

#

Yes but its called AltLinux

#

like its literally linux

#

with their own local patches for some stuff

carmine nacelle Mar 9, 2025, 12:03 PM

#

Like for elbrus stupidity

twilit talon Mar 9, 2025, 12:03 PM

#

maybe what they meant is that they now have an iso for loongarch

carmine nacelle Mar 9, 2025, 12:03 PM

#

carmine nacelle Like for elbrus stupidity

Closed source gcc patches is just insane

carmine nacelle Mar 9, 2025, 12:03 PM

#

twilit talon maybe what they meant is that they now have an iso for loongarch

I guess, who knows

#

Russian CPU KEKW

twilit talon Mar 9, 2025, 12:04 PM

#

what was nice is they give anyone who wanted it an ssh server with that cpu

#

so u can try it out

#

via telegram or website application

carmine nacelle Mar 9, 2025, 12:05 PM

#

But like how is one supposed to port operating systems to it

twilit talon Mar 9, 2025, 12:05 PM

#

like which? for linux its natively supported

#

windows wont ever run on it

carmine nacelle Mar 9, 2025, 12:06 PM

#

elbrus

twilit talon Mar 9, 2025, 12:06 PM

#

which os i mean

carmine nacelle Mar 9, 2025, 12:06 PM

#

anything that's not linux

twilit talon Mar 9, 2025, 12:06 PM

#

why would they care like

#

its for the goverment

#

which uses linux

#

their own fork that has been verified via various crap

#

static analyzers etc

#

also it supports x86_64 emulation natively

twilit talon Mar 9, 2025, 12:08 PM

#

carmine nacelle anything that's not linux

how many osses are supported by loongarch trl

carmine nacelle Mar 9, 2025, 12:09 PM

#

Well, there will be pmOS and Menix KEKW

#

(how to attract the attention of all 3 letter agencies)

#

LLVM only has Linux KEKW

toxic torrent Mar 9, 2025, 12:52 PM

#

twilit talon what does that even mean

ported a distro

toxic torrent Mar 9, 2025, 12:52 PM

#

carmine nacelle (how to attract the attention of all 3 letter agencies)

chad

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oh shit

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i gotta do the loongarch mlibc port first

carmine nacelle Mar 9, 2025, 12:58 PM

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I've already ported my libc chad

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I'm now porting kernel

pearl narwhal Mar 9, 2025, 1:07 PM

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carmine nacelle LLVM only has Linux <:KEKW:913708372329644042>

loongarch32 is a thing??

carmine nacelle Mar 9, 2025, 1:08 PM

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Yes

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And RISC-V

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I mean I was thinking about eventually supporting 32 bit risc-v userspace with 64 bit kernel

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And I might do the same with loongarch because why not...

pearl narwhal Mar 9, 2025, 1:10 PM

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carmine nacelle And I might do the same with loongarch because why not...

are you doing new world or old world?

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if you do old world you might be able to get WPS Office running lmao

carmine nacelle Mar 9, 2025, 1:11 PM

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?

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I don't get it

pearl narwhal Mar 9, 2025, 1:11 PM

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with some shims and syscall emulation

carmine nacelle Mar 9, 2025, 1:11 PM

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what are you referring to

pearl narwhal Mar 9, 2025, 1:11 PM

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loongarch abis

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there's old world and new world

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pretty much everything open source uses the new world so it's like the sys-v ABI for loongarch

carmine nacelle Mar 9, 2025, 1:12 PM

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what is the difference

carmine nacelle Mar 9, 2025, 1:13 PM

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pearl narwhal pretty much everything open source uses the new world so it's like the sys-v ABI...

I guess I'll also use it

pearl narwhal Mar 9, 2025, 1:13 PM

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carmine nacelle what is the difference

no idea

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but the proprietary OS(es?) made by loongson use the old world ABI

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and the WPS Office joke is that there's a port of WPS Office to old world linux on loongarch

carmine nacelle Mar 9, 2025, 1:17 PM

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New world probably

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Ok, the kernel already compiles (the arch-independent stuff that is)

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I'm just missing paging, interrupts and timers

pearl narwhal Mar 9, 2025, 1:21 PM

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ooo Kylin, Loongnix and UOS are migrating to new world

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so old world will die lol

carmine nacelle Mar 9, 2025, 1:22 PM

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Lol it has a wikipedia entry

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(I mean it's serious)

pearl narwhal Mar 9, 2025, 1:49 PM

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hmm I thought callconvs were different between OW/NW but apparently not

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most of the differences are linux syscalls

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the only differences that should really matter are ELF differences and firmware differences

carmine nacelle Mar 9, 2025, 4:13 PM

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What is the point of this?

toxic torrent Mar 9, 2025, 4:47 PM

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linux code

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typical

lunar island Mar 9, 2025, 4:50 PM

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theres probs an ifdef

twilit talon Mar 9, 2025, 4:53 PM

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carmine nacelle What is the point of this?

If there isnt a define it uses a generic implementation

carmine nacelle Mar 10, 2025, 2:02 PM

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I give up and will probably add framebuffer output to kernel

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For boot logs and panics

carmine nacelle Mar 10, 2025, 2:36 PM

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thonk This is interesting...

carmine nacelle Mar 12, 2025, 12:02 AM

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So, in theory I should have all paging functions

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Now I just gotta figure out the interrupt controllers + add flanterm to kernel

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I guess it's time to resurrect this branch...

toxic torrent Mar 12, 2025, 12:21 PM

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gcon :D

carmine nacelle Mar 12, 2025, 12:22 PM

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?

toxic torrent Mar 12, 2025, 12:39 PM

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why put flanterm in the kernel

kindred venture Mar 12, 2025, 12:45 PM

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to be able to see kernel log messages before userspace is initialized

vale hinge Mar 12, 2025, 12:46 PM

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even Ironclad does that now lol

vale hinge Mar 12, 2025, 12:47 PM

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toxic torrent gcon :D

bold of you to suggest people use a project that was never ported to !Ironclad and you probably never used yourself

wide spruce Mar 12, 2025, 12:47 PM

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yeah we had issues with early initialization on certain machines that required that output for early debug

toxic torrent Mar 12, 2025, 12:47 PM

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guh

wide spruce Mar 12, 2025, 12:48 PM

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we dont have a terminal that userland uses though, its just flanterm as a quick mirror of /dev/console

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the quickest and roughest way to just get some text to screen before gcon hits

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so if uacpi shits the bed, we can know instead of having a black screen on laptops

toxic torrent Mar 12, 2025, 12:48 PM

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i initially wanted to do the same but you raise a good point

wide spruce Mar 12, 2025, 12:49 PM

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like things fail, if it was fool proof I wouldnt have it, but its just such a pain to do bug reports without that

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ive had like 20 people tell me at random moments that Ironclad doesnt boot and they have a black screen

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what do I do

vale hinge Mar 12, 2025, 12:51 PM

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what i meant to say is that there are very valid reasons to want to have text/terminal output from inside a kernel way before userland is initialised

carmine nacelle Mar 12, 2025, 12:51 PM

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toxic torrent why put flanterm in the kernel

loongarch doesn't seem to have a convenient serial controller

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(maybe it does but docs are even more distributed than those of RISC-V)

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Like there's no SBI debug output or 0xe9

hexed knot Mar 12, 2025, 12:52 PM

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you definitely have either pl011 or an 8250

carmine nacelle Mar 12, 2025, 12:52 PM

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But I can't just hardcode it for early debugcon

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Like with x86 ns16550

hexed knot Mar 12, 2025, 12:53 PM

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yes you can

carmine nacelle Mar 12, 2025, 12:53 PM

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carmine nacelle But I can't just hardcode it for early debugcon

(maybe I can)

carmine nacelle Mar 12, 2025, 12:53 PM

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hexed knot yes you can

What's the address?

carmine nacelle Mar 12, 2025, 12:54 PM

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wide spruce ive had like 20 people tell me at random moments that Ironclad doesnt boot and t...

That also happened with pmOS

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How do you handle kernel panics?

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Like my solution is praying that it doesn't on physical HW, but it's not a good one

wide spruce Mar 12, 2025, 12:55 PM

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In terms of what, reporting to the user?

carmine nacelle Mar 12, 2025, 12:55 PM

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Yes

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Like if kernel panics, you can't (easilly) ask userspace terminal driver to print it to the screen

twilit talon Mar 12, 2025, 12:56 PM

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toxic torrent why put flanterm in the kernel

for the kernel terminal? like what linux has

wide spruce Mar 12, 2025, 12:56 PM

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What you can though is take over the framebuffer again and print it yourself

toxic torrent Mar 12, 2025, 12:57 PM

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twilit talon for the kernel terminal? like what linux has

yea but pmos is a microkernel, doesn't that make a difference?

carmine nacelle Mar 12, 2025, 12:57 PM

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wide spruce What you can though is take over the framebuffer again and print it yourself

I've been thinking about that, but what about GPU drivers and such

twilit talon Mar 12, 2025, 12:57 PM

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toxic torrent yea but pmos is a microkernel, doesn't that make a difference?

wellll

kindred venture Mar 12, 2025, 12:57 PM

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wide spruce we dont have a terminal that userland uses though, its just flanterm as a quick ...

hydrogen by default writes the kernel log to one of the boot framebuffers, the init process gets a handle which allows it to 'detach' the kernel log which needs to be done before taking control of the fb

carmine nacelle Mar 12, 2025, 12:57 PM

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carmine nacelle I've been thinking about that, but what about GPU drivers and such

Like there needs to be an interface to notify kernel of their existence

hexed knot Mar 12, 2025, 12:58 PM

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carmine nacelle What's the address?

its in the FDT

wide spruce Mar 12, 2025, 12:58 PM

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carmine nacelle I've been thinking about that, but what about GPU drivers and such

There's no way is the real answer, windows and Linux just die when the graphic driver dies and cannot be recovered

hexed knot Mar 12, 2025, 12:58 PM

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this is how it works on literally all platforms (except kinda not really riscv, and kinda x86)

carmine nacelle Mar 12, 2025, 12:58 PM

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carmine nacelle I've been thinking about that, but what about GPU drivers and such

I've been also thinking about having some sort of panic thread, which can be scheduled even if everything is on fire

wide spruce Mar 12, 2025, 12:58 PM

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kindred venture hydrogen by default writes the kernel log to one of the boot framebuffers, the i...

Ironclad just assumes it can use it if it is not mapped by userland

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If it's mapped by userland we don't use it

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Simple and sweet

carmine nacelle Mar 12, 2025, 1:01 PM

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toxic torrent yea but pmos is a microkernel, doesn't that make a difference?

It's my first "serious" kernel, so a lot of the design decisions might not be the best I guess

wide spruce Mar 12, 2025, 1:01 PM

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As a microkernel you shouldn't panic much

toxic torrent Mar 12, 2025, 1:01 PM

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i mean same

wide spruce Mar 12, 2025, 1:01 PM

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If at all

toxic torrent Mar 12, 2025, 1:02 PM

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i dont know fuckall about what im doing lol

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just asking

carmine nacelle Mar 12, 2025, 1:03 PM

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wide spruce As a microkernel you shouldn't panic much

Yeah, somehow it's stable enough that it doesn't usually panic, but if it does, the system just freezes with no way to know what caused it if you don't have COM port

carmine nacelle Mar 12, 2025, 2:25 PM

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Note to myself and anyone doing loongarch: "If the exception processed is an error-related exception" means machine check exception

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(so the interrupt handling is very similar to RISC-V)

carmine nacelle Mar 12, 2025, 7:13 PM

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Ok, so by the end of the day I'm missing

Page walking
Interrupt controllers
Floating point?
Exceptions

carmine nacelle Mar 12, 2025, 9:53 PM

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Rust is trolling me

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carmine nacelle Mar 13, 2025, 12:22 AM

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Limine is trolling me...

#pmOS - microkernel OS for RISC-V, x86, and LoongArch