#pmOS - microkernel OS for RISC-V, x86, and LoongArch
1 messages · Page 5 of 1
Which then talks to drivers
Via IPC, which is asynchronous
And stores the cache
Idk, it's a bit of a dumb system, I can just put part of it into each driver
to traverse the tree
what if a filesystem starts reading from disk
that's the unfortunate, uncached case
why do you have a vfs cache server?
Because after the filesystem "handle" (I only have IPC ports atm) for a file is resolved from it, the libc then communicates with filesystems directly
that is a weird design
Yeah, but what else can I do
Kernel has no knowledge of filesystems, it's all IPC for it
well, have the vfs server do the talking for you?
you = whoever is trying to open/read/write a file
How would that work?
It would be a message to VFS then a message to filesystem for everything
wdym how? it would just talk to the server responsible for a given file system
yeah that's how, i guess
managarm has some optimizations for that iirc
i think the call that "passthrough lanes"
And I just let processes talk directly to filesystems
how does the process know what file system server to talk to
Also, VFS can disappear and make of the opened files would be closed
It asks VFS cache
It's a bad name
Should be something like namespaces server
yeah, in managarm the open request gives you an ipc lane you talk to to make file requests like read/write/etc
and the ipc on that lane is handled by the fs server responsible for that particular file
I'm kinda thinking about pulling a
move and exposing all ACPI devices to devfs (which I don't have yet)
Sounds like a nice abstraction abstraction
And also maybe adding "namespaces" is a solution to root remounting
Like I would have "dev" namespace, which would get mounted to /dev
And then various servers will then be able to mount their stuff there
This is so good
It can probably just expose AML methods as Unix files
Lazily executing it
A bit of a random thought: why not use "banks" of memory for struct Pages on 32 bit platforms? This way I can support "infinite" RAM with PAE
I hate gcc
How do I make this go away? 
what the hell is this? https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647835.html
misha@Ryzen-PC:~/gcc-pmos/gcc$ cat ./config/linux-android.opt.urls
; Autogenerated by regenerate-opt-urls.py from gcc/config/linux-android.opt and generated HTML
mandroid
UrlSuffix(gcc/GNU_002fLinux-Options.html#index-mandroid)
tno-android-cc
UrlSuffix(gcc/GNU_002fLinux-Options.html#index-tno-android-cc)
tno-android-ld
UrlSuffix(gcc/GNU_002fLinux-Options.html#index-tno-android-ld)
Anyway, I think I'm gonna disappear for two weeks, until I'm finished with the exams
The plan after that is to
- Implement AHCI reading
- Redo VFS mess (although maybe it's not too bad, but C just makes me feel miserable)
- S3 sleep?
- Finish implementing signals
- Implement USB
- Look at GPU stuff
(I wanna see if the whole "ACPI and all drivers in userspace" will survive S3)
also a good patience test
In theory I just need to save and restore all the state
It can't be that hard
Just a few extra callbacks
What about them?
you need them
Idk how they work
you kinda need them for suspend
well you actually only need them for wake
so if you have no problem with not being able to wake properly
that's fine
(if at all)
It would be cool to be support them in general
why pmos is removed from active threads
I have exams
Bump
The build
FDT doesn't do much
And AHCI driver is broken for some reason (because of broken fork)
My
kernel can't save the registers properly so forked processes call exit for some reason immediately after forking
As long as it loads everything it needs via uefi to do anything I guess we will be fine :P
I've tested uboot half a year ago
If it doesn't work now I'll return to it in a week
Place your bets if it still boots
I need to fine two more probes though
nvm one more probe
Does this board have ns16550-style controller?
No
then there will probably be no logs to uart from userspace
framebuffer should still work though
hang on this thing is acting odd
reee
Not sure why but this thing isnt working at all
the board?
Is it not working with pmOS or not working at all?
why you are not in my friends
?
😡
idk
I’ll try again later not sure what’s going on
risc-v
virt machine will work?
windows ❤️
what type of virus did it detect? lol
windows moment
nahhh let him chill
exams are ass
also im giving pmos a star
:)
@carmine nacelle
Then I get thrown out the university
what is ur opinion on me staring the project
u deserve way more stars
dont force urself to work on pmos
work on it WHEN u want to
focus on ur exams
university is crazy scary i would be shitting my pants as well
I'm not working on it atm
good
I'm done with exams so I guess it's time to do that
(and I think I have a month of holidays)

Ok I guess I'm semi-back
I caught a flu (?)
Anyways, I need to think how to implement partition probing and stuff like that
And if I want it to be another server
Which would also expose itself as a filesystem
so the filesystems can then just do open("/dev/sda") or whatever

(because wtf not)
And the network subsystem is gonna be in Go
I'm feeling much better today, so maybe I'll do something
Did I just catch the framebuffer bug in QEMU?
wtf
kernel just decided it doesn't want to work anymore
i'm done
working with kvm but not with tsc is something new
average C++
And fun templates
timers are still broken...

(I think I don't EOI spurious interrupts)
I don't get it
Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI.
one shot
one kill
go to sleep
please
dont be like me
I usually go to sleep at 3 am
You should
I can't sleep 
I was talking more to nyaux, but you should as well
Debugging continues: it looks like I get spurious int as soon as I enter userspace, even if I kill IOAPIC code
fuck kvm
wait whats happening, didnt u have working userspace
My interrupts just casually stop working
like userspace works, but I loose timers and external ints
I think that's also the reason why it was breaking on some physical PCs
like without timer it can't even poll stuff (which I do periodically for all devices
)

Wtf is this code
(for reference)
I'm pointing LAPIC timer to spurious int vector, and wondering why I'm getting that interrupt
great
Nice 2 years old code
What's a better question is why did it only break now
I think the whole timer/clock code has to go...
I'm too fed up with it
(average c++ skill issue)
I guess AHCI is cooking...
(now I just need to think about IPC)
lld 20 is neat
Ok, now that I've slept on it, I think I'll implement sending memory objects
And just do zero-copy disk io
no read() on block devices
(now that I think of it, it should not even be very difficult to implement)
no new syscalls
and somehow, I think the permissions system is building itself
I think I know how to handle multithreaded filesystems
(explanation: currently, my ports are tied to threads, which kinda makes some stuff difficult)
I've been thinking about breaking that up, but didn't come up with anything I liked
But, why not just return sets of ports
And let userspace decide what it wants to do with them
With some scheduler changes, and considering that every process has a worker thread anyway, it can also get notifications from scheduler, and keep track of which core thread is bound to
So in other words, all threads can know which CPU they are on, without making syscalls
And with some caching memes, my libc can just decide where to send messages for each request
(like how did my stupid IPC just work out?)
Wtf declaring overloaded 'operator()' as 'static' is a C++23 extension [-Wc++23-extensions]
how was it only added in c++23?
i was skimming through the code
isn't this magic reversed?
ah nvm the 7f is at the start

this would get loaded by multiboot, load kernel, and continue in ring 3 
bruh
nice c++
i feel like this line of code will be a source of at least one bug
is begin an iterator?
that doesn't make sense nvm
is it some sort of intrusive data structure?
I've just changed std::list-like things of smart pointers (because why not) to intrusive list, removing 2 memory allocations...
anyway, I think I'll finally have AHCI disk reading after I implement sending memory objects
(memory object is my abstraction for in-kernel buffer of pages)
cool, apparently I don't have syscall for creating memory objects...
do I understand it correctly as that you're doing the microkernel equivalent of memfd_create + sendmsg(SCM_RIGHTS)?
also, are your userspace "processes" (or "tasks" or whatever) isolated from each other in memory?
Basically yes
Threads are not, processes are
"tasks" can share or not page tables
so I'm creating a memory buffer, DMAing to it, and sending it to another process
which can then move pages to other files
and there are no memory copies
iirc Linux has a refcounted struct mm_struct, and clone() and whatever other syscalls there are can "unshare" it by setting some flag (CLONE_MM or something). I guess that would be similar in semantics to what you are doing (except afaik Linux only allows "unsharing" the mm_struct at clone or fork (done implicitly) time if some constraints apply)
I have done very little linux userspace development so idk
I guess
well linux userspace usually doesn't touch clone() that much itself. and basically never does weird CLONE_MM shit unless it is doing something unusual
ok actually it is CLONE_VM
I'm also trying to implement posix api on top of what I have I guess
afaik linux clone3 isn't posix
generally linux isn't posix
... and that is a good thing
so userspace doesn't have to touch my api if it doesn't want to
question, wouldn't an infinite loop in one of the servers cause one cpu to be at 100% at all times?
or is that intended
My IPC blocks on reads from empty queues
If it's a bug, it would
i'm looking at processd atm
It does get_message or whatever (I don't remember), and it should block
what's up with it?
it's missing a "n"

typo
@carmine nacelle https://github.com/ThatMishakov/pmOS/blob/main/devicesd/generic/acpi/acpi.c#L257
you should be disabling interrupts here
How do I disable them?
cli
This is userspace
Ok, I think I'll finally implement sending memory objects
I need to decide how to do that...
Did I just discover why it would break sometimes?
I think it's trolling me
(wtf)
it has to be something dumb
Variable just magically becomes 3...
bruh c++ moment
ok, surprisingly sending memory objects was very easy (ignoring the debugging/discovery of unrelated issue)
Time to figure out how to build a disk image with make
(I'm gonna stop polluting uACPI thread)
This looks credible...
I think it's working, now I just need to figure out how to mount filesystems
Like how do I do fstab or whatever
Cool, the dev branch is juicy...
What if I just merge it?
(I think I urgently need execlp...)
and to fix fork on ia32 and risc-v
which means that I need to fix vfs (even though it isn't really broken...)
(by which I mean that I need to write a good hash map header)
and "improve the code quality"
but I want to do USB...
Maybe pmOS will finally have shell in 2026...
I think it's very reasonable to just put that in blockd
which will talk to devicesd
which will talk to vfsd
which will talk to bootstrapd
which will talk to filesystems drivers
but maybe I want fat32 driver be written in Rust...
o/
are your filesystem drivers separate servers or are they libraries attached to vfsd or blockd or whatever
error: unknown type name '__uint128_t' 
ah yes that doesn't exist on i686
or the m68k
kinda sad, I just coped by using uint64_t instead
in the one place I used 128-bit integers
iirc I do something cursed by measuring the frequency, then first multiplying by like a million or something, then dividing by the frequency, followed by multiplying by 1000 again
though idr if this was for TSC or HPET
ld.lld: error: undefined symbol: __udivdi3 

I think I'll finally have to add memory region stuff to my PMM
Since ia32 wants cr3 in < 4GB
It should be doable...
I just don't know how to deal with it
Like do I always allocate from > 4GB and then go to < 4GB if that fails?
hm
wait, does that mean on x86 you cannot physically have more than 1048576 processes ever?
?
in ia32
you can probably recycle page tables..
32 bit x86
Idk
Yeah
I'll probably limit kernel to 16GB of RAM or something anyway
because of struct page
PDPT is 32 bytes, and not required to be page aligned...
what
how is this 32 bytes
4 entries of 8 bytes?
ah i didn't read the middle block
I'm too dumb for this
Software can transition between 32-bit paging and PAE paging by changing the value of CR4.PAE with MOV to CR4.
Wouldn't it pagefault?
AMD manual says this
Implicit Invalidations. The following operations cause the entire TLB to be invalidated, including
global pages:
• Modifying the CR0.PG bit (paging enable).
• Modifying the CR4.PAE bit (physical-address extensions), the CR4.PSE bit (page-size
extensions), or the CR4.PGE bit (page-global enable).
Cool, it looks like libclang_rt.builtins-i386 is sane and doesn't emit xmm for that

c0102e9c: c7 44 24 4c 00 00 00 00 movl $0x0, 0x4c(%esp)
; long_string_str long_string = {0, 0};
c0102ea4: 8d 74 24 50 leal 0x50(%esp), %esi
c0102ea8: c7 44 24 50 00 00 00 00 movl $0x0, 0x50(%esp)
c0102eb0: c7 44 24 54 00 00 00 00 movl $0x0, 0x54(%esp)
; void *operator new[](size_t size) { return malloc(size); }
c0102eb8: b9 0a 00 00 00 movl $0xa, %ecx
c0102ebd: e8 7e 85 00 00 calll 0xc010b440 <malloc>
; long_string.ptr = new char[length + 1];
c0102ec2: 89 44 24 54 movl %eax, 0x54(%esp)
; serial_logger.printf("%s %i\n", bootstrap.c_str(), bootstrap.length());
c0102ec6: 6a 00 pushl $0x0
c0102ec8: 56 pushl %esi
c0102ec9: 68 1c e3 11 c0 pushl $0xc011e31c # imm = 0xC011E31C
c0102ece: 68 44 17 12 c0 pushl $0xc0121744 # imm = 0xC0121744
c0102ed3: e8 c8 82 00 00 calll 0xc010b1a0 <_ZN6Logger6printfEPKcz>
I'm smelling UB
Or stupid code
(for some reason, the kernel is having a skill issue with printf...)
wild guess: since afaik you're porting to 32-bit, it might be having skill issues with int64_t and uint64_t values. assuming you don't mean something like page faults occuring in vsnprintf.
I've had issues with that in allocators because of __builtin_clzl/__builtin_clzll
But it doesn't look like it
It loads 0 from vtable of a global class
for some reason...
and calls a null pointer
Is it the same dumb problem that I've had about a month ago?
I think it's stack overflow 


Fun, it's almost working...
Now I just need to write all the boring assembly to handle interrupts...
(and I also want to support PAE next)
(which implies adding zoned to my pmm)
But after thinking about it, it should be quite easy with my design
And I also need to figure out SMP bringup...
Because I want it to support 16GB of RAM with 32 bits
that's enough
that 4KiB stack must be having lots of fun
I kinda have userspace (now I just need PF handler and memes
)
apparently hardware task switching is not that bad...
printing registers in decimal is diabolical

completetly diabolical
Anyway, maybe I will have it fully working by the end of today?
(the same thing I said on Sunday)
New least overcomplicated save_registers function
```x86asm
.type save_registers, @function
save_registers:
pushl %eax
movw $0x1b, %ax
cmpw 8(%esp), %ax
jne 1f
movw $0x38, %ax
movl %ax, %gs
movl %gs:16, %eax
popl (%eax)
movl %ebx, 4(%eax)
movl %ecx, 8(%eax)
movl %edx, 12(%eax)
movl %esi, 16(%eax)
movl %edi, 20(%eax)
movl %ebp, 24(%eax)
movl 8(%esp), %ecx # %eip
movl 16(%esp), %edx # eflags
movl %ecx, 32(%eax)
movl %edx, 36(%eax)
movl 20(%esp), %ecx # esp
movl 4(%esp), %edx # error code
movl %ecx, 28(%esp)
xorl %ecx, %ecx
movl %ecx, 52(%eax)
xorl %eax, %eax
ret
1:
movw $0x70, %ax
cmpw 8(%esp), %ax
jne 1f
movl %gs:16, %eax
popl (%eax)
movl %ebx, 4(%eax)
movl %ecx, 8(%eax)
movl %edx, 12(%eax)
movl %esi, 16(%eax)
movl %edi, 20(%eax)
movl %ebp, 24(%eax)
popl %ecx
popl %edx
addl $4, %esp
popl 32(%eax)
addl $4, %esp
popl 36(%eax)
movl %esp, 28(%eax)
movl %gs:4, %esp
pushl %ecx
movl $4, %ecx
movl %ecx, 52(%eax)
xorl %eax, %eax
ret
1:
xchgl %ecx, 4(%esp)
xchgl %ecx, (%esp)
pushl %edx
pushl %ebx
pushl %ebp
pushl %esi
pushl %edi
movl %esp, %eax
movl 28(%esp), %edx
jmp *%ecx
honestly I should just ask some osdevers in here to hand-"optimize" some assembly routines... then have it as a CTF reversing challenge
wtf is j *%ecx
ig that was intended to be jmp?
definitely
i'm just saying "wtf is this" 
because it's definitely not a valid mnemonic
yeah it was supposed to be jmp
It kinda worked after an hour of debugging 
Now SSE gives me #UD instead of #NM for some reason 
even though cr0 = 0xe000001b
(which is CR0.MP and CR0.TS set and CR0.EM cleared)
since it's j on risc-v
Nvm, it does
QEMU log was just showing 6 instead of 7 for some reason...
Cool, now it works in bochs but breaks in qemu...
And in bochs it's returning ECONNREFUSED
because why wouldn't it I guess
Bruh clang's -O3 -flto assembly is weird...
Cool, it's trying to load userspace stuff (the errors are expected since it's 64 bit binaries because I can't be bothered to fix the build scripts...)
And it #GPs in SSE instruction in QEMU for no reason
(I think)
(I don't have GP handler...)
(I'm blaming getCR4() function)
Yep
c0105766: 0f 20 e0 movl %cr4, %eax
; cr4 |= (0x01 << 10); // CR4.OSXMMEXCPT (enable #XF exception)
c0105769: 89 c1 movl %eax, %ecx
c010576b: 81 c9 00 06 00 00 orl $0x600, %ecx # imm = 0x600
; inline void setCR4(unsigned long val) { asm("movl %0, %%cr4" : : "r"(val)); }
c0105771: 0f 22 e1 movl %ecx, %cr4
; if (xsave_supported) {
c0105774: 80 3d f8 4e 13 c0 01 cmpb $0x1, -0x3fecb108
c010577b: 75 14 jne 0xc0105791 <kmain+0x3611>
; setCR4(getCR4() | CR4_OSXSAVE);
c010577d: 0d 00 00 04 00 orl $0x40000, %eax # imm = 0x40000
; inline void setCR4(unsigned long val) { asm("movl %0, %%cr4" : : "r"(val)); }
c0105782: 0f 22 e0 movl %eax, %cr4
void enable_sse()
{
auto cr0 = getCR0();
cr0 &= ~(0x01UL << 2); // CR0.EM
cr0 |= (0x01 << 1); // CR0.MP
cr0 |= (0x01 << 3); // CR0.TS (Lazy task switching)
setCR0(cr0);
auto cr4 = getCR4();
cr4 |= (0x01 << 9); // CR4.OSFXSR (enable FXSAVE/FXRSTOR)
cr4 |= (0x01 << 10); // CR4.OSXMMEXCPT (enable #XF exception)
setCR4(cr4);
if (xsave_supported) {
setCR4(getCR4() | CR4_OSXSAVE);
set_xcr(0, xcr0);
}
}
(that was it, qemu also works now)
Userspace kinda works more, but framebuffer driver is crashing...
Letsgo
(something's passing nullptr to flanterm_write 💀)
(if I can read the assembly)
Or not
which makes no sense
I think my registers saving/restoring is broken
I can't get bochs to boot 
Could hyper be pagefaulting?
It boots fine in QEMU
@twilit talon ?
This is pagefaulting with kernel address..?
Nope
I'm dumb
uint64_t's are haunting me
It's crashing in strlen...

(I think I know what's killing the framebuffer/hanging the system)
it's i8042
(I don't have timers...)
why are u doing bochs btw
?
it's qemu
idk bochs debugger is convenient to me
when there are a lot of context switches and gdb can't keep up
It just freezes on inb
qemu that is
ah
bruh i'm dumb it was tripple faulting
and this pagefault is very concerning
(it looks like something has destroyed the stack after the syscall)

I've asked ChatGPT and it did it for me lol
And it even seems to work

Anyway, the only things that's broken is ACPI (should be trivial to reimplement) and that weird pagefault
(and maybe fork)
(since it was broken for no reason with 64 bit kernel)
and then I want to implement zones in pmm
(which will be also beneficial for 64 bit memes)
and PAE because I like to suffer
(though I don't expect to)
oh, and SMP
I need to investigate how to load the trampoline
I will probably add an under 1MB zone to PMM
Which I'll also eventually use for ISA DMA 
And try to make it relocatable
Fun, I'm not getting lapic interrupts for some reason...
(definitely a qemu bug)

I didn't know IF was respected by ring 3
Now we're talking...
bruh it's pagefaulting in movl %gs:0x0, %edi
somehow everything is working
(except interrupts
)
but that's the kernel skill issue
The kernel is trolling me
It #GPs on keybord interrupt then pagefaults on ACPI interrupt

And it pagefaults inside malloc 
that pagefault might be normal though
I wonder if that #GP is unrelated to interrupts 
It's sus that it's in framebuffer's driver
through the magic of printf, I've deduced that that pagefault was indeed normal, but now I get gpf 
This is kinda weird... 
(Or maybe not, if I have a memory leak, for example...)
Or an interrupt storm
Now all userspace just pagefaults when I press the power button
why would it page fault and not just panic(OOM)?
Idk
Maybe it can't allocate memory
(I'm in a long trip and have drained my laptop's battery so I can't debug untill I get home
)
I have a charger but it's 33W so it charges by 1% every 5 minutes or so
(maybe faster, but still very slow)
i mean it's not utilized so of course it's clocked lower than usual
that's how laptops work
oh it looks like it is
16% lol
mine does that too if i don't do anything, but that's probably becuase i dont have some ultra performance thing enabled or whatever
Anyway, I was calling call instead of jmp in interrupt handlers, which was shifting stack, and passing stack address instead of the interrupt number, which was confusing the kernel and causing interrupt storm
though the PS/2 controller still spams interrupts for some reason
(broken timer infrastructure?)
(I poll PS/2 devices every few seconds to check that they were not disconnected or died)
And uACPI has successfully shut down QEMU!
Yep, timers are broken, but spamming is not because of that
(and that's also why uACPI was bugged (probably))
(or maybe it's actually not)
I think it's PS/2 mouse...
Yep, timers just like to die from time to time...
I think it's time to move IOAPIC to the kernel...
Also I have a fucked thought
What if I make the kernel preemptive by timers
But just not reschedule inside them
Though I don't know how to notify the lower priority levels
Also, I think I know why the RISC-V port is calling exit(0) on fork 
I'm having skill issue passing arguments from asm to C
push arguments in reverse order, don't forget to pop them at the end
also something something stack alignment
32 bit is weird
how in the world have you even managed to do IOAPIC in userspace??
As usual?
It was taking 2 uint64_ts and I've been pushing 2 longs instead + I've had some other skill issues with using addl instead of subl for alignment
Just mapped them into the devices server
(it also does interrupts allocation at the moment)
(and had hpet driver)
though I just use lapic now
why
idk. it's just an unusual way of doing things
your microkernel is like a scheduler, ipc, and a trimmed-down memory manager
it's a fat memory manager
but that's like the whole point?
yeah
but like
allocating interrupt lines in userspace, sure. I can buy that.
but actually writing to APIC registers and stuff, that's just... a bit far, maybe
LAPIC is in kernel
though it kinda creates problems
since I don't know what to do with interrupts masking now
I guess kernel could ask userspace, but that seems weird
What if all userspace dies and kernel gets stormed by interrupts
(also, I've put plic into kernel with risc-v memes)
bruh I like how f'ed it's getting
kernel is becoming nonpreemptive with a little * that it actually is
(I just need to change amd64 and risc-v ports
)
lol
eventually
anyway, that was how I wanted to do copy-to-user anyway
(by allowing the kernel to pagefault in itself)
it's working in i686 port now (except the actual copy-to-user impl)
I have a feeling that fork's CoW is returning garbage instead of copying pages for some reason
But i've fixed a long-standing issue (caused by myself, but that's besides the point) where the newly allocated top level pages were not shared across the processes
Now I just let the kernel only map the new top level ptes in the global/idle page table, and copy it to the other ones, on demand, in pagefaults anywhere inside the kernel, if they were not copied during the task creation
also I don't like how flanterm has stopped #GPing
I guess I'll have to wait for another few months for it to surface again
The kernel is being casually weird
It's deducing that the page is only mapped once after fork
which sounds fishy...
Yep the kernel is being weird
or my printf is broken
somehow the pages teleport from one page table to the other one

magic
I think I'm going to sleep 
(I slept for 5 hours today, and I think I'm too energetic (considering that I've taken 2 (or maybe 3) cups of coffee, when I usually don't drink any))
(what the fuck is this code)
(32 bit addr mask is ~0xfff)
cool, kernel decided to pagefault, why not
(while taking a spinlock)
oh yeah that was me
ok I'm hoping the oberrow curse goes away in the morning
my paging code was the thing that was never crashing
but uint64_ts are haunting me now
oberrow curse never goes away
sorry you have to find out this way
cleansing negative energy from pmOS kernel
I've heard if you smoke crack before starting osdev, bugs go away (this is a joke, don't smoke crack)
I'll just change the vscode theme to light so they burn
(I think it's just stack overflowing)
(I really need stack guard pages)
(especially since I have a good vmm which could actually trivially let me do that)
This printf stuff is sus
Why is is copying all of them if it was only told to copy 1 page? 
(there is no such thing as too many printfs)
more wtf code
Cool it seems to be working
(the fork that is)
Now it just fails to map the memory object when reading the AHCI disk (probably uint64_t's striking again)
No, it's size_t instead of uint64_t

Cool, I guess AHCI also works now
Also, somehow the i686 port feels very fast
(I think it's because of the temp mappings)
I wonder how it would perform if I redo the read from user function...

I wanted to do ifunc memes, but I still need to figure out ELF relocations...
So I guess I'll do the fast copy from user memes
I'm having weird issue with clang
Which pops arguments from stack
(it feels like clang is using stdcall instead of cdecl for some reason, or I'm stupid and can't write assembly)
anyway, I've changed addl $24, %esp to leal -16(%ebp), %esp since I don't trust clang (aka I don't know my tooling) and it seems to be working...
Though I am getting a suspicious ```
/home/misha/pmos/kernel/arch/i686/paging/user_access.cc:5:28: warning: 'user_access_page_fault' has C-linkage specified, but returns incomplete type 'ReturnStr<bool>' which could be incompatible with C [-Wreturn-type-c-linkage]
5 | extern "C" ReturnStr<bool> user_access_page_fault(unsigned access, const char *faulting_addr,
| ^
1 warning generated.
and it's tripple faulting with kvm 
I think this is working too well, so I'll do the same on x86_64 
pmos playing portal 2 when
When I get a disk driver and a shell
(although well, AHCI kinda works (it pagefaults on phys hardware))
(the way I've been handling interrupts before was a tiny bit insane)
Now I just save nested interrupt registers on stack...
And I suspect I know why the framebuffer was casually breaking
I'm having a skill issue with GDT 
(something is destroying the return frame, gdt works as normal (it seems))

I wonder...
if this is what could be breaking the framebuffer...
(ok, I urgently need watchdog memes)
I've been thinking about this all day, and I haven't come up with something that I like...
I think I'll just create a general, and below 4G zone, and a reserved below 1MB zone for now, and that's it
Oof, PAE is not working well...
bruh, auto is trolling me
Ok I have absolutely no clue of what the fuck is happening
pmm just pretends that addresses above 4GB don't exist, even though they clearly do
then some fuckery happens
and then the memory read by uacpi becomes corrupt
or maybe it isn't?
wtf
all I did was enabling PAE
How nice
(the only nice thing is that it's consistent...)

(32 bit ints are really haunting me
)
This is insanity
How does it even get demoted to int from unsigned long long?
The kernel has really gone rogue...
(that looks like ascii)
Could it be a seabios skill issue?
I want to try something...
bruh I think hyper just tripple faults, with no image
removing -O3 and lto makes it fail to boot...
bro how🙏
linux reference
not even my OS dared to do that
altho when my APIC implementation was wrong the keyboard only worked on -O3
then i discovered i did not setup the redirect tables
It (-O3) optimized a bunch of stuff away, which was broken because I was missing constinit in pmm, and my pmm is initialized before I call global constrictors
Now it crashes in different place
(all registers get ASCII in them, and then the kernel pagefaults)
bruh it returns to a bogus address, ebp also points to shit, and I have no idea how to debug that
Idk why, but if feels like I'm using wrong calling convention
The issue was ratified, and it almost behaves exactly the same 
(except that the kernel also pagefaults now)
I suspect I know what's going on...
I wonder if this could be an issue with tlb...
*TLS (?)
No
Translation Lookaside Buffer
I think it never gets invalidated somehow
like flanterm works, and it uses the same functions, so phys mappings have to be correct...
Yep, I've compared the logs, and it's not flushing the tlb properly
It was a dumb mistake in page invalidation loop
(the only issue now is that AHCI driver pagefaults...)
ok, PAE kinda seems to be fully working...
(I just need to fix PMM ignoring physical memory limit)
what was the bug?
it was not invalidating tlb
bruh
between mmap and munmap
I've set it to 16GB 
It also can allocate memory below 4GB now, on 64 bit arches as well
For legacy devices DMA
Actually nevermind...
(if someone wants to try it
)
The only thing missing is NX (which is also unsupported on x86_64 port)
but works on RISC-V, so it should mostly be working...
I mean be easy to implement...

What's weird is that PAE is supposedly disabled yet it's still doing that
ok, I think I need a PXE server...
it should have been assert(page->allocated_count <= 14) 
Cool, ignoring the fact that AHCI driver explodes (probably after seeing 6TB drive), it fully works!
how do these work?
Magic
Ok, since my holidays end this week, I think I'll just fix the x86_64 and RISC-V ports and merge the ia32 port without SMP
(though I still need to investigate it not working on the Sony laptop...)
(also, the not broken build)
they likely don't
at least not in the way you'd think they would
it's probably a PS/2 to USB adapter that exposes them as USB devices to the host, given the description of the item and the fact it literally has an extra spare internal USB port
I'm assuming it's just a USB keyboard
So am I
it doesn't page fault but still doesn't work

Just times out
But the disk light is on
What am I missing? 
*the activity light that is
Even though identify works fine
Do I need some special flag for it to clear CI or something?
Fun, the AHCI driver now actually works well enoguh to read partition tables from 2 disks on physical hardware
(kinda feel like magic hearing hard drives noises and it actually reading data)
(and also, it was done on 32 bit kernel, with allocator allocating data at about 16GB physical addresses)
(so PAE also works, and kernel and userspace don't choke on 64 bit addresses and >4GB RAM)
Anyway, I'll probably add changes to 64 bit builds (the zoned pmm stuff changed the initialization somewhat) and merge IA32 support sometime soon ™
Then I just need to design the interface for filesystems 
Also this thing (AHCI) works with IOAPIC and level triggered interrupts, so I guess props to uACPI for interrupts routing
(and also, this whole thing uses c++ coroutines because why not)
Ok, there are too many things I want to do
IA64 when
gift me itanium hardware
i will port the bootloader of choice of whoever gifts me itanium hardware
Yeah, that's the issue
No hardware
Maybe I'll port to aarch64 though...

Though I really wanted to finally write a filesystem driver
Maybe in Rust 
(I wanted to do it in Ada, but that language is too alien for me)
that sounds fun
Not sure where to test

Nevermind, it was a printf skill issue 
Great, the pmm now poops itself on 64 bit platforms for some reason...
maybe I should just drop the 64 bit support 
limine tripple faults on my PC (?)
Unfun: interrupts are broken for some reason on AMD64 build...
@vale hinge
And it was refusing to post after reboot
(btw, what happened to your avatar?)
(maybe it's some massive skill issue...)
(it's not booting on 2 PCs)
ahci driver also worked on intel macbook

(before I lost interrupts...)
Fun statistic: limine passes 107 memory entries on that PC
?
what PC?
open an issue? send additional information
do you think i have a crystal ball or something lol
what does the PM of PMOS mean
protected mode
really?
Mikhail and my friend Pau
It was a 2 person project
(There was pimOS before with Ivan, but it didn't even get to loading its own page tables
)
If I boot with bios, it doesn't load, idk
On 2 PCs
Which suggests it's a skill issue on my part
So probably false alarm
But it's the PC which broke it before
Which remaps LAPIC
but hyper does work
and the image does boot in qemu
well, is it just your kernel or like, any Limine kernel?
does it work booting Linux, does it work booting other Limine kernel such as the template or test kernel bundled with the Limine repo?
limine itself doesn't boot, I see the bios logo and it reboots
with bios booting
which might suggest that I didn't write it to usb drive properly
have you made sure you created the image properly as well?
it boots in qemu
I do limine/limine bios-install $(DISK_IMAGE) and it says
Physical block size of 512 bytes.
Installing to GPT. Logical block size of 512 bytes.
Secondary header at LBA 0x3ffff.
Secondary header valid.
GPT partition NOT specified. Attempting GPT embedding.
New maximum count of partition entries: 44.
Stage 2 to be located at 0x1a00 and 0x7ffd600.
Reminder: Remember to copy the limine-bios.sys file in either
the root, /boot, /limine, or /boot/limine directories of
one of the partitions on the device, or boot will fail!
Limine BIOS stages installed successfully!
on some motherboards CSM won't boot GPT images that aren't ISOHYBRID ISOs
unless it is an ISO
idk you need to be way more specific
it also fails on a pure bios machine
It's a GPT image with 2 partitions
fat32 and ext2
is the Hyper image also GPT?
pure BIOS machines may also fail to boot disks that present GPT disk labels
Hyper is MBR
https://gitlab.com/mishakov/pmos/-/blob/dev/limine/Makefile?ref_type=heads#L118 this is how I create the image
ok well, that is one difference, you should make sure those 2 things are the same and reevaluate
and it has arch linux in bios + gpt mode installed
with grub
Attempt 2
Does it have EFI?
Idk we will see
it does
just one EfiConventionalPage descriptor?
@carmine nacelle @untold pollen check #voice-0
ok well then, i will delete the Limine repository thanks for the feedback
how can I debug it?
like i would like to see limine working on that PC
Hyper can't
@twilit talon accurate?
I can test mbr + bios
also that PC has COM port and 0xb8 for early debugging if that's needed
yeah, test #2 would be, as i said above, test Limine with BIOS/MBR
also #3 would be to please open an issue with the machine specific and what you've tested so far, just so this issue does not get lost in time if we don't fix it
Yeah, the installer cant embed it in gpt because I was lazy
cool!!
i will remove embedding anyways for 9.x so
:^)
i thought up a better replacement
Why is that?
well, you're seeing part of it here now, also shrinking and extending images causes issues with it, and so on
anyway, latest risc-v pmOS build
i686 port is fun...
Ok, so the first step of learning the language is porting its standard library 
(my latop is suffering from compiler compilations)
(also, I wonder how insane it would get, using 3 languages)
which?
why not
its a bit of a pita
The osdev wiki article is very bad though
yeah i wonder why
(it was probably written by someone who has no idea what they are doing)
i recommend you take a peek at managarm
they have rust already
and from what i know it's a giant pain in the ass
I haven't found it
(but looked for like 30 seconds)
Ok, I think it's trolling me already
I've added my target to STAGE0_MISSING_TARGETS and it's pretending it's not there
enjoy :^)
rust must have changed something
is it that bad?
apparently
linux abi compat enjoyers win again
wdym
linux abi compat is pain
linux compat is boring
that aside
id rather implement namespaces than port rust 
I'm gonna join their discord server
I'm sure some people will be thrilled to help...
no they wont
namespaces are not that hard

I still have no idea of what's happening
I've looked at managarm and redox in the rust code
And I have the same stuff as they
But no, fuck you, unsupported target
also, greping rust tree for error occurred yields nothing, but matches in binary
which makes me wonder if that could be coming from llvm
std porting is the only hard bit (but extremely hard
if you used mlibc this would be basically free 
but it shouldn't be too much worse than idk go probably and go has its own issuds
did u?
you're likely on the wrong server
@carmine nacelle no "error occurred" in llvm
yeah they said I joined wrong server
the "official" discord server for rust is for developing rustc and nobody uses it
most rustc development happens on zulip
the unofficial rust server is what you're looking for
specifically #os-dev or the rustc-dev thread in #dark-arts
llvm/tools/llvm-split/llvm-split.cpp
line 89
I can send an invite if you want
oh bruh i was in pager mode on the top of the page
is my llvm patch fucked up?
I just use x86_64-pmos normally
or whatever
without unknown

Time to dig through that I guess...
no, but llvm should be printing error
it's not coming from there...
through scientific printfs, I've deduced that it can't find the right C compiler...

How am I supposed to modify it?
(for a future reference to myself: RUSTC=/home/misha/rust-pmos/build/host/stage2/bin/rustc cargo run -p gen-target-info)
why don't I also add RISC-V and i686 and aarch64, while at it?
I think I finally made it recognize pmOS!
It's even trying to build std
(I guess it's time for some big time stubbing)
(tomorrow)
i think your problem is that cargo doesnt know about your toolchain
https://rust-lang.github.io/rustup/concepts/toolchains.html
under "custom-toolchain"
@carmine nacelle
I've read that already and it didn't work
It only started working after I cloned cc-rs and ran this with new toolchain
Inside it
And pointed std Cargo.lock to use my cc-rs
do you use a crt0 object?
I think so
that might cause the need for cc-rs
(the wiki is a bit ambiguous)
I want it to link against my libc anyway (?)
(tbh idk how rust works)
afaik you have two options either have a crt0 object that inits the stack and stuff or call the entry point directly but you need to do the setup before that
you dont need to afaik
you could implement your os api directly in rust std without a libc in between
but usually a system already has a libc so putting rust std on top of that is reasonable
My libc creates its own thread and manages signals, open files, processes and stuff like that
So I kinda want it loaded
(I guess I could reimplement it later fully in Rust)
probably?
So it works now?
Do I even need crt0 objects if in theory my libc should take care of it for me?
they need to be statically linked into every program iirc
I don't have dynamic linking anyway...
bruh, rust std wants random generator...
(and a bunch of other stuff I don't have yet)
int
random (void)
{
return 4; // generated by the roll of a fair dice
}
/// Generate cryptographically secure random numbers using a novel
/// high-performance patent-pending algorithm.
pub fn random<const N: usize>() -> [u8; N] {
// I have been informed that the letter 'A' is equally likely to be chosen as any other.
[0x41; N]
}
pub fn random() usize {
let mut ret: usize = 4;
#[cfg(target_arch = "x86_64")]
{
unsafe {
core::arch::asm!(
"rdrand",
_ = out(ret),
);
}
}
ret
}```
shrimple
this is a reference to XKCD and a suggestion to stub it out
thats actually insecure
what if someone has Google Project Zero microcode
real...
insecure hash function
probably adding some garbage data and causing a hash collision or some shit
then you're screwed anyways lol
more details though lol
no
that microcode doesnt cause a security issue
because it doesnt set CF
not for rust programms, all rust cares about is that its std main is called with a specified setup this can either be done by crt0 or by a sophisticated os lib like a userspace scheduler
or just in asm in your code in the std
I decided not to rant in porting
But
Very nice of Rust
https://pubs.opengroup.org/onlinepubs/9799919799/
The <sys/types.h> header shall define at least the following types:
gid_t
Used for group IDs.
id_t
Used as a general identifier; can be used to contain at least a pid_t, uid_t, or gid_t.
pid_t
Used for process IDs and process group IDs.
...All of the types shall be defined as arithmetic types of an appropriate length, with the following exceptions:
...
Additionally:
nlink_t, uid_t, gid_t, and id_t shall be integer types.
blksize_t, pid_t, and ssize_t shall be signed integer types.
Very nice
My ids are all int64_t
are you even allowed to do that
Am I prohibited?
looking at the spec, no
POSIX just says it has to be an integer type of "an appropriate length"
I can change it to int32_t or whatever, but it's gonna be anoying
(I mean the pmOS thing)
(Can I complain somewhere? 
)
/dev/null
how
getpid must not fail