#pmOS - microkernel OS for RISC-V, x86, and LoongArch

1 messages · Page 5 of 1

dense carbon
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it's usually so fast as to warrant no asynchronicity

carmine nacelle
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Which then talks to drivers

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Via IPC, which is asynchronous

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And stores the cache

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Idk, it's a bit of a dumb system, I can just put part of it into each driver

carmine nacelle
carmine nacelle
dense carbon
carmine nacelle
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which would make my vfs cache server block

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(weird design)

left dew
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why do you have a vfs cache server?

carmine nacelle
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Because after the filesystem "handle" (I only have IPC ports atm) for a file is resolved from it, the libc then communicates with filesystems directly

left dew
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that is a weird design

carmine nacelle
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Yeah, but what else can I do

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Kernel has no knowledge of filesystems, it's all IPC for it

left dew
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well, have the vfs server do the talking for you?

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you = whoever is trying to open/read/write a file

carmine nacelle
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How would that work?

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It would be a message to VFS then a message to filesystem for everything

left dew
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wdym how? it would just talk to the server responsible for a given file system

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yeah that's how, i guess

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managarm has some optimizations for that iirc

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i think the call that "passthrough lanes"

carmine nacelle
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And I just let processes talk directly to filesystems

left dew
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how does the process know what file system server to talk to

carmine nacelle
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Also, VFS can disappear and make of the opened files would be closed

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It asks VFS cache

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It's a bad name

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Should be something like namespaces server

hexed acorn
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and the ipc on that lane is handled by the fs server responsible for that particular file

carmine nacelle
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I'm kinda thinking about pulling a galaxybrain move and exposing all ACPI devices to devfs (which I don't have yet)

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Sounds like a nice abstraction abstraction

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And also maybe adding "namespaces" is a solution to root remounting

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Like I would have "dev" namespace, which would get mounted to /dev

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And then various servers will then be able to mount their stuff there

carmine nacelle
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This is so good

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It can probably just expose AML methods as Unix files

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Lazily executing it

carmine nacelle
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A bit of a random thought: why not use "banks" of memory for struct Pages on 32 bit platforms? This way I can support "infinite" RAM with PAE

carmine nacelle
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I hate gcc

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How do I make this go away? nooo

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misha@Ryzen-PC:~/gcc-pmos/gcc$ cat ./config/linux-android.opt.urls
; Autogenerated by regenerate-opt-urls.py from gcc/config/linux-android.opt and generated HTML

mandroid
UrlSuffix(gcc/GNU_002fLinux-Options.html#index-mandroid)

tno-android-cc
UrlSuffix(gcc/GNU_002fLinux-Options.html#index-tno-android-cc)

tno-android-ld
UrlSuffix(gcc/GNU_002fLinux-Options.html#index-tno-android-ld)
carmine nacelle
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Maybe I'll just remove pmos.opt

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fuck it

carmine nacelle
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Anyway, I think I'm gonna disappear for two weeks, until I'm finished with the exams

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The plan after that is to

  1. Implement AHCI reading
  2. Redo VFS mess (although maybe it's not too bad, but C just makes me feel miserable)
  3. S3 sleep?
  4. Finish implementing signals
  5. Implement USB
  6. Look at GPU stuff
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(I wanna see if the whole "ACPI and all drivers in userspace" will survive S3)

twilit talon
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thats a good sturdiness test

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of both kernel & driver design

hoary moat
carmine nacelle
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In theory I just need to save and restore all the state

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It can't be that hard

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Just a few extra callbacks

hoary moat
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lmao

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what about D states?

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and power resources?

carmine nacelle
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What about them?

hoary moat
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you need them

carmine nacelle
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Idk how they work

hoary moat
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you kinda need them for suspend

hoary moat
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so if you have no problem with not being able to wake properly

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that's fine

carmine nacelle
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It would be cool to be support them in general

lunar orchid
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why pmos is removed from active threads

carmine nacelle
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I have exams

untold pollen
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Bump

carmine nacelle
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The build

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FDT doesn't do much

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And AHCI driver is broken for some reason (because of broken fork)

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My galaxybrain kernel can't save the registers properly so forked processes call exit for some reason immediately after forking

untold pollen
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As long as it loads everything it needs via uefi to do anything I guess we will be fine :P

carmine nacelle
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I've tested uboot half a year ago

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If it doesn't work now I'll return to it in a week

untold pollen
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Place your bets if it still boots

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I need to fine two more probes though

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nvm one more probe

carmine nacelle
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Does this board have ns16550-style controller?

untold pollen
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No

carmine nacelle
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then there will probably be no logs to uart from userspace

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framebuffer should still work though

untold pollen
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hang on this thing is acting odd

untold pollen
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reee

untold pollen
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Not sure why but this thing isnt working at all

carmine nacelle
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the board?

untold pollen
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yeah

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will try with og image really quick iguess

carmine nacelle
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Is it not working with pmOS or not working at all?

lunar orchid
carmine nacelle
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?

lunar orchid
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😡

carmine nacelle
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idk

untold pollen
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hmm seems like at all

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not sure whats going on there

untold pollen
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I’ll try again later not sure what’s going on

noble mason
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rv or x86?

carmine nacelle
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risc-v

noble mason
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virt machine will work?

carmine nacelle
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yes

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it's the only thing i've tested it on

noble mason
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windows ❤️

carmine nacelle
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what type of virus did it detect? lol

noble mason
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pmos is actually trojan do not download

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ill try pmos on linux tomorrow

lunar orchid
vale hazel
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exams are ass

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also im giving pmos a star

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:)

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@carmine nacelle

carmine nacelle
vale hazel
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u deserve way more stars

carmine nacelle
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thanks for starring

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idk, I'm too stressed

vale hazel
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dont force urself to work on pmos

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work on it WHEN u want to

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focus on ur exams

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university is crazy scary i would be shitting my pants as well

carmine nacelle
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I'm not working on it atm

vale hazel
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good

carmine nacelle
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(and I think I have a month of holidays)

hoary moat
carmine nacelle
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Ok I guess I'm semi-back
I caught a flu (?)

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Anyways, I need to think how to implement partition probing and stuff like that

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And if I want it to be another server

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Which would also expose itself as a filesystem

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so the filesystems can then just do open("/dev/sda") or whatever

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(because wtf not)

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And the network subsystem is gonna be in Go

carmine nacelle
carmine nacelle
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Did I just catch the framebuffer bug in QEMU?

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wtf

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kernel just decided it doesn't want to work anymore

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i'm done

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working with kvm but not with tsc is something new

carmine nacelle
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somehow -bios ovmf-x86/OVMF.fd breaks it...

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I think my timers are broken...

carmine nacelle
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average C++

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And fun templates

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Thonk timers are still broken...

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(I think I don't EOI spurious interrupts)

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I don't get it

Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI.

vale hazel
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one kill

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go to sleep

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please

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dont be like me

carmine nacelle
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I usually go to sleep at 3 am

scarlet salmon
carmine nacelle
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I can't sleep iwannadie

scarlet salmon
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I was talking more to nyaux, but you should as well

carmine nacelle
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Debugging continues: it looks like I get spurious int as soon as I enter userspace, even if I kill IOAPIC code

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fuck kvm

twilit talon
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wait whats happening, didnt u have working userspace

carmine nacelle
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My interrupts just casually stop working

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like userspace works, but I loose timers and external ints

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I think that's also the reason why it was breaking on some physical PCs

carmine nacelle
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Wtf is this code

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(for reference)

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I'm pointing LAPIC timer to spurious int vector, and wondering why I'm getting that interrupt

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great

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Nice 2 years old code

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What's a better question is why did it only break now

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I think the whole timer/clock code has to go...

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I'm too fed up with it

carmine nacelle
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When did lld get this good?

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This is fun...

carmine nacelle
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(average c++ skill issue)

carmine nacelle
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I guess AHCI is cooking...

carmine nacelle
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(now I just need to think about IPC)

toxic torrent
carmine nacelle
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I'm using 19.1.0-rc3

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but I guess I could rebase onto that

carmine nacelle
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Ok, now that I've slept on it, I think I'll implement sending memory objects

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And just do zero-copy disk io

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no read() on block devices

carmine nacelle
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(now that I think of it, it should not even be very difficult to implement)

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no new syscalls

carmine nacelle
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and somehow, I think the permissions system is building itself

carmine nacelle
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I think I know how to handle multithreaded filesystems

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(explanation: currently, my ports are tied to threads, which kinda makes some stuff difficult)

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I've been thinking about breaking that up, but didn't come up with anything I liked

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But, why not just return sets of ports

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And let userspace decide what it wants to do with them

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With some scheduler changes, and considering that every process has a worker thread anyway, it can also get notifications from scheduler, and keep track of which core thread is bound to

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So in other words, all threads can know which CPU they are on, without making syscalls

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And with some caching memes, my libc can just decide where to send messages for each request

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(like how did my stupid IPC just work out?)

carmine nacelle
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Wtf declaring overloaded 'operator()' as 'static' is a C++23 extension [-Wc++23-extensions]

restive junco
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cursed

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lol

carmine nacelle
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how was it only added in c++23?

toxic torrent
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i was skimming through the code

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isn't this magic reversed?

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ah nvm the 7f is at the start

carmine nacelle
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this is dead code

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from when I was using multiboot2 to boot bruh

toxic torrent
carmine nacelle
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this would get loaded by multiboot, load kernel, and continue in ring 3 KEKW

toxic torrent
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bruh

carmine nacelle
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(now in kernel)

carmine nacelle
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nice c++

left dew
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i feel like this line of code will be a source of at least one bug

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is begin an iterator?

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that doesn't make sense nvm

carmine nacelle
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Yeah

left dew
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is it some sort of intrusive data structure?

carmine nacelle
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it is

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my own impl

left dew
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makes perfect sense

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otherwise that delete &*it would've been very weird

carmine nacelle
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I've just changed std::list-like things of smart pointers (because why not) to intrusive list, removing 2 memory allocations...

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anyway, I think I'll finally have AHCI disk reading after I implement sending memory objects

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(memory object is my abstraction for in-kernel buffer of pages)

carmine nacelle
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cool, apparently I don't have syscall for creating memory objects...

eager rose
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do I understand it correctly as that you're doing the microkernel equivalent of memfd_create + sendmsg(SCM_RIGHTS)?

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also, are your userspace "processes" (or "tasks" or whatever) isolated from each other in memory?

carmine nacelle
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"tasks" can share or not page tables

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so I'm creating a memory buffer, DMAing to it, and sending it to another process

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which can then move pages to other files

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and there are no memory copies

eager rose
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iirc Linux has a refcounted struct mm_struct, and clone() and whatever other syscalls there are can "unshare" it by setting some flag (CLONE_MM or something). I guess that would be similar in semantics to what you are doing (except afaik Linux only allows "unsharing" the mm_struct at clone or fork (done implicitly) time if some constraints apply)

carmine nacelle
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I have done very little linux userspace development so idk

eager rose
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ok actually it is CLONE_VM

carmine nacelle
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I'm also trying to implement posix api on top of what I have I guess

eager rose
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afaik linux clone3 isn't posix

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generally linux isn't posix

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... and that is a good thing

carmine nacelle
toxic torrent
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question, wouldn't an infinite loop in one of the servers cause one cpu to be at 100% at all times?

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or is that intended

carmine nacelle
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My IPC blocks on reads from empty queues

toxic torrent
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i'm looking at processd atm

carmine nacelle
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It does get_message or whatever (I don't remember), and it should block

carmine nacelle
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what's up with it?

restive junco
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it's missing a "n"

carmine nacelle
toxic torrent
hoary moat
carmine nacelle
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How do I disable them?

hoary moat
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cli

twilit talon
hoary moat
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Set lapic's priority level register to 0xf0

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Also

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So idk

carmine nacelle
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Ok, I think I'll finally implement sending memory objects

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I need to decide how to do that...

carmine nacelle
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Did I just discover why it would break sometimes?

carmine nacelle
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I think it's trolling me

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(wtf)

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it has to be something dumb

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Variable just magically becomes 3...

carmine nacelle
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bruh c++ moment

carmine nacelle
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ok, surprisingly sending memory objects was very easy (ignoring the debugging/discovery of unrelated issue)

carmine nacelle
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Time to figure out how to build a disk image with make

carmine nacelle
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Bruh did AHCI driver just work?

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(238 is 0xEE, which is GPT)

carmine nacelle
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the first entry looks weird...

carmine nacelle
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(I'm gonna stop polluting uACPI thread)

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This looks credible...

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I think it's working, now I just need to figure out how to mount filesystems

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Like how do I do fstab or whatever

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Cool, the dev branch is juicy...

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What if I just merge it?

carmine nacelle
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and to fix fork on ia32 and risc-v

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which means that I need to fix vfs (even though it isn't really broken...)

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(by which I mean that I need to write a good hash map header)

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and "improve the code quality"

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but I want to do USB...

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Maybe pmOS will finally have shell in 2026...

carmine nacelle
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which will talk to devicesd

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which will talk to vfsd

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which will talk to bootstrapd

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which will talk to filesystems drivers

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but maybe I want fat32 driver be written in Rust...

torpid vector
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o/

pearl narwhal
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are your filesystem drivers separate servers or are they libraries attached to vfsd or blockd or whatever

carmine nacelle
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I haven't decided

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They will probably be separate servers

carmine nacelle
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error: unknown type name '__uint128_t' bruh

hoary moat
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ah yes that doesn't exist on i686

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or the m68k

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kinda sad, I just coped by using uint64_t instead

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in the one place I used 128-bit integers

carmine nacelle
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I'm using it to calculate timer frequencies

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(stolen from managram)

eager rose
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iirc I do something cursed by measuring the frequency, then first multiplying by like a million or something, then dividing by the frequency, followed by multiplying by 1000 again

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though idr if this was for TSC or HPET

carmine nacelle
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ld.lld: error: undefined symbol: __udivdi3 nooo

toxic torrent
carmine nacelle
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I think I'll finally have to add memory region stuff to my PMM

toxic torrent
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please don't remind me

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i need to do the same

carmine nacelle
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Since ia32 wants cr3 in < 4GB

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It should be doable...

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I just don't know how to deal with it

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Like do I always allocate from > 4GB and then go to < 4GB if that fails?

toxic torrent
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hm

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wait, does that mean on x86 you cannot physically have more than 1048576 processes ever?

carmine nacelle
#

?

carmine nacelle
carmine nacelle
toxic torrent
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isn't ia32 = x86?

carmine nacelle
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32 bit x86

toxic torrent
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yea

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to be fair you'd surely run out of ram before reaching 1M processes

carmine nacelle
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Idk

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Yeah

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I'll probably limit kernel to 16GB of RAM or something anyway

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because of struct page

carmine nacelle
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Cool, the paging is almost working

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But it craps itself while doing printf...

carmine nacelle
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This looks reasonable...

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Silly issue fixed...

carmine nacelle
toxic torrent
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how is this 32 bytes

carmine nacelle
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4 entries of 8 bytes?

toxic torrent
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ah i didn't read the middle block

carmine nacelle
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I'm too dumb for this

Software can transition between 32-bit paging and PAE paging by changing the value of CR4.PAE with MOV to CR4.

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Wouldn't it pagefault?

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If PAE paging would be in use following an execution of MOV to CR0 or MOV to CR4 (see Section 4.1.1) and the
instruction is modifying any of CR0.CD, CR0.NW, CR0.PG, CR4.PAE, CR4.PGE, CR4.PSE, or CR4.SMEP; then the
PDPTEs are loaded from the address in CR3.

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AMD manual says this

Implicit Invalidations. The following operations cause the entire TLB to be invalidated, including
global pages:
• Modifying the CR0.PG bit (paging enable).
• Modifying the CR4.PAE bit (physical-address extensions), the CR4.PSE bit (page-size
extensions), or the CR4.PGE bit (page-global enable).

carmine nacelle
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(the porting to ia32 continues...)

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error: undefined symbol: __udivdi3 nooo

carmine nacelle
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Cool, it looks like libclang_rt.builtins-i386 is sane and doesn't emit xmm for that

carmine nacelle
#
c0102e9c: c7 44 24 4c 00 00 00 00          movl    $0x0, 0x4c(%esp)
;         long_string_str long_string = {0, 0};
c0102ea4: 8d 74 24 50                      leal    0x50(%esp), %esi
c0102ea8: c7 44 24 50 00 00 00 00          movl    $0x0, 0x50(%esp)
c0102eb0: c7 44 24 54 00 00 00 00          movl    $0x0, 0x54(%esp)
; void *operator new[](size_t size) { return malloc(size); }
c0102eb8: b9 0a 00 00 00                   movl    $0xa, %ecx
c0102ebd: e8 7e 85 00 00                   calll    0xc010b440 <malloc>
;             long_string.ptr  = new char[length + 1];
c0102ec2: 89 44 24 54                      movl    %eax, 0x54(%esp)
;     serial_logger.printf("%s %i\n", bootstrap.c_str(), bootstrap.length());
c0102ec6: 6a 00                            pushl    $0x0
c0102ec8: 56                               pushl    %esi
c0102ec9: 68 1c e3 11 c0                   pushl    $0xc011e31c             # imm = 0xC011E31C
c0102ece: 68 44 17 12 c0                   pushl    $0xc0121744             # imm = 0xC0121744
c0102ed3: e8 c8 82 00 00                   calll    0xc010b1a0 <_ZN6Logger6printfEPKcz>
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I'm smelling UB

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Or stupid code

carmine nacelle
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(for some reason, the kernel is having a skill issue with printf...)

eager rose
#

wild guess: since afaik you're porting to 32-bit, it might be having skill issues with int64_t and uint64_t values. assuming you don't mean something like page faults occuring in vsnprintf.

carmine nacelle
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I've had issues with that in allocators because of __builtin_clzl/__builtin_clzll

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But it doesn't look like it

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It loads 0 from vtable of a global class

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for some reason...

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and calls a null pointer

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Is it the same dumb problem that I've had about a month ago?

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I think it's stack overflow bruh

hoary moat
carmine nacelle
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Fun, it's almost working...

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Now I just need to write all the boring assembly to handle interrupts...

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(and I also want to support PAE next)

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(which implies adding zoned to my pmm)

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But after thinking about it, it should be quite easy with my design

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And I also need to figure out SMP bringup...

carmine nacelle
toxic torrent
carmine nacelle
#

I'm allocating 8KB arrays on stack

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For TLB shootdowns

left dew
#

that 4KiB stack must be having lots of fun

carmine nacelle
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I kinda have userspace (now I just need PF handler and memes meme)

carmine nacelle
#

thonk apparently hardware task switching is not that bad...

left dew
#

printing registers in decimal is diabolical

toxic torrent
little smelt
carmine nacelle
#

Anyway, maybe I will have it fully working by the end of today?

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(the same thing I said on Sunday)

carmine nacelle
#

New least overcomplicated save_registers function trl ```x86asm
.type save_registers, @function
save_registers:
pushl %eax
movw $0x1b, %ax
cmpw 8(%esp), %ax
jne 1f

movw $0x38, %ax
movl %ax, %gs
movl %gs:16, %eax
popl (%eax)
movl %ebx, 4(%eax)
movl %ecx, 8(%eax)
movl %edx, 12(%eax)
movl %esi, 16(%eax)
movl %edi, 20(%eax)
movl %ebp, 24(%eax)

movl 8(%esp), %ecx # %eip
movl 16(%esp), %edx # eflags
movl %ecx, 32(%eax)
movl %edx, 36(%eax)
movl 20(%esp), %ecx # esp
movl 4(%esp), %edx # error code
movl %ecx, 28(%esp)
xorl %ecx, %ecx
movl %ecx, 52(%eax)
xorl %eax, %eax
ret

1:
movw $0x70, %ax
cmpw 8(%esp), %ax
jne 1f

movl %gs:16, %eax
popl (%eax)
movl %ebx, 4(%eax)
movl %ecx, 8(%eax)
movl %edx, 12(%eax)
movl %esi, 16(%eax)
movl %edi, 20(%eax)
movl %ebp, 24(%eax)

popl %ecx
popl %edx
addl $4, %esp
popl 32(%eax)
addl $4, %esp
popl 36(%eax)
movl %esp, 28(%eax)
movl %gs:4, %esp
pushl %ecx
movl $4, %ecx
movl %ecx, 52(%eax)
xorl %eax, %eax
ret

1:
xchgl %ecx, 4(%esp)
xchgl %ecx, (%esp)
pushl %edx
pushl %ebx
pushl %ebp
pushl %esi
pushl %edi

movl %esp, %eax
movl 28(%esp), %edx
jmp *%ecx
eager rose
#

honestly I should just ask some osdevers in here to hand-"optimize" some assembly routines... then have it as a CTF reversing challenge

left dew
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wtf is j *%ecx

hexed acorn
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ig that was intended to be jmp?

left dew
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definitely

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i'm just saying "wtf is this" meme

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because it's definitely not a valid mnemonic

carmine nacelle
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It kinda worked after an hour of debugging meme

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Now SSE gives me #UD instead of #NM for some reason sadmeme

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even though cr0 = 0xe000001b

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(which is CR0.MP and CR0.TS set and CR0.EM cleared)

carmine nacelle
carmine nacelle
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QEMU log was just showing 6 instead of 7 for some reason...

carmine nacelle
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Cool, now it works in bochs but breaks in qemu...

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And in bochs it's returning ECONNREFUSED

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because why wouldn't it I guess

carmine nacelle
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Bruh clang's -O3 -flto assembly is weird...

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Cool, it's trying to load userspace stuff (the errors are expected since it's 64 bit binaries because I can't be bothered to fix the build scripts...)

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And it #GPs in SSE instruction in QEMU for no reason

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(I think)

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(I don't have GP handler...)

carmine nacelle
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Yep

c0105766: 0f 20 e0                         movl    %cr4, %eax
;     cr4 |= (0x01 << 10); // CR4.OSXMMEXCPT (enable #XF exception)
c0105769: 89 c1                            movl    %eax, %ecx
c010576b: 81 c9 00 06 00 00                orl    $0x600, %ecx            # imm = 0x600
; inline void setCR4(unsigned long val) { asm("movl %0, %%cr4" : : "r"(val)); }
c0105771: 0f 22 e1                         movl    %ecx, %cr4
;     if (xsave_supported) {
c0105774: 80 3d f8 4e 13 c0 01             cmpb    $0x1, -0x3fecb108
c010577b: 75 14                            jne    0xc0105791 <kmain+0x3611>
;         setCR4(getCR4() | CR4_OSXSAVE);
c010577d: 0d 00 00 04 00                   orl    $0x40000, %eax          # imm = 0x40000
; inline void setCR4(unsigned long val) { asm("movl %0, %%cr4" : : "r"(val)); }
c0105782: 0f 22 e0                         movl    %eax, %cr4
#
void enable_sse()
{
    auto cr0 = getCR0();
    cr0 &= ~(0x01UL << 2); // CR0.EM
    cr0 |= (0x01 << 1);    // CR0.MP
    cr0 |= (0x01 << 3);    // CR0.TS (Lazy task switching)
    setCR0(cr0);

    auto cr4 = getCR4();
    cr4 |= (0x01 << 9);  // CR4.OSFXSR (enable FXSAVE/FXRSTOR)
    cr4 |= (0x01 << 10); // CR4.OSXMMEXCPT (enable #XF exception)
    setCR4(cr4);

    if (xsave_supported) {
        setCR4(getCR4() | CR4_OSXSAVE);
        set_xcr(0, xcr0);
    }
}
#

(that was it, qemu also works now)

carmine nacelle
#

Userspace kinda works more, but framebuffer driver is crashing...

twilit talon
#

Letsgo

carmine nacelle
#

(something's passing nullptr to flanterm_write 💀)

#

(if I can read the assembly)

#

Or not

#

which makes no sense

#

I think my registers saving/restoring is broken

carmine nacelle
#

I can't get bochs to boot nooo

#

Could hyper be pagefaulting?

#

It boots fine in QEMU

#

@twilit talon ?

twilit talon
#

Doubt

#

It worked last time

carmine nacelle
#

This is pagefaulting with kernel address..?

#

Nope

#

I'm dumb

#

uint64_t's are haunting me

carmine nacelle
carmine nacelle
#

a.result is int64_t, aka long long

#

(uint64_ts are really haunting me)

carmine nacelle
#

(I think I know what's killing the framebuffer/hanging the system)

#

it's i8042

#

(I don't have timers...)

twilit talon
#

why are u doing bochs btw

carmine nacelle
#

?

#

it's qemu

#

idk bochs debugger is convenient to me

#

when there are a lot of context switches and gdb can't keep up

carmine nacelle
#

qemu that is

twilit talon
#

ah

carmine nacelle
carmine nacelle
#

More stuff is working...

#

(I really need to fix timers)

carmine nacelle
#

(it looks like something has destroyed the stack after the syscall)

hoary moat
carmine nacelle
#

And it even seems to work

#

Anyway, the only things that's broken is ACPI (should be trivial to reimplement) and that weird pagefault

#

(and maybe fork)

#

(since it was broken for no reason with 64 bit kernel)

#

and then I want to implement zones in pmm

#

(which will be also beneficial for 64 bit memes)

#

and PAE because I like to suffer

#

(though I don't expect to)

#

oh, and SMP

#

I need to investigate how to load the trampoline

#

I will probably add an under 1MB zone to PMM

#

Which I'll also eventually use for ISA DMA trl

#

And try to make it relocatable

carmine nacelle
#

Fun, I'm not getting lapic interrupts for some reason...

#

(definitely a qemu bug)

#

I didn't know IF was respected by ring 3

#

Now we're talking...

carmine nacelle
#

bruh it's pagefaulting in movl %gs:0x0, %edi

#

somehow everything is working

#

(except interrupts trl)

#

but that's the kernel skill issue

carmine nacelle
#

The kernel is trolling me

#

It #GPs on keybord interrupt then pagefaults on ACPI interrupt

#

And it pagefaults inside malloc nooo

#

thonk that pagefault might be normal though

#

I wonder if that #GP is unrelated to interrupts thonk

#

It's sus that it's in framebuffer's driver

carmine nacelle
carmine nacelle
#

This is kinda weird... thonk

#

(Or maybe not, if I have a memory leak, for example...)

#

Or an interrupt storm

#

Now all userspace just pagefaults when I press the power button

eager rose
carmine nacelle
#

Idk

#

Maybe it can't allocate memory

#

(I'm in a long trip and have drained my laptop's battery so I can't debug untill I get home nooo)

hoary moat
#

use your brain to transfer energy from your brain to your laptop

#

to charge it

carmine nacelle
#

I have a charger but it's 33W so it charges by 1% every 5 minutes or so

#

(maybe faster, but still very slow)

carmine nacelle
#

Bruh windows's trolling me

#

(cpu stuck at 530 MHz)

left dew
#

i mean it's not utilized so of course it's clocked lower than usual

#

that's how laptops work

carmine nacelle
#

No

#

It's not underutilized

left dew
#

oh it looks like it is

#

16% lol

#

mine does that too if i don't do anything, but that's probably becuase i dont have some ultra performance thing enabled or whatever

carmine nacelle
#

It idles at 1 GHz usually

#

But it gets stuck at some very low frequency

carmine nacelle
#

though the PS/2 controller still spams interrupts for some reason

#

(broken timer infrastructure?)

#

(I poll PS/2 devices every few seconds to check that they were not disconnected or died)

#

And uACPI has successfully shut down QEMU!

#

Yep, timers are broken, but spamming is not because of that

#

(and that's also why uACPI was bugged (probably))

#

(or maybe it's actually not)

#

Thonk I think it's PS/2 mouse...

#

Yep, timers just like to die from time to time...

carmine nacelle
#

I think it's time to move IOAPIC to the kernel...

#

Also I have a fucked thought

#

What if I make the kernel preemptive by timers

#

But just not reschedule inside them

#

Though I don't know how to notify the lower priority levels

#

Also, I think I know why the RISC-V port is calling exit(0) on fork meme

carmine nacelle
#

I'm having skill issue passing arguments from asm to C

left dew
#

push arguments in reverse order, don't forget to pop them at the end

#

also something something stack alignment

#

32 bit is weird

eager rose
carmine nacelle
#

As usual?

carmine nacelle
carmine nacelle
#

(it also does interrupts allocation at the moment)

#

(and had hpet driver)

#

though I just use lapic now

eager rose
#

goddamn

#

cursed

carmine nacelle
#

why

eager rose
#

idk. it's just an unusual way of doing things

#

your microkernel is like a scheduler, ipc, and a trimmed-down memory manager

carmine nacelle
#

it's a fat memory manager

carmine nacelle
eager rose
#

yeah

#

but like

#

allocating interrupt lines in userspace, sure. I can buy that.

but actually writing to APIC registers and stuff, that's just... a bit far, maybe

carmine nacelle
#

LAPIC is in kernel

#

though it kinda creates problems

#

since I don't know what to do with interrupts masking now

#

I guess kernel could ask userspace, but that seems weird

#

What if all userspace dies and kernel gets stormed by interrupts

#

(also, I've put plic into kernel with risc-v memes)

carmine nacelle
#

bruh I like how f'ed it's getting

#

kernel is becoming nonpreemptive with a little * that it actually is

#

(I just need to change amd64 and risc-v ports nooo)

toxic torrent
#

lol

carmine nacelle
#

anyway, that was how I wanted to do copy-to-user anyway

#

(by allowing the kernel to pagefault in itself)

carmine nacelle
carmine nacelle
carmine nacelle
#

Now I just let the kernel only map the new top level ptes in the global/idle page table, and copy it to the other ones, on demand, in pagefaults anywhere inside the kernel, if they were not copied during the task creation

#

also I don't like how flanterm has stopped #GPing

#

I guess I'll have to wait for another few months for it to surface again

carmine nacelle
#

It's deducing that the page is only mapped once after fork

#

which sounds fishy...

#

Yep the kernel is being weird

#

or my printf is broken

#

somehow the pages teleport from one page table to the other one

#

magic

#

I think I'm going to sleep risc

#

(I slept for 5 hours today, and I think I'm too energetic (considering that I've taken 2 (or maybe 3) cups of coffee, when I usually don't drink any))

#

(what the fuck is this code)

#

(32 bit addr mask is ~0xfff)

#

cool, kernel decided to pagefault, why not

carmine nacelle
hoary moat
#

oh yeah that was me

carmine nacelle
#

ok I'm hoping the oberrow curse goes away in the morning

#

my paging code was the thing that was never crashing

#

but uint64_ts are haunting me now

hoary moat
#

sorry you have to find out this way

carmine nacelle
#

cleansing negative energy from pmOS kernel

hoary moat
#

I've heard if you smoke crack before starting osdev, bugs go away (this is a joke, don't smoke crack)

carmine nacelle
#

I'll just change the vscode theme to light so they burn

carmine nacelle
#

(I really need stack guard pages)

#

(especially since I have a good vmm which could actually trivially let me do that)

carmine nacelle
#

Why is is copying all of them if it was only told to copy 1 page? thonk

#

(there is no such thing as too many printfs)

#

more wtf code

#

Cool it seems to be working

#

(the fork that is)

#

Now it just fails to map the memory object when reading the AHCI disk (probably uint64_t's striking again)

carmine nacelle
#

Cool, I guess AHCI also works now

#

Also, somehow the i686 port feels very fast

#

(I think it's because of the temp mappings)

#

I wonder how it would perform if I redo the read from user function...

carmine nacelle
#

thonk I wanted to do ifunc memes, but I still need to figure out ELF relocations...

#

So I guess I'll do the fast copy from user memes

carmine nacelle
#

I'm having weird issue with clang

#

Which pops arguments from stack

#

(it feels like clang is using stdcall instead of cdecl for some reason, or I'm stupid and can't write assembly)

#

anyway, I've changed addl $24, %esp to leal -16(%ebp), %esp since I don't trust clang (aka I don't know my tooling) and it seems to be working...

#

Though I am getting a suspicious ```
/home/misha/pmos/kernel/arch/i686/paging/user_access.cc:5:28: warning: 'user_access_page_fault' has C-linkage specified, but returns incomplete type 'ReturnStr<bool>' which could be incompatible with C [-Wreturn-type-c-linkage]
5 | extern "C" ReturnStr<bool> user_access_page_fault(unsigned access, const char *faulting_addr,
| ^
1 warning generated.

carmine nacelle
#

and it's tripple faulting with kvm nooo

carmine nacelle
vale hazel
#

pmos playing portal 2 when

carmine nacelle
#

When I get a disk driver and a shell

#

(although well, AHCI kinda works (it pagefaults on phys hardware))

carmine nacelle
#

Now I just save nested interrupt registers on stack...

carmine nacelle
#

And I suspect I know why the framebuffer was casually breaking

carmine nacelle
#

I'm having a skill issue with GDT nooo

carmine nacelle
#

(something is destroying the return frame, gdt works as normal (it seems))

carmine nacelle
carmine nacelle
#

Ok, I think it's time to add zones to my PMM

#

(Then do PAE and SMP on i686...)

carmine nacelle
#

I wonder...

#

if this is what could be breaking the framebuffer...

#

(ok, I urgently need watchdog memes)

carmine nacelle
#

I've been thinking about this all day, and I haven't come up with something that I like...

#

I think I'll just create a general, and below 4G zone, and a reserved below 1MB zone for now, and that's it

carmine nacelle
#

Oof, PAE is not working well...

carmine nacelle
#

bruh, auto is trolling me

#

Ok I have absolutely no clue of what the fuck is happening

#

pmm just pretends that addresses above 4GB don't exist, even though they clearly do

#

then some fuckery happens

#

and then the memory read by uacpi becomes corrupt

#

or maybe it isn't?

#

wtf

#

all I did was enabling PAE

#

How nice

#

(the only nice thing is that it's consistent...)

#

(32 bit ints are really haunting me nooo)

#

This is insanity

#

How does it even get demoted to int from unsigned long long?

#

The kernel has really gone rogue...

#

(that looks like ascii)

carmine nacelle
#

Could it be a seabios skill issue?

#

I want to try something...

#

bruh I think hyper just tripple faults, with no image

carmine nacelle
#

removing -O3 and lto makes it fail to boot...

little smelt
toxic torrent
little smelt
#

not even my OS dared to do that

#

altho when my APIC implementation was wrong the keyboard only worked on -O3

#

then i discovered i did not setup the redirect tables

carmine nacelle
#

Now it crashes in different place

#

(all registers get ASCII in them, and then the kernel pagefaults)

carmine nacelle
#

bruh it returns to a bogus address, ebp also points to shit, and I have no idea how to debug that

carmine nacelle
#

Idk why, but if feels like I'm using wrong calling convention

carmine nacelle
#

(except that the kernel also pagefaults now)

#

I suspect I know what's going on...

carmine nacelle
#

I wonder if this could be an issue with tlb...

hoary moat
#

*TLS (?)

carmine nacelle
#

No

#

Translation Lookaside Buffer

#

I think it never gets invalidated somehow

#

like flanterm works, and it uses the same functions, so phys mappings have to be correct...

carmine nacelle
#

Yep, I've compared the logs, and it's not flushing the tlb properly

carmine nacelle
#

It was a dumb mistake in page invalidation loop

#

(the only issue now is that AHCI driver pagefaults...)

carmine nacelle
#

ok, PAE kinda seems to be fully working...

#

(I just need to fix PMM ignoring physical memory limit)

twilit talon
carmine nacelle
#

it was not invalidating tlb

twilit talon
#

bruh

carmine nacelle
#

between mmap and munmap

carmine nacelle
carmine nacelle
#

For legacy devices DMA

carmine nacelle
#

(if someone wants to try it bruh)

#

The only thing missing is NX (which is also unsupported on x86_64 port)

#

but works on RISC-V, so it should mostly be working...

#

I mean be easy to implement...

#

What's weird is that PAE is supposedly disabled yet it's still doing that

carmine nacelle
#

ok, I think I need a PXE server...

carmine nacelle
#

Cool, ignoring the fact that AHCI driver explodes (probably after seeing 6TB drive), it fully works!

#

thonk how do these work?

hoary moat
#

Magic

carmine nacelle
#

Ok, since my holidays end this week, I think I'll just fix the x86_64 and RISC-V ports and merge the ia32 port without SMP

#

(though I still need to investigate it not working on the Sony laptop...)

cyan elk
#

at least not in the way you'd think they would

#

it's probably a PS/2 to USB adapter that exposes them as USB devices to the host, given the description of the item and the fact it literally has an extra spare internal USB port

carmine nacelle
#

I'm assuming it's just a USB keyboard

carmine nacelle
#

bruh my AHCI driver is trolling me

hoary moat
carmine nacelle
#

It was just me being dump

#

It was doing what I told it to do

hoary moat
#

My code does what it wants to do

#

So at least yours does what you told it to do

carmine nacelle
#

it doesn't page fault but still doesn't work

#

Just times out

#

But the disk light is on

#

What am I missing? thonk

#

*the activity light that is

#

Even though identify works fine

#

Do I need some special flag for it to clear CI or something?

carmine nacelle
#

Fun, the AHCI driver now actually works well enoguh to read partition tables from 2 disks on physical hardware

#

(kinda feel like magic hearing hard drives noises and it actually reading data)

#

(and also, it was done on 32 bit kernel, with allocator allocating data at about 16GB physical addresses)

#

(so PAE also works, and kernel and userspace don't choke on 64 bit addresses and >4GB RAM)

#

Anyway, I'll probably add changes to 64 bit builds (the zoned pmm stuff changed the initialization somewhat) and merge IA32 support sometime soon ™

#

Then I just need to design the interface for filesystems nooo

carmine nacelle
#

(and also, this whole thing uses c++ coroutines because why not)

carmine nacelle
#

Ok, there are too many things I want to do

carmine nacelle
#

When either Limine or Hyper decides to support it

#

@twilit talon ?

pearl narwhal
#

gift me itanium hardware

#

i will port the bootloader of choice of whoever gifts me itanium hardware

carmine nacelle
#

Yeah, that's the issue

#

No hardware

#

Maybe I'll port to aarch64 though...

#

Though I really wanted to finally write a filesystem driver

#

Maybe in Rust trl

#

(I wanted to do it in Ada, but that language is too alien for me)

pearl narwhal
twilit talon
carmine nacelle
#

Nevermind, it was a printf skill issue bruh

#

Great, the pmm now poops itself on 64 bit platforms for some reason...

#

maybe I should just drop the 64 bit support trl

pearl narwhal
#

just drop everything

#

pmOS should only run in your mind

carmine nacelle
#

bruh limine tripple faults on my PC (?)

#

Unfun: interrupts are broken for some reason on AMD64 build...

carmine nacelle
carmine nacelle
#

(maybe it's some massive skill issue...)

#

(it's not booting on 2 PCs)

#

ahci driver also worked on intel macbook

#

(before I lost interrupts...)

#

Fun statistic: limine passes 107 memory entries on that PC

vale hinge
#

what PC?

#

open an issue? send additional information

#

do you think i have a crystal ball or something lol

wide spruce
#

what does the PM of PMOS mean

vale hinge
#

protected mode

wide spruce
#

really?

carmine nacelle
#

Mikhail and my friend Pau

#

It was a 2 person project

#

(There was pimOS before with Ivan, but it didn't even get to loading its own page tables bruh)

carmine nacelle
#

On 2 PCs

#

Which suggests it's a skill issue on my part

#

So probably false alarm

carmine nacelle
#

Which remaps LAPIC

#

but hyper does work

#

and the image does boot in qemu

vale hinge
#

does it work booting Linux, does it work booting other Limine kernel such as the template or test kernel bundled with the Limine repo?

carmine nacelle
#

limine itself doesn't boot, I see the bios logo and it reboots

#

with bios booting

#

which might suggest that I didn't write it to usb drive properly

vale hinge
#

have you made sure you created the image properly as well?

carmine nacelle
#

it boots in qemu

vale hinge
#

that's not necessarily a guarantee

#

qemu is very lenient

carmine nacelle
#

I do limine/limine bios-install $(DISK_IMAGE) and it says

Physical block size of 512 bytes.
Installing to GPT. Logical block size of 512 bytes.
Secondary header at LBA 0x3ffff.
Secondary header valid.
GPT partition NOT specified. Attempting GPT embedding.
New maximum count of partition entries: 44.
Stage 2 to be located at 0x1a00 and 0x7ffd600.
Reminder: Remember to copy the limine-bios.sys file in either
          the root, /boot, /limine, or /boot/limine directories of
          one of the partitions on the device, or boot will fail!
Limine BIOS stages installed successfully!
vale hinge
#

on some motherboards CSM won't boot GPT images that aren't ISOHYBRID ISOs

#

unless it is an ISO

#

idk you need to be way more specific

carmine nacelle
#

it also fails on a pure bios machine

#

It's a GPT image with 2 partitions

#

fat32 and ext2

vale hinge
#

is the Hyper image also GPT?

#

pure BIOS machines may also fail to boot disks that present GPT disk labels

carmine nacelle
#

Hyper is MBR

vale hinge
#

ok well, that is one difference, you should make sure those 2 things are the same and reevaluate

carmine nacelle
#

with grub

untold pollen
#

Attempt 2

carmine nacelle
#

Does it have EFI?

untold pollen
#

Idk we will see

toxic torrent
#

it does

little smelt
toxic torrent
#

@carmine nacelle @untold pollen check #voice-0

vale hinge
carmine nacelle
#

like i would like to see limine working on that PC

vale hinge
#

can Hyper do GPT on BIOS? for one test that in that case

#

that would be test #1

carmine nacelle
#

Hyper can't

vale hinge
#

@twilit talon accurate?

carmine nacelle
#

I can test mbr + bios

#

also that PC has COM port and 0xb8 for early debugging if that's needed

vale hinge
#

yeah, test #2 would be, as i said above, test Limine with BIOS/MBR

carmine nacelle
#

idk

#

and I have limine repo cloned already

vale hinge
#

also #3 would be to please open an issue with the machine specific and what you've tested so far, just so this issue does not get lost in time if we don't fix it

twilit talon
pearl narwhal
vale hinge
#

:^)

#

i thought up a better replacement

twilit talon
vale hinge
#

well, you're seeing part of it here now, also shrinking and extending images causes issues with it, and so on

twilit talon
#

I didnt read the entire thread

#

But yeah its a hack

carmine nacelle
carmine nacelle
#

i686 port is fun...

carmine nacelle
#

Ok, so the first step of learning the language is porting its standard library ultrameme

#

(my latop is suffering from compiler compilations)

#

(also, I wonder how insane it would get, using 3 languages)

twilit talon
#

which?

left dew
#

Do not port rust

#

i Repeat DO NOT port rust

carmine nacelle
#

why not

wide spruce
#

its a bit of a pita

carmine nacelle
#

Why?

#

rustc already recognizes it

left dew
#

lol you're in for a treat

#

porting the std WILL be fun!

carmine nacelle
#

I had Go kinda working

#

It can't be that hard

#

Will also improve my libc

left dew
#

oh it WILL

#

or will it...

#

idk, all i can say is good luck!

carmine nacelle
#

The osdev wiki article is very bad though

left dew
#

yeah i wonder why

#

(it was probably written by someone who has no idea what they are doing)

carmine nacelle
#

I have no idea what I'm doing

#

somehow it had build stage 0 without my target

left dew
#

i recommend you take a peek at managarm

#

they have rust already

#

and from what i know it's a giant pain in the ass

carmine nacelle
#

I haven't found it

#

(but looked for like 30 seconds)

#

Ok, I think it's trolling me already

#

I've added my target to STAGE0_MISSING_TARGETS and it's pretending it's not there

left dew
#

enjoy :^)

carmine nacelle
#

rust must have changed something

twilit talon
left dew
twilit talon
#

linux abi compat enjoyers win again

wide spruce
#

they already have enough pain

#

let them have this one

carmine nacelle
#

wdym

wide spruce
#

linux abi compat is pain

carmine nacelle
#

linux compat is boring

wide spruce
#

that aside

twilit talon
#

id rather implement namespaces than port rust LULW

carmine nacelle
#

I'm gonna join their discord server

#

I'm sure some people will be thrilled to help...

wide spruce
#

no they wont

wide spruce
carmine nacelle
#

the build system is dumb

toxic torrent
#

bruh

#

what i did once is use mrustc

#

to bootstrap another rustc

carmine nacelle
#

I still have no idea of what's happening

#

I've looked at managarm and redox in the rust code

#

And I have the same stuff as they

#

But no, fuck you, unsupported target

#

also, greping rust tree for error occurred yields nothing, but matches in binary

#

which makes me wonder if that could be coming from llvm

pearl narwhal
toxic torrent
#

if you used mlibc this would be basically free meme

pearl narwhal
#

but it shouldn't be too much worse than idk go probably and go has its own issuds

pearl narwhal
#

you're likely on the wrong server

toxic torrent
#

@carmine nacelle no "error occurred" in llvm

carmine nacelle
pearl narwhal
#

most rustc development happens on zulip

#

the unofficial rust server is what you're looking for

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specifically #os-dev or the rustc-dev thread in #dark-arts

carmine nacelle
#

line 89

pearl narwhal
#

I can send an invite if you want

toxic torrent
carmine nacelle
#

is my llvm patch fucked up?

#

I just use x86_64-pmos normally

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or whatever

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without unknown

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Time to dig through that I guess...

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no, but llvm should be printing error

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it's not coming from there...

carmine nacelle
#

through scientific printfs, I've deduced that it can't find the right C compiler...

carmine nacelle
carmine nacelle
#

How am I supposed to modify it?

carmine nacelle
#

(for a future reference to myself: RUSTC=/home/misha/rust-pmos/build/host/stage2/bin/rustc cargo run -p gen-target-info)

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thonk why don't I also add RISC-V and i686 and aarch64, while at it?

carmine nacelle
#

I think I finally made it recognize pmOS!

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It's even trying to build std

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(I guess it's time for some big time stubbing)

#

(tomorrow)

modest nest
#

i think your problem is that cargo doesnt know about your toolchain

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@carmine nacelle

carmine nacelle
carmine nacelle
#

Inside it

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And pointed std Cargo.lock to use my cc-rs

modest nest
#

do you use a crt0 object?

carmine nacelle
#

I think so

modest nest
#

that might cause the need for cc-rs

carmine nacelle
#

(the wiki is a bit ambiguous)

#

I want it to link against my libc anyway (?)

#

(tbh idk how rust works)

modest nest
#

afaik you have two options either have a crt0 object that inits the stack and stuff or call the entry point directly but you need to do the setup before that

#

you dont need to afaik

#

you could implement your os api directly in rust std without a libc in between

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but usually a system already has a libc so putting rust std on top of that is reasonable

carmine nacelle
#

My libc creates its own thread and manages signals, open files, processes and stuff like that

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So I kinda want it loaded

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(I guess I could reimplement it later fully in Rust)

carmine nacelle
#

Do I have to patch unix crate if I declare pmOS as so?

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*libc

modest nest
#

probably?

carmine nacelle
#

thonk it's not recognizing my target bruh

#

nvm, I'm just dumb

modest nest
#

So it works now?

carmine nacelle
#

Yeah, but I'm filling definitions from my libc atm

#

And there's a lot of them

carmine nacelle
#

Do I even need crt0 objects if in theory my libc should take care of it for me?

left dew
#

they need to be statically linked into every program iirc

carmine nacelle
#

I don't have dynamic linking anyway...

carmine nacelle
#

bruh, rust std wants random generator...

#

(and a bunch of other stuff I don't have yet)

eager rose
#
int
random (void)
{
        return 4; // generated by the roll of a fair dice
}
hexed knot
left dew
#
pub fn random() usize {
  let mut ret: usize = 4;
  #[cfg(target_arch = "x86_64")]
  {
    unsafe {
      core::arch::asm!(
        "rdrand",
        _ = out(ret),
      );
    }
  }
  ret
}```
#

shrimple

eager rose
left dew
#

real...

hexed knot
#

lol

#

i am really curious what the exploit is tbh

#

and also

#

how i can exploit it

left dew
#

insecure hash function

#

probably adding some garbage data and causing a hash collision or some shit

eager rose
hexed knot
hexed knot
#

that microcode doesnt cause a security issue

#

because it doesnt set CF

carmine nacelle
#

But there is no RDRAND on Pentium Pro...

modest nest
#

or just in asm in your code in the std

carmine nacelle
#

I decided not to rant in porting

#

But

#

Very nice of Rust

#

https://pubs.opengroup.org/onlinepubs/9799919799/

The <sys/types.h> header shall define at least the following types:
gid_t
Used for group IDs.
id_t
Used as a general identifier; can be used to contain at least a pid_t, uid_t, or gid_t.
pid_t
Used for process IDs and process group IDs.
...

All of the types shall be defined as arithmetic types of an appropriate length, with the following exceptions:
...
Additionally:
nlink_t, uid_t, gid_t, and id_t shall be integer types.
blksize_t, pid_t, and ssize_t shall be signed integer types.

#

Very nice

#

My ids are all int64_t

toxic torrent
carmine nacelle
toxic torrent
#

looking at the spec, no

carmine nacelle
toxic torrent
#

weird that rust does that then

#

i guess cast it meme

carmine nacelle
#

I can change it to int32_t or whatever, but it's gonna be anoying

#

(I mean the pmOS thing)

#

(Can I complain somewhere? bruhtrl)

toxic torrent
#

/dev/null

carmine nacelle
#

nice

#

Also my getpid can ENOMEM ultrameme

#

But I think that is not allowed

toxic torrent
#

getpid must not fail

carmine nacelle
#

Yeah