#Nyaux
1 messages · Page 29 of 1
china has all my data ngl
idk man i just wanna focus on having good aim instead of ability spam
im fucked
theres no ablitiy that insta kills you
just play the game well and ur good
also theres lit kayo who disables ablities
Cs and valo are like different genres imo
with his knife thing
Cs is a normal shooter val is a hero shooter
just play kayo, disable the enemy teams abilities
done
fair point
Yeah valorants ac is picky as fuck
I have played cs like once with a friend like 5 years ago and I sucked at it
Ok but cs 2 tho
so I just mostly stick to overwatch
Smokes
i used to play ow a lot
Fr
If ow2 actually had a campaign like they promised
zarya or sigma
nah thats abandoned
ow2 is just ow1 but u have battle pass and overpriced skins instead of loot boxes
I know because blizzard fucking sucks at making games
yeah
Ow2 is just ow1 but you have to pay full price for the same game a second time
if u wanna keep up with the skins u have to pay way way more
Easy cash grab
in ow1 u could grind all of them but that was making them less money obv
I mostly play junk + cass (this is from this comp season)
roadhog
ROAD
hog
one shot hook is very enjoyable
oh man
there is also the classic event rn
real??
with the original heroes + abilities
yeah i tried it, but they didnt even bother adding ranked to it lol
WAIT FR
like whats the point lol
OH SHITTTT
LEMEM HOP ON OW2
wait fuck
lemme
first finish up code with the hpet
brb
shouldnt take
5 minutes
Lmao
but classic def feels like a breath of fresh air
Never make promises like that because you’re going to end up spending the next 2 weeks with sleepless nights trying to finish hpet
its like reading 1 register lol
what
bro
hpet is so fucking easy
how the hel
Not specifically hpet
I just have superstition when it comes to saying I’ll complete things in a timely manner
yea i might get stuck
somewhere
but its fine
it wont be as bad
as before
im not gonna be making the same mistakes anyway
and im working on my own time
for the love of god stop speedrunning it
I should make some sort of emulator/virtualizer in crescent so then I can run nyaux inside it 
It’s a leisurely pace if you ask idfk fast people
anyways if u arent keep at it idk
Like Usain Bolt
yea i am not speedrunning
maybe I can get it to usable state before nyaux has bash (likely not lol)
a kvm-like framework?
yes and a virtual machine using it
Average weekend project
I unironically though about that, then I could run actual apps maybe
u can get that up an running in a few months probably
run nyaux
inside
creasant
then inside nyaux bash
creasant 💀
corssiant
no
then inside nyaux
crossiant
then inside crossiant
nyaux
idk if the cpu likes that, would probably have to be software virt at that point lol
then finally run windows for all the apps
Snaps
nested virt is a thing yeah\
to some point yeah but can you arbitrary nest them?
yup
I don’t see why not
each layer would be slower than the previous
cpu dies
because every vmexit would chain
A speed limit inevitably but I don’t see why you wouldn’t be able to just have endless chained vms
while you are it also make all apps their own vm's (with their own os instance)
Yeah, as long as qemu supports emulating vmexit I don’t see why you wouldn’t be able to endlessly chain them
at this point maybe I should make a croissant the crescent logo 
idk what should I seriously make it tho, I though about a crescent moon but idk
have to think about it
proceeds to not do it until its too late and I stop developing it
I’d like to imagine when sys admins get access to a super computer the first thing they do with them before doing like research or breaking encryption of government adversaries is stupid shit like this
it could be a fun experiment yeah
i thought it was a star wars reference
iirc they had something like that
oh yeah looks like it does have all kinds of things that contain that word
I didn't even know that lol
I think I just originally looked at some word list and picked it from there
oh
oh
oh
oh
here
it page faults
cr2 is 0
error code is write to non present page
what i called
i swear if this is another allocator bug
im gonna blow my brains out

this is not how this api works
oh
hpet_table shouldnt be a pointer
what should it be, a non pointer
oh
and then i
yes...
yea i get u
apologies
yea it foudn the hpet
okay works now!
10 nanoseconds
@frigid cliff
got stuck doing the hpet huh
lit
5 minutes
i finished it
lool
69 20 6C 6F 76 65 20 69 74 61 6E 69 75 6D 2A
😡
and i hate u, i play df 😭
i mean for the most part it’s just me being bad 
but it’s staying when u predict a tracer blink or whatever that other thing is
haven’t played this shit in forever i forgot everything
In pmOS, I have a map of { GSI, {CPU ID, Vector} }, which I allocate to a random CPU on first use, or reuse if it's already configured, which should work with interrupt line sharing
(if I bothered to add multiple IRQ per vector in kernel, which shouldn't be difficult...)
😡
satisfying* whoops
typing with one eye closed and 2nd half open doesn't work that well
hi chatji
im having a deep think
about if i should start designing the kernel around smp
or if i should just assume one core for now til bash and then redo everything for smp later
Yes
"So our so-called Lord Ny
aux is a three-meter human male, possibly a Jedi, certainly a Force user, wandering around in a world where it probably doesn't understand anything."
/jk
😭 😭
good point
yeah its good to design with it in mind to start with
im guessing i store anything cpu related in gs
yea fair
I found that in some kind of starwars wiki while I were looking for crescent in there 

ofc not with nyaux but with nyax
Not this again......

kk
@finite summit i think i understand, store a ptr to cpu local shit in gs base
Use the search feature
#1230349543623757845 message
yea cpu_local struct
Look through those couple hours
but i understand this
???
why do i need to look at this a couple of hours if i understand this
😭
yep
write to gs base a ptr to cpu local struct, different for each cpu. im gonna store shit i need for my interrupt shit in there as well
cause yes
Wut
as in
some stuff that is per cpu spefici
i need
to store in it
this garbage, storing ptrs for uacpi handlers and stuff
and also
making this per cpu
Why?
you are unlikely to have so many devices that you'd actually need per-cpu idt
okay
When nyaux abstract IRQs
?
obos just gives uacpi a pointer to a struct irq
Which handles everything
ehhh idrk how to abstract it well
dunno how this works
my irq abstraction is ```cpp
struct IrqHandler {
DoubleListHook hook {};
kstd::small_function<bool(IrqFrame* frame)> fn {};
bool can_be_shared {};
};
void register_irq_handler(u32 num, IrqHandler* handler);
void deregister_irq_handler(u32 num, IrqHandler* handler);
Magic
ummm, u still need a global array to access
yes ```cpp
static DoubleList<IrqHandler, &IrqHandler::hook> IRQ_HANDLERS[256] {};
Eventually
Just wait until I have the willpower to port to aarch64
there are also a lot of fun devices there like reset controllers, clocks and ldos lol (no its not that fun when you have to configure them before you can write a driver for the actual thing you want to use)
wait people store a whole struct in there?
nyaux itanium port when
Soon, I pray
well on systems with many cores and per-queue msis i can see it happening
well yeah its possible but that's unlikely to happen on a "normal" pc
and even if it would happen you could still share irqs at the cost of performance
well sharing msis doesn't really work since they're edge triggered no?
you could just scale down the amount of queues
oh yeah I didn't think about that
I do
why
what do you store there?
alternative approach: share the IDT vector between CPUs
(i considered this, opted against it for now, might change my mind)
that was more aimed at ilobilo :^)
the main reason i opted against it for now, it's hard to design a cross-platform abstraction for this, because some other platforms don't permit something like this
Basically just scheduler shit
Oops
I meant fitting a struct in there instead of a pointer to one
I might have misunderstood
ah well i thought it was obvious that it's a pointer to the struct
I store a pointer to a struct lol
also no self pointer?
how do you get the pointer
rdmsr?
Yes
lol
I wonder what kinda speed increase I could get if I had a self pointer
I do wrmsr and mov gs:[0]
i have one for convenience but i decided to have a struct cpu_locals and put most cpu locals in there
advantage is on most arches you can do a cpu-local-data-register + offset to something important (curthread for instance) load in one instruction
I also though that it might be a good idea to have something actually resembling tls too along with the per cpu struct because it gets kinda messy when you stuff everything including random pools into the cpu struct
I should probably have a self ptr instead of an index used for accessing a global array lol
i think there is strong merit for it, a cpu local struct is still useful so you can put things in there at fixed offsets (no register + other register offset load on riscv)
yeah its certainly useful for generic stuff but there are some misc things that could just be better being on their own
or well putting literally everything inside the struct would work too ofc but it might not be the most cleanest solution
dynamic per cpu allocation useful too (i forgot the use case but i had one in mind)
especially with drivers and stuff
that's a good one
the other option is allocate an array of as many as there are CPUs but that's slightly more tedious
No need to be sorry
I store all this... (and per-CPU interrupt handlers in it) https://github.com/ThatMishakov/pmOS/blob/main/kernel/generic/sched/sched.hh#L73
You BETTER be sorry!!!!!
Only NERDs do their homework and I'm gonna shove you in a locker, nyaux
Oh I read hw as homework
thats probably correct
I read it as both
CPU got too mad with Nyaux
and battery if using a laptop lol
tbh it's actually true with basically all hobby os's, they use a lot of power because of no power management of any kind
Common hobby OS L
OBOS
Has power management
well obos doesnt have fan or power zone management
also cpu power management 
or thermal zone
Yet
Infy
I am in a desert
Thats one way to call UAE
Nice
Interesting
But if you hlt CPU, doesn't it not use energy?
its much deeper than that
u can configure the state the cpu enters on halt
there are many of them
Isn't there also stuff like mwait and monitor on x86
I mean hlt isn’t like deep sleep
that too is important yeah
it can be configured to a state where waking up has a huge latency
Interesting
Does acpi have anything to do with these states
Nvm just remembered you telling me they don’t a couple months ago
nah its unrelated
but iirc u use ACPI to tell the firmware u support that
via _OSC
and it then dynamically loads extra cpu methods
i dont remmeber how these two are related
this stuff
Marker
wait, because of smp
i might need to
wait
because
other cpus are gonna be modifying this
which is like
wait
you just have a lock?
no but
like this is only suposed to be for one cpu
and like
if that
represents one cpus vector space
and then
another cpu modifies that
for something else
things can get fucking weird
😭
how
lemme pull up vscode
i even found what it does
If set, OSPM is capable of independent C1, P state and T state support for each processor for multi-processor configurations.
etc etc
well im not worried for that because this is gonna be happening on the bootstrap cpu anyway
for whatever uacpi does
butttttt
this
this will get modified
yes?
if you have some kind of driver there then yes
cpu
if it's shared then yeah but why would that matter?
the irq is still only going to be triggered on whatever cpu you configure the io-apic/msi to send it to
but i limit myself in the amount of isrs to only 256
so like one cpu
even if theres multiple
yes that's true
thats stupid
but unless you are planning on running on eg. servers its very likely a non-issue
then do it the per cpu idt way 
i can make it so
yes
in gs
base
funny
yes
i need a scheduler like now
so um
let me
wait i need lapic timer
shouldnt be hard
brb
i found a bug
yea wtf
why am i putting 0
in ea
xx
bro wtf is this
sil
lol
Rsi but one byte
Fr
sil ly
idk what to do now

i cant exactly return
as ill only return edx
why does readmsr divide edx and eax
might be because of legacy
you can just combine them tho
how exactly, bitwise or?
yes
kk
edx << 32 | eax
oki
ummmmm
sir
mr
how tf am i supposed to do it then
static inline uint32_t rdmsr(uint32_t msr) {
uint32_t low = 0;
uint32_t hi = 0;
__asm__ volatile ("rdmsr" : "=a"(low), "=d"(hi) : "c" (msr));
uint32_t combined = (low << 32)|hi;
}
cast it to a bigger type first
how do you expect
to shift a 32 bit integer
byu 32
uint32_t combined 💀
okay
yeah that isnt gonna work
sorry i fixed it
static inline uint64_t rdmsr(uint32_t msr) {
uint32_t low = 0;
uint32_t hi = 0;
__asm__ volatile ("rdmsr" : "=a"(low), "=d"(hi) : "c" (msr));
uint64_t combined = ((uint64_t)low << 32)|hi;
return combined;
}
better now
no reason to apologize
okay
alright
BRO GO TO SLEEP 😭
u better
onjly been up fr abtou 12 hroujss
all done
static inline uint64_t rdmsr(uint32_t msr) {
uint32_t low = 0;
uint32_t hi = 0;
__asm__ volatile("rdmsr" : "=a"(low), "=d"(hi) : "c"(msr));
uint64_t combined = ((uint64_t)low << 32) | hi;
return combined;
}
static inline uint64_t wrmsr(uint32_t msr, uint64_t value) {
uint32_t low = (uint32_t)value;
uint32_t hi = (uint32_t)(value >> 32);
__asm__ volatile("rdmsr" : : "a"(low), "d"(hi), "c"(msr));
}
:)
now lapic timer
wrmsr
rdmsr
i dont get it
static inline uint64_t rdmsr(uint32_t msr) {
uint32_t low = 0;
uint32_t hi = 0;
__asm__ volatile("rdmsr" : "=a"(low), "=d"(hi) : "c"(msr));
uint64_t combined = ((uint64_t)low << 32) | hi;
return combined;
}
static inline uint64_t wrmsr(uint32_t msr, uint64_t value) {
uint32_t low = (uint32_t)value;
uint32_t hi = (uint32_t)(value >> 32);
__asm__ volatile("wrmsr" : : "a"(low), "d"(hi), "c"(msr));
}
oh
no my github is rdmsr
goodnighttttt
because i no have scheduler im just gonna do
struct per_cpu_data {
void (*idt_handlers[256])(struct StackFrame *frame);
}
struct per_cpu_data *data = kmalloc(sizeof(per_cpu_data));
wrmsr(GS_BASE, data);
FOR NOW
and i am going to change a LOT of things now with ze idt
and
wait
ill leave the bootstrap cpu alone in how it handles its idt shit
but ill make operations u can perform on this per cpu idt
the idt.c file is just for bootstrap cpu only
what copy pasting does to a mf (we'av all done it before)
lol fr
good design plan chat?
i dunno i'm just lurking in this server in the hopes to passively scrape up enough knowledge to help me when i eventually have enough time and have a strong want to write my own OS
hi chat not feeling up to do much today
but i got some smp working ig
which was cool
im taking my time afterall so no need to speedrun lol
wtf
lollllll
bro
wtf
page fault 0x10???????
HOWWWW
all i hecking do
HOWWWW
wtf

dont tell me its MORE vmm shit
i swear to god
i have a lock on my
fucking flanterm term
RIP IS 0
BTW
RIP IS FUCKING ZERO

stack corruption?
idfk?????
limine is providing the stack sooooo
shouldnt be from that
limine is providing the stack
im using
goto address
yea
are you doing any assembly which might push more than what is popped?
interrupts?
im not even installing any interrupts in the bootstrap function
i didnt do anything
no interrupt is firing
oh wait, are you starting other cpus?
yes
oh I see
haven't seen much of the code. is it safe for bootstrap to return?
WAIT
one second
no its not safe
maybe mark it as noreturn so the compiler complains at you if you forget again
init_smp(): Found CPU 0
init_smp(): Found CPU 1
init_smp(): Found CPU 2
init_smp(): Found CPU 3
init_smp(): Found CPU 4
init_smp(): Found CPU 5
bootstrap(): Hello from CPU bootstrap(): Hello from CPU 2
bootstrap(): Hello from CPU 6
bootstrap(): Hello from CPbootstrap(): Hello from CPU 3
U 51
bootstrap(): Hello from CPU 4
init_smp(): Found CPU 6
init_smp(): Found CPU 7
init_smpbootstrap(): Hello from CPU 8
(): Found CPU 8
init_smp(): Found CPU 9
init_smp(): Found CPU 10
init_smp(): Found CPU 11
init_smp(): Found CPU 12
init_smp(): Found CPU 13
init_smp(): Found CPU bootstrap(): Hello from CPU 14
bootstrap(): Hello from CPU 13
bootstrap(): Hello from CPU 11
bootstrap(): Hello from CPU 7
14
init_smp(): Found CPU 15
init_smp(): Found CPU 16
init_smp(): Found CPU 17
init_smp(): Found CPU 18
init_smp(): Found CPU 19
bootstrap(): Hello from CPU 1bootstrap(): Hello from CPU 19
bootstrap(): Hello from CPU 12
bootstrap(): Hello fr
bootstrap()5
om CPU : Hello from CPbootstrap(): Hello from CPU 9
bootstrap(): Hello from CPU 17
U 10
NYAUX Panic! Reason: 16
bootstrap(): Hello from CPU 18
why is this happening
i have a lock
on my terminal
yep
yea
init_smp(): Found CPU 0
init_smp(): Found CPU 1
init_smp(): Found CPU 2
init_smp(): Found CPU 3
init_smp(): Found CPU 4
init_smp(): Found CPU 5
bootstrap(): Hello from CPU 2
init_smp(): Found CPU 6
init_smp(): Found CPU 7
init_smp(): Found CPU 8
init_smp(): Found CPU 9
init_smp(): Found CPU 10
bootstrap(): Hello from CPU 7
bootstrap(): Hello from CPU 1
init_smp(): Found CPU 11
init_smp(): Found CPU 12
init_smp(): Found CPU 13
init_smp(): Found CPU 14
init_smp(): Found CPU 15
init_smp(): Found CPU 16
init_smp(): Found CPU 17
init_smp(): Found CPU 18
init_smp(): Found CPU 19
bootstrap(): Hello from CPU 17
bootstrap(): Hello from CPU 15
bootstrap(): Hello from CPU 13
NYAUX Panic! Reason: Uhhh yeah wssup
bootstrap(): Hello from CPU 18
bootstrap(): Hello from CPU 8
bootstrap(): Hello from CPU 3
bootstrap(): Hello from CPU 14
bootstrap(): Hello from CPU 10
bootstrap(): Hello from CPU 16
bootstrap(): Hello from CPU 4
bootstrap(): Hello from CPU 9
oopsie uwu :3
bootstrap(): Hello from CPU 11
bootstrap(): Hello from CPU 5
bootstrap(): Hello from CPU 12
bootstrap(): Hello from CPU 19
bootstrap(): Hello from CPU 6
works now
oh ok
(p cores and e cores but yk)
ah
chat my gf is ghosted me WHERE TF IS SHE I WANNA YAP TO HER ABOUT THE FACT I GOT SMP WORKING IN NYAUX
😡
Sorry, she was busy with me while I yapped about MY OS
Is it bc I'm a trans woman? Wow nyaux... I see how it is... /j
linuxmaster on his way to getting banned
wait wheres the /j
but im not transphobic
(/s /j)
is using tone indicators sarcastically evil?
i wonder
BUT NOW
FUCKING
SCHEDULER
TIME
time to read back the thread
im gonna make a document designing and how implmentation
will work
please do not fuck the scheduler
of the nyaux scheduler
😭 😭
nah im not gonna make it UB
or poopy
it will be a per cpu queue scheduler
load balancing later on
if i can learn how that works
you check if the load is unbalanced and if it is, balance it

bru
@surreal path what scheduler design do u use atm
per cpu run queues
my bad was eepying

💀
(interesting life decisions
)
imagine
-# same
Can you not bring a laptop to school?
its not illegal
it may be forbidden by school rules
though then again maybe not
yea
i really have to
school work
so no work on nyaux for a bit (like until friday or smthin)
sounds like a great plan
hi sorry
been busy with school work
not today cause a lot of homework
but tmrw def
:)
Yoyoyooy
I'm in GMT time zone now
In london
Doing osdev at 6 30 am is pretty unhealthy
its fineee
but wtf
its in the fucking file
and i #pragma once every header file
wtf is the issue lmao
wait nvm have an idea
solved it
nvm
solved it
also i decided after a long think
im not doing a per cpu idt
its too complex and just it'd honestly be a waste of time
not rlly complex but
im lazy
damn u going home?
bro
BRO
its lit
0x1b
like seriously
why isnt my fucking bitmask working
it just makes the address 0
0x0
wtf????
bro what

help
Cuz I can be
yeah, and show the code for rdmsr
Yes
okay
static inline uint64_t rdmsr(uint32_t msr) {
uint32_t low = 0;
uint32_t hi = 0;
__asm__ volatile("rdmsr" : "=a"(low), "=d"(hi) : "c"(msr));
uint64_t combined = ((uint64_t)low << 32) | hi;
return combined;
}
uh
why is low being shifted left? are your variables backwards or something
okay that solved everything
what time is it for you?
oh I see
ye

Yes
good to hear! glad u had fun on ur trip
heres what
one of the numbers look like
all look similar
but different
so im def accessing the lapic id register of the lapic
but i dont understand
why im not getting the proper id, even if i bitshift by 24 as per spec from the sdm for xapic even
i dont know what im doing wrong

anyone know?
where do u shift it
sorry for the late reply
was sleeping
but
static inline uint32_t get_lapic_id() {
uint64_t addr = (rdmsr(0x1b) & 0xfffff000);
uint64_t *ptr = (uint64_t *)(addr + hhdm_request.response->offset);
uint32_t val = *(uint64_t *)((uint64_t)ptr + 0x20);
return (val >> 24);
}
i do it here
which results in all lapic ids being 0
mhm
im reading 0x1b
which is the correct msr
for the lapic address
yeaaaa
clearly
not working
Don't you need to enable X2APIC to have MSRs?
yea
i dont have that enabled
Also, according to SDM, you're supposed to be reading 0x802
Then you're supposed to use MMIO instead of MSRs
thats what im doing
Oh
im using mmio and reading lapic addr + hhdm + 0x20
😭 all good man
You're supposed to be reading it as volatile uint32_t *
yea but even doing that doesnt change anything
You're casting uint64_t * to uint32_t *, which is UB
(I've been bitten by it, gcc just issues noop)
I think?
May be not
let me change it
static inline uint32_t get_lapic_id() {
uint64_t addr = (rdmsr(0x1b) & 0xfffff000);
volatile uint32_t *ptr = (volatile uint32_t *)(addr + hhdm_request.response->offset);
uint32_t val = *(volatile uint32_t *)((uint64_t)ptr + 0x20);
return (val >> 24);
}
changed
ill try running it
it solved it
@flat nymph thank you!
can u say always use volatile for mmio
so someone can pin it in this thread
so i never forget
😭
I mean I think it depends
Yeah, volatile means the memory has side effects outside of the C abstract machine - mmio fits that description.
Also yeah the width of an mmio access is important too. The lapic regs are 32bits wide, so you should operate on them in that size (use a volatile uint32_t*)
anyways hi yall
time to work on some lapic init
get it to fire on each cpu
and then
its scheduler
the scary

very spooky
Just don't do UB and you'll be set 
@surreal path some people are using nyaux as a reference
damn, where is this?
cosmos server
I randomly opened it and saw people trying to use uacpi
and they don't understand what "return 100ns increments" means
nope
good thing i got rid of this in the current pr
its now just nanoseconds
so that people dont get confused
lmao
its now just uacpi_kernel_get_nanoseconds_since_boot
surely u cant mess this one up
yeah that's better
(well its not merged yet but soon)
aml uses 100ns ticks internally and i just copied the acpica os interface for it initially
which i shouldnt have done
because acpica interfaces suck ass
Linux switching to uacpi in a year
imo implementation details must be handled by the library instead of coming up with r-worded interfaces
No way that ever goes well
infy about to rewrite uacpi in C#
When uacpi c# bindings
and its wrong anyway because _S5 can be a method returning a package instead of package directly
not to mention _PTS and stuff
Cosmos is an operating system "construction kit". Build your own OS using managed languages such as C#, VB.NET, and more! - CosmosOS/Cosmos
yeah thats where they got that from
have you seen https://github.com/lowlevelmemes/acpi-shutdown-hack ?
this leads to stuff like that
thats the same thing just cleaner, it assumes _S5 is a package and doesnt call _PTS so it will enter most laptops into a UB state
i think it checks if it's a package and just fails if it isn't?
as in gracefully handled
as graceful as it gets yeah
i mean it's better than not checking at all
outw(facp->PM1a_CNT_BLK, SLP_TYPa | (1 << 13));
if (facp->PM1b_CNT_BLK)
outw(facp->PM1b_CNT_BLK, SLP_TYPb | (1 << 13));
This will break on some hw too
u cant just write both at the same time since some hw breaks when that happens
u have to first write the sleep type, and only then the sleep bit
basically yeah, for desktops it will probably work for like 85% of them
a proper ACPI implementation is obviously a much better solution lol
for laptops idk, way less
i actually tested it on many machines of mine and i couldn't find any on which it didn't work (or appear to work, at least)
that said, it's obviously a limited sample
and u tested reboot after this shutdown right?
like, starting them up again? if so, yes
yeah, basically
its UB so ya know how it goes
sometimes it just works ™️
didnt even realize it was your project lol
Since what boot? The init process is run? The kernel is run? The computer is powered on? 
calling it a project is disrespectful to any real project
it's a literal disembodied hack that @vague mural helped me improve a little
not something i'd recommend anyone use
lol
nah its fine for casual use
like for quick testing or emulators
especially if u know it works on your specific hw
@kind root #834060104143208487 message
bruh 💀
Is that cosmos discord?
yes
This is why we can’t have nice things
hi
sorry
im not in the mood
to work on nyaux today
a lot of horrible things happened
another attempt today happened
and i rlly dont feel like doing anything right now for today at least
im sorry
this keeps happening
but
yea.
its hard to be keeping myself stable anymore
its making it difficult to do anything atp
i did finish getting lapic working though
yesterday i did
ill push it later
its ok, take a break if you need to and focus on yourself 🫂
hi
its been 2 days and i think im ready to come back
i feel much better
back to what we were doing
im gonna start writing the scheduler
🤞
Glad to hear that 
interesting
that testing the actual lapic code
gives this
one sec
huh?
now its page faulting
then 0xdf
tf
yea this is wheere things get difficult
with smp
oaky i know whats going on lol
47????
lollll
sorry
this makes no sense
WHY IS IT 47?
doing as asked
and oring it
should just
leave those other bits alone
ugh fine ill cast it into a uint8
AND IT DOESNT WORK
i dont understand?
solved it
*sur_interrupt = 34 | (*sur_interrupt << 8);
wait
wait
wait
wait
wait
Possible spam detected for user: linuxmaster2.0. Please contact a moderator to be unmuted.
surround it in ` so it doesn't format weirdly
Nice to see you back btw, I hope your health has improved since you were sick 🙂
let me think of something
thanks
yea
apic got disabled
yk
yea
you probably should be reading it, anding out the bits you don't need, then oring the vector and APIC enable instead of just writing to it
that's what I was trying to say to do
having some interrupt memes with isr stub 32
fun
i forgot my sleep meds
fuck

GUESS WHO ISNT SLEEPING
TIHSUG UYY
go to sleep
Sleep is for the weak (I slept for 3 hours today)
Are you though
Nevermind me, sorry
You fixed it
I need to eep around 10h a day
eep
do u know whats crazy
AT THE SAME TIME
my gf decided she wanted to see
other people
bro had me crying all night instead
im done with girls bro
genuinely
so intead of useful debugging
i just had a puddle of tears
damn chat
chat i need to make progress
obos is making more progres
s
then im doing in a week
:ratge
😡
this is like
mac vs windows
obos vs nyaux
real
nyaux is windows real
gf haram
girlfriEND Girlfriends have an end
osdev has NO end
