there is more data in the table after the acpi sdt header
#Nyaux
surreal path
OKAY NOW
kind root
Wait acpi_entry_header is a thing?
thorn bramble
in uacpi? yes, acpi_entry_hdr
kind root
Oh right lol
thorn bramble
lmaoo
surreal path
OKAY NOW
so 1 lapic, 1 ioapic, bunch of interrupt service overrides and a local apic nmi
kind root
so 1 lapic, 1 ioapic, bunch of interrupt service overrides and a local apic nmi
Thats correct
surreal path
me trying to read acpi spec trying to understand what iso's are 
thorn bramble
yeah SRAT seems to reference that as well
kind root
Now add more CPUs
thorn bramble
what is SRAT anyway?
kind root
NUMA affinity table
kind root
What memory belongs to what domain etc
kind root
me trying to read acpi spec trying to understand what iso's are <:nooo:750466870...
By default irqs are identity mapped to ioapic, overrides allow the platform to redirect them
surreal path
By default irqs are identity mapped to ioapic, overrides allow the platform to r...
For example, if your machine has the ISA Programmable Interrupt Timer (PIT) connected to ISA IRQ 0, but in APIC mode, it is connected to I/O APIC interrupt input 2, then you would need an Interrupt Source Override where the source entry is ‘0’ and the Global System Interrupt is ‘2.’
yea im seeing 
kind root
Yup
surreal path
and thats what global system interrupts are? interrupts that came from the ioapic i suppose?
is that correct?
kind root
Yeah
unkempt relic
NUMA affinity table
will come in handy for nyaux os
surreal path
do i need to parse something or what
unkempt relic
do i need to parse something or what
parse is a little extreme, it's mostly casting pointers
these overrides tell you what a traditional IRQ's corresponding GSI is
surreal path
parse is a little extreme, it's mostly casting pointers
yes but im so confused like what i need to do next, to like configure the apics or whatevs
surreal path
these overrides tell you what a traditional IRQ's corresponding GSI is
okay then ill just read them i suppose and print them out
kind root
will come in handy for nyaux os
Lol
unkempt relic
what is bus?
which bus the IRQ is said to be from
surreal path
which bus the IRQ is said to be from
ah okay
kind root
Bro
unkempt relic
i shouldn't worry about the bus, i don't even remember that being a field
surreal path
The header has structs for these as well
hm?
unkempt relic
The header has structs for these as well
i saw some structure definitions were added, i will transition to them eventually
kind root
i saw some structure definitions were added, i will transition to them eventuall...
I think I added everything that your average hobby osdever might need, but I will add more eventually
unkempt relic
I think I added everything that your average hobby osdever might need, but I wil...
i look forward to using the SRAT and SLIT definitions in the future
obscene sounding things but what can you do
kind root
I wanna support those from the get go in my os
surreal path
acpi_madt_x
wow i love uacpi
kind root
Will be interesting to design allocators with those in mind
surreal path
okay so 5 isos coming from the legacy isa bus
lets read that irq number and gsi number!
kind root
wow i love uacpi
No need to do case 2, uACPI has enums for those
surreal path
No need to do case 2, uACPI has enums for those
wow
i love uacpi even more
whats the enum called
unkempt relic
i would be using them already but i decided to not be too radical as i've only just, i think, acquired a complete enough understanding of working set model based vmm design to implement a not overly impressive one - but proper NUMA support with per-domain VM management is something i want to do
kind root
whats the enum called
Above the madt definition
kind root
i would be using them already but i decided to not be too radical as i've only j...
Yeah that's definitely interesting
surreal path
these are what the isos look like btw
legacy irq 0 goes to 2
kind root
these are what the isos look like btw
Looks correct
kind root
It overrides polarity and or triggering
kind root
surreal path
😭
tawdry mirage
polarity says whether the irq line has to be high or low for the irq to happen
triggering says whether the irq is triggered by a transition from low to high (or high to low), or whether it's triggered by the line just being in the high (or low) state
unkempt relic
now that i've parsed the isos
you'll need them when you want to establish redirections with the I/O APIC
that will become relevant when you want to handle traditional IRQs
surreal path
ah okay
oooo what is this
👀
global system interrupt base? is this like a table that describes which gsi's go to which vectors?
or smthin
tawdry mirage
every ioapic serves gsis [gsi base, gsi base + ioapic pin count)
surreal path
oh so its memory mapped to the actual gsi pins
okay
what do i do with that lmao
can i like trigger a gsi if i write to gsi base or smthin
thorn bramble
you can use this information to route interrupts to LAPICs
interrupts are triggered externally
you cannot trigger them yourself
surreal path
oh
thorn bramble
that's the sole purpose of the IOAPIC
surreal path
you can use this information to route interrupts to LAPICs
i just put the lapic id into one of the gsis?
and its routed?
thorn bramble
no, you write to the IOAPIC's redirection table
kind root
Read the ioapic spec
surreal path
bruh
surreal path
okay wait
surreal path
kind root
Yes
surreal path
oh okay
surreal path
okay so its a register
i need to select a register in the REGISTER SELECT REGISTER
and then i can write or read from a register with the
WINDOW REGISTER
okay
to access these registers im guessing its ioapic address + FEC0 for the select register
correct?
i think thats correct
can there be multiple io apics?
or is there like only one
?
ionic jetty
Indeed
ionic jetty
can there be multiple io apics?
Yes
ionic jetty
I have tested on 16 and 24 core cpus and they’ve only had one i think
ionic jetty
I can’t comfortably approve you that
But my guess would be that especially high core server cpus are more likely to have multiple
surreal path
im not writing a kernel for server cpus
☠️
maybe if i was linux sure but im not linux
im mr nyaux kernel for poo poo hobbyist os
so the moment i find an ioapic im gonna store the ioapic address as a global variable
and just assume theres only 1
ionic jetty
That works too ig
surreal path
to access these registers im guessing its ioapic address + FEC0 for the select r...
btw @ionic jetty this is correct yes?
kind root
can there be multiple io apics?
Yeah, and often there's two
surreal path
Yeah, and often there's two
for now im just gonna assume theres only one (FOR NOW)
ionic jetty
btw <@1035264194142023752> this is correct yes?
That sounds high tbh
I remeber the ioapic having less regs
surreal path
is what intel says
ionic jetty
I get the ioapic base from acpi
surreal path
yep
ionic jetty
And then IOREGSEL has offset 0
ionic jetty
Maybe the base address for the first apic
surreal path
idk 🤷♂️
ionic jetty
So like first ioapic is at FEC0 0000
kind root
So read it
ionic jetty
The next one at this + 0x1000
And so on
Thats the xy
And then the 00 at the end is what i said
Offset 0
surreal path
The next one at this + 0x1000
but intel says next register is base + 10h?
surreal path
no
surreal path
huh?
surreal path
Are you reading the ioapic spec
yes
ionic jetty
Nice
surreal path
how am i supposed to put it then
ionic jetty
Yes remove the h
ionic jetty
Its intels way of saying this number is hex
ionic jetty
surreal path
okay i made my cool functions for writing to and reading from the ioapic registers
okay uhhhhhh
kind root
Now lapic
ionic jetty
Lapic is the per cpu controller
surreal path
yes i know
finite summit
and get SMP
ionic jetty
And a high precision low overhead per core timer
ionic jetty
what am i supposed to do to the lapic
You write functions to do what we just listed
surreal path
You write functions to do what we just listed
the lapic also has these kind of registers?
lapic spec sheet where?
kind root
the lapic also has these kind of registers?
Read spec
kind root
lapic spec sheet where?
Sdm
ionic jetty
Thats a rare achievement
surreal path
okay i see a bunch of registers
kind root
Yup
surreal path
im guessing its different to ioapic where you can just directly read and write the registers?
kind root
Wdym
surreal path
as in instead of selecting your register in like a register
and writing to a rw register
like the io apic
ionic jetty
No select here
kind root
Yes
ionic jetty
Theres an msr for it too
And the address is most likely to be fixed if i remember correctly
surreal path
okay made some functions that can read and write to a lapic register
okay
uhhhh
whats exactly next?
kind root
Start other cores
tawdry mirage
oh so its memory mapped to the actual gsi pins
no gsi base is the number of the first gsi that is handled by that ioapic
kind root
Or do something else
tawdry mirage
also re multiple ioapics ```
qookie@selenium ~ λ dmesg | grep -i ioapic
[ 0.035325] IOAPIC[0]: apic_id 7, version 33, address 0xfec00000, GSI 0-23
[ 0.035330] IOAPIC[1]: apic_id 8, version 33, address 0xfec01000, GSI 24-55
[ 0.970713] ACPI: Using IOAPIC for interrupt routing
on my laptop
surreal path
no gsi base is the number of the first gsi that is handled by that ioapic
oh get u
only got one
😎
from gsis 0-119
ionic jetty
also re multiple ioapics ```
qookie@selenium ~ λ dmesg | grep -i ioapic
[ 0.0...
How many cpus
tawdry mirage
How many cpus
1 cpu, 6 cores (and 6 threads)
ionic jetty
2 ioapics with 6 cores? Okay
surreal path
Or do something else
like what, if i have a apic_init function what do i do next after i set the ioapic global variable address and stuff
how do i start getting things like irqs or smthin
tawdry mirage
2 ioapics with 6 cores? Okay
i'm pretty sure most amd platforms have 2 ioapics
kind root
Yup
ionic jetty
like what, if i have a apic_init function what do i do next after i set the ioap...
Dont forget to route spurious ints too
kind root
like what, if i have a apic_init function what do i do next after i set the ioap...
Init lapic by setting the spurious vector
surreal path
Dont forget to route spurious ints too
route spurious ints?
surreal path
Init lapic by setting the spurious vector
kk
ionic jetty
or mask them i forgot
surreal path
okay so lapic_base + 0xf0
ima write to it
okay i need to set bit 8 to 1
to enable it?
okay im writing 0x80 to it
which should just be the 8-eith bit that is on
tawdry mirage
try again
surreal path
wdym?
tawdry mirage
you got it wrong
surreal path
oh wait
wrong bit
thats the 7th bit
sec
0x100
no idea whats gonna happen but we will see?
tawdry mirage
you probably want a different vector than 0
surreal path
what
tawdry mirage
the spurious vector?
surreal path
oh i gotta select a vector
uhhhh
0x33 yea!
page faults
bruh
this should be right?
why is bro page faulting
☠️
tawdry mirage
why cast the address to a volatile uint32
tawdry mirage
you're ignoring lapic_base and adding ioapic->address?
tawdry mirage
please turn on -Wall -Wextra -Werror
surreal path
whoopsie
tawdry mirage
-Wpedantic if you're not using gnu extensions
tawdry mirage
what's cr2?
surreal path
huh ??? 
tawdry mirage
hm the first 4GB should be mapped unconditionally
surreal path
hm the first 4GB should be mapped unconditionally
huh
surreal path
okay sec
ionic jetty
hm the first 4GB should be mapped unconditionally
Ive seen that multiple times now
Why is that
I mean yes most devices are there
But like why not map them whenever u need them
tawdry mirage
idk i wasn't there in the room when the limine spec was being written
finite summit
hm the first 4GB should be mapped unconditionally
unless you're using revision 1
ionic jetty
Oh you meant its a limine thing
surreal path
what does `info tlb` say in the qemu monitor
info tlb causes qemu to crash lol
finite summit
then the first 4 gib isn't mapped
tawdry mirage
unless you're using revision 1
the first 4GB is not identity mapped then, it's still mapped into the hhdm
surreal path
im using revision 1
im so confused
why isnt the hhdm working
i mapped like pretty much everything
wicked loom
Limine broke, ask for replacement
wicked loom
already existed
surreal path
when???
wicked loom
we're at Limine 7.x
surreal path
no we need limine uhhh
20.x
uhhh does this look like the end of the hhdm mappings to yall
FFFF8000D0788000 is calculated as the limit of the hhdm
tawdry mirage
sounds broken
or well
your recreated hhdm doesn't match limine's hhdm if you don't map the first 4GB unconditionally
surreal path
your recreated hhdm doesn't match limine's hhdm if you don't map the first 4GB u...
i walk through the memmap
and calculate the hhdm limit through every entry
yea
wicked loom
your recreated hhdm doesn't match limine's hhdm if you don't map the first 4GB u...
but he's using base rev 1
tawdry mirage
yes and on top of all memory map entries, limine also maps the first 4GB unconditionally into the hhdm
tawdry mirage
but he's using base rev 1
the hhdm mapping still exists?
surreal path
yes and on top of all memory map entries, limine also maps the first 4GB uncondi...
what
wicked loom
yes
kind root
but he's using base rev 1
Why doesn't it map the first 4g?
wicked loom
it does
tawdry mirage
rev 1 gets rid of the identity mapping
kind root
Oh
tawdry mirage
not the first 4GB in the hhdm
kind root
Ultra just has a higher-half-exclusive mode in the proto
surreal path
i dont follow u
i am so confused
tawdry mirage
idk how else to word it
limine unconditionally maps [0, 0x100000000) into the hhdm, and on top of that whatever the memory map says
surreal path
limine unconditionally maps [0, 0x100000000) into the hhdm, and on top of that w...
so i gotta map 0 to 0x100000000
correct?
tawdry mirage
if you want to end up with the same hhdm as limine gave you
surreal path
okay
kind root
idk i wasn't there in the room when the limine spec was being written
Thats because on x86 mmio is usually 3-4GiB phys, so it would be very inconvenient to not have it mapped
surreal path
so i gotta map 0 to 0x100000000
but wait
tawdry mirage
alternatively you could just allocate some vm space and map the lapic in yourself, without relying on the hhdm
surreal path
but wait
does the like
the memmap represents physical memory yes?
and like wait
what if a memmap entry represents like
something in that range
0 to 0x100000000
what am i supposed to do in that case
cause currently how i calculate the hhdm limit is like
add 0x1000 to hhdm_limit as i map, looping through each page
tawdry mirage
why do you need the hhdm limit
surreal path
why do you need the hhdm limit
cause i need to represent the hhdm as an allocated virtual address region
unreal hill
limine basically does max(what you did, 0x1_0000_0000)
surreal path
what
unreal hill
always mapping at least 4gb for this exact reason, mmio devices that aren't "real" memory with "real" memmap entries, which live around 4gb on pcs
kind root
So what's the problem exactly
surreal path
okay so i need to calculate the END of the hhdm
kind root
Why dont u have that memory mapped on the higher half
thorn bramble
okay so i need to calculate the END of the hhdm
no, map [hhdm, hhdm + 4G) and then map any memory map entries that are >4G
tawdry mirage
yea
btw do you know that cases can fall through to other cases
you don't need to repeat the body a million times
surreal path
okay i know what to do
it may be stupid but
🤷♂️
i think itll work
easy
😎
and then i can just unconditionally map the lower 4gib
easily and add the hhdm pages
as normal
yea i think this'll work
THIS SHOULD WORK LETS SEE CHAT 😎
oh
okay
um
this did NOT work!
uhhhh
oh wait
lOL ITS ZERO?
WHAT??
😭
wait nvm
okay i think im doing this wrong
i dont know what to do
how tf am i gonna calculate the hhdm limit and map all of this ughhhh
thorn bramble
it's that simple
surreal path
this did NOT work!
like u saw this loop and this loop causes an oom error cause its probs going on forever
kind root
Im detecting big presence of a skill issue
surreal path
😠
thorn bramble
perchance..
surreal path
perchance..
tawdry mirage
please invent a printf ```c
serial_print_color("Region Information!: Base: ", 0);
serial_print(itoah(buffer, cur_node->base));
serial_print(", Length: ");
serial_print(itoah(buffer, cur_node->length));
serial_print("\n");
kind root
please invent a printf ```c
serial_print_color("Region Information!: Bas...
Lmaoo
He literally has one
Since uACPI uses it
surreal path
it worked?
@tawdry mirage i think this is a valid hhdm limit similar to limines??
cause it didnt page fault and now it works?
tawdry mirage
you are winrar
surreal path
winrar?
i am winrar??
wowie !!!!
im winrar guys
😎
okay so it enabled the lapic!
i wrote to the spurcious vector register thingy
and it worked
tho nothing interesting happened
what do i do next now that i've enabled the lapic 😎
uhhh
is there anything else i need to configure or?
tawdry mirage
you want to configure lints as the madt lapic nmi entries say
tawdry mirage
so 1 lapic, 1 ioapic, bunch of interrupt service overrides and a local apic nmi
you literally mention it here
surreal path
you literally mention it here
ok lemme read acpi spec again
This structure describes the Local APIC interrupt input (LINTn) that NMI is connected to for each of the processors in the system where such a connection exists. This information is needed by OSPM to enable the appropriate local APIC entry.
okay
surreal path
you want to configure lints as the madt lapic nmi entries say
nmi is non maskable interrupt right?
tawdry mirage
yes
surreal path
okay so each lapic has 2 lint pins
lint0 and lint 1
so a nmi can be connected to multiple processors as well and stuff
okay
okay so im confused
lol what
oh wait
wrong struct
oh wow
an nmi connected to lint 1
!!
whatever will i do with this information
LOCAL APIC LINT THIS NMI IS CONNECTED TO: 1 FOR PROCESSER ID: FF
this is an nmi for all processors
according to acpi spec
okay
i dont get what im supposed to do with this information? 😭
yes a non maskable interrupt is connected to lapic pin 1 for all processors okay? 😭
i dont get what i have to configure
like huh?
unreal hill
generally it's more useful to start assuming you don't need to care until you do; there's a lot of highly specific information in these tables that won't matter to you at this stage. I'm sure it's possible to generate an NMI in qemu, but I would argue it's almost completely irrelevant to you
surreal path
generally it's more useful to start assuming you don't need to care until you do...
what
tawdry mirage
generally it's more useful to start assuming you don't need to care until you do...
nmi in the monitor iirc
unreal hill
tl;dr: "what do I have to configure?" -> nothing
surreal path
tl;dr: "what do I have to configure?" -> nothing
okay?
so what do i do now ig
i've enabled the lapic
parsed the heckin madt entries ig
set surprious interrupts to vector 33
whats next?
to do?
unreal hill
what was the original goal of this excursion?
surreal path
okay im reading the sdm
says i need to access lapic base + 0x320 register to setup a timer?
okay so i need to set bits 0-7 to my isr handler for a timer ig?
seemingly
okay
now to configure the timer
and try it out
and see if we get an irq
and it handles it
and prints out "tick"
what should i set inital count to?
nothing happened 😔
i think cause its masked?
i dont know how to unmask it tho
sdm doesnt say which bit to set
ok bit 16 is the mask bit
WHY ISNT IT DOING ANYTHING
COME ON DO SOMETHIN
TRIGGER ME INTERRUPT
this should BE riight
😭
surreal path
Why isn’t the lapic timer doing anything like at all
finite summit
Try sending a self ipi to test it via the ICR
Registers
You get to choose the vector
If that doesn't work your LAPIC is initialized incorrectly (maybe check the msr?)
surreal path
Try sending a self ipi to test it via the ICR
Okay wait
surreal path
WHY ISNT IT DOING ANYTHING
But from how it looks Omar am I at least configuring the lapic correctly? I set the divide register to divide by 1, set initial count to 1 and set the vector to 34
finite summit
You misconfigured
Line 71
Where you write to offset 0x320
That isn't how bit logic works
finite summit
The bit isn't set though
Whatever bit is the value you were noting isn't set in 0x34
surreal path
oh right
finite summit
Yeah
And you're setting the value
So it doesn't matter
Ths initial count should be set last btw
That's what starts the timer
finite summit
Yeah then it errored out because vector was likely zero initialized
and it's illegal to send an IRQ to vectors < 32
And it's probably also giving an error when you set all those bits (a lot reserved) in the timer vector register
surreal path
and it's illegal to send an IRQ to vectors < 32
no im setting it to 34
finite summit
Before when you orred those bits
Did rearranging the code and not setting the bits fix anything
?
surreal path
nope
finite summit
Try setting the initial count to 1000
1 is quite fast especially considering you're using an emulator
surreal path
ok
surreal path
finite summit
If they are, check if cr8 is zero (should be if you never touch it)
haughty kite
no thats not how x86 works
surreal path
no thats not how x86 works
😠
why am i not allowed to put the value of rflags into i
haughty kite
because thats not how x86 works
surreal path
because thats not how x86 works
what am I not allowed to access non general purpose registers or something
your not telling me why
haughty kite
what am I not allowed to access non general purpose registers or something
not in this way no
and also thats not how at&t syntax works
and if you are using -Mintel.. just no
surreal path
not in this way no
Then am I supposed to read the rflags register
rigid fable
Then am I supposed to read the rflags register
push rflags, pop rax, get rax into a variable via =m in the output
rigid fable
Use sti
I thought that for some reason he was trying to read rflags, not really read the entirr convo
rigid fable
Then am I supposed to read the rflags register
I probably read this wrong
surreal path
He wants to set if
I’m did
And nothing happens still
Sorry I was at school
Executing sti does nothing
before setting up apic
and cr8 is 0xe
surreal path
All of it?
surreal path
okay im back
from school
yea uhhh
BRO CR8 IS ZERO WTF
😭
WORK U DAMN STUPID TIMER
GRRR
the lapic timer is a meanie
wtf
thorn bramble
what do you expect to be in cr8?
also you are moving to cr8
of course it's gonna be 0
thorn bramble
what significance does cr8 have here??
type info lapic into qemu monitor
see if it's configured correctly
surreal path
that should mask out irq 34
cr8 was 0xe
which masks out irq 34
so i have to set it to zero
thorn bramble
weird
surreal path
type `info lapic` into qemu monitor
okay
tf
WHY IS THE TIMER MASKED AND WHY IS IT SET PERIODIC AND WHY IS IT VECTOR 5😠
thorn bramble
surreal path
hm?
surreal path
i clearly setup the surpious vector register
thorn bramble
IRR is not set
surreal path
IRR is not set
irr?
surreal path
how do you configure the timer?
after i enable the lapic i set the timer to divide by 1
then i set the vector of the lvt timer to vector 34
thorn bramble
show the values
surreal path
okay
thorn bramble
you write to the lapic registers
surreal path
write_lapic_register(madt->local_interrupt_controller_address, 0xf0, 0x100 | 33);
serial_print("enabled lapic?\n");
// enable lapic timer?
// divide by 1
write_lapic_register(madt->local_interrupt_controller_address, 0x3e0, 7);
// set vector to 34
write_lapic_register(madt->local_interrupt_controller_address, 0x320, 34);
// set inital count?
lapic_addr = madt->local_interrupt_controller_address;
write_lapic_register(madt->local_interrupt_controller_address, 0x380, 1);
no no it was part of my previous message
surreal path
what im confused
thorn bramble
show the values...
...you write to the lapic registers
surreal path
```C
write_lapic_register(madt->local_interrupt_controller_address, 0xf0, 0x100 ...
thats the values ^
thorn bramble
you are configuring lapic timer to be one-shot btw
surreal path
yea ik
thorn bramble
and it's going very slow
surreal path
okay but
surreal path
interrupt request register
what is that????
thorn bramble
oh right, i totally forgot about that
i have no idea if it's significant or not
but for me it's set to what i believe is my timer interrupt vector
¯_(ツ)_/¯
thorn bramble
i have no idea but that value is put there if i write to the LVT timer register
surreal path
weird
thorn bramble
writeRegister(.LvtDivide, 3);
writeRegister(.LvtTimer, @as(u32, timer_vector.?));
writeRegister(.LvtInitialCount, 0x5000);```i write those values
LvtDivide being 0x3e0, LvtTimer being 0x320 and LvtInitialCount being 0x380
can you show your write_lapic_register?
surreal path
writing those values did nothing
sure
volatile void write_lapic_register(uint32_t lapic_base, uint8_t reg_offset, uint32_t data)
{
*(volatile uint32_t*)(lapic_base + reg_offset + hhdm_request.response->offset) = data;
}
why?
thorn bramble
idk, ask someone who knows more than i do
surreal path
thorn bramble
all i know is that you should use the msr, but it should be the same
surreal path
idk, ask someone who knows more than i do
okay
thorn bramble
well that's good at least
thorn bramble
can you add -trace apic_mem_write* to your qemu command line
surreal path
can you add `-trace apic_mem_write*` to your qemu command line
okay
thorn bramble
apic_mem_writel 0xf0 = 0x000001ff
apic_mem_writel 0x3e0 = 0x00000003
apic_mem_writel 0x320 = 0x00000020
apic_mem_writel 0x380 = 0x00005000```i get this when configuring my lapic + lapic timer
surreal path
apic_mem_writel 0xf0 = 0x00000121
enabled lapic?
apic_mem_writel 0xe0 = 0x00000003
apic_mem_writel 0x20 = 0x00000022
apic_mem_writel 0x80 = 0x00005000
which is writing to the spurious vector register, lvt divide, lvt timer and lvt initial count
well
that's not looking good
surreal path
tf
thorn bramble
```C
volatile void write_lapic_register(uint32_t lapic_base, uint8_t reg_offset,...
oh
dumbass
uint8_t
surreal path
OH
☠️
OH
uint16
apic_mem_writel 0xf0 = 0x00000121
enabled lapic?
apic_mem_writel 0x3e0 = 0x00000003
apic_mem_writel 0x320 = 0x00000022
apic_mem_writel 0x380 = 0x00005000
well um
thorn bramble
that's a little better
thorn bramble
you can -trace apic_local_deliver*
surreal path
kk
thorn bramble
to figure out if its firing any interrupts
thorn bramble
i get a bunch of apic_local_deliver vector 0 delivery mode 0 apic_local_deliver vector 0 delivery mode 0 apic_local_deliver vector 0 delivery mode 0 apic_local_deliver vector 0 delivery mode 0
so yeah the same for you
-d int then
surreal path
kk
thorn bramble
maybe you're not registering an interrupt handler properly?
lol
idk at this point
but it seems to be firing
oh
its one shot
surreal path
yea its one shot?
thorn bramble
maybe it fires before you get a chance to unmask it
but i think if you set cr8 to 0 and there's any pending interrupts they should fire anyway
surreal path
but i think if you set cr8 to 0 and there's any pending interrupts they should f...
i do sti and i do set cr8 to 0 before ANYTHING
thorn bramble
if they were pending due to the cr8 masking them that is
surreal path
the last thing i do is set inital count
thorn bramble
try a periodic timer
surreal path
kk
thorn bramble
anything when you use -d int?
thorn bramble
interesting
surreal path
yea doing -trace apic_local_deliver*
shows
its sending interrupts
spamming my stdio
oh
thorn bramble
oh?
thorn bramble
oh rip
thorn bramble
well the idt shouldn't have anything to do with the interrupts not arriving
surreal path
yea
thorn bramble
are you messing with the PIC/PIT/IOAPIC?
surreal path
are you messing with the PIC/PIT/IOAPIC?
ioapic yes?
surreal path
no wait no im not doing anything with the ioapic
thorn bramble
hm ok then
surreal path
so like wtf
thorn bramble
confused
surreal path
will i post my code onto github or smth
cause idk
why the interrupts
arent arriving
its sending interrupts
the lapic looks configured correctly
whats going on
thorn bramble
i am not able to help even
qemu trace clearly tells you that the apic is trying to deliver interrupts
surreal path
my kernel is cursed
thorn bramble
but something is preventing them from reaching the cpu
surreal path
but something is preventing them from reaching the cpu
yea 😭
is it a limine thing idk
about
thorn bramble
can you try using 0xff as the spurious interrupt vector?
surreal path
or smthin
thorn bramble
no its not
surreal path
can you try using 0xff as the spurious interrupt vector?
ok
thorn bramble
or it shouldn't be
surreal path
can you try using 0xff as the spurious interrupt vector?
does nothing
thorn bramble
hm ok well it was worth a try
thorn bramble
one more difference is that your lvt0 is configured as edge triggered and for me it's configured as level triggered
idk how it all works, but i can see that it's a difference
surreal path
idk how it all works, but i can see that it's a difference
yea but this shouldnt rlly do anything
i should still be getting an interrupt
at the very least
😭
idk what to do
surreal path
im banging my head againist the wall with this issue
like bro
why wont bro just
receive the heckin interrupt
😭
surreal path
show eflags
kk
surreal path
show eflags
9th bit is off
001001000110 is the binary of 0x246
@finite summit
triggering the timer irq interrupt i have setup in my idt manually works fine
meaning that idt is configured correctly
surreal path
yea
surreal path
send an EOI
okay
finite summit
if that fixes it, someone forgets to send an EOI
tawdry mirage
how fast does current_count go up? (down?)
surreal path
how fast does `current_count` go up? (down?)
quite fast
surreal path
if that fixes it, someone forgets to send an EOI
sent one
void send_lapic_eoi()
{
write_lapic_register(lapic_addr, 0xb0, 1);
}
before enabling the lapic
nothing happened
surreal path
quite fast
to the point it spams my terminal when tracing each interrupt the apic sends in qemu
unreal hill
do you have the vector set up as an interrupt or trap gate? you could be getting so many interrupts it never gets to print anything. You could also up the interval so you get fewer interrupts
surreal path
do you have the vector set up as an interrupt or trap gate? you could be getting...
interrupt gate
thorn bramble
are you using kvm?
surreal path
no
thorn bramble
welp
surreal path
-accel tcg
thorn bramble
just making sure
anything !tcg would make it so -d int doesnt print anything
or at least kvm, cant say for sure for other
surreal path
this makes zero sense
in why the cpu
isnt getting any interrupts at all
from the apic
@sudo qemu-system-x86_64 $(IMAGE_NAME).iso -M q35 -bios /usr/share/edk2-ovmf/OVMF_CODE.fd -m 3G -accel tcg -serial stdio
my qemu command
surreal path
https://pastebin.com/kgaDRuTf my whole apic.c
tawdry mirage
irr = 34 seems curious
finite summit
That means the LAPIC has that irq in it's queue
but something is blocking it from getting sent
surreal path
https://pastebin.com/kgaDRuTf my whole apic.c
you can see clearly i do sti
so i can get interrupts
what other thing could possibly block it???
is it something with limine?
finite summit
TPR in the LAPIC
surreal path
tpr?
finite summit
Task Priority Register
finite summit
also if the LAPIC is waiting for an EOI
thorn bramble
he's not getting an interrupt to begin with
surreal path
he's not getting an interrupt to begin with
^^^
i mean i can try reading the tpr and see the value
surreal path
`asm("mov %0, %%cr8" : "=r"(i));` this is wrong
what?
thorn bramble
it is definitely broken, but if he compiles in debug it's probably moving 0 to cr8 anyway
you are moving from reg to cr8
but you are telling gcc you are reading to the register
asm("mov %%cr8, %0" : "=r"(i));
this is how you read out of cr8 to i
thorn bramble
it is definitely broken, but if he compiles in debug it's probably moving 0 to c...
since he initializes it to 0 beforehand
oh nvm if it's debug then it's probably on the stack and the register will contain garbage
thorn bramble
yea he adopted the same garbage values i use in zigux
i even have a big ass troll face in the source code right above it
tawdry mirage
you want 0xB not 0x3, because the value is _X__ not ___
thorn bramble
i used 0x3 with initial count of 5000 because it gave me roughly what i was looking for, apparently setting lvt divide to 0x3 gives you a divisor of 16
professional lapic timer calibration
surreal path
uhhh weird results
oh yeah cause we end at _start and disable interrupts and just hlt
BUT IT WORKS!!!!
thorn bramble
also you are moving to cr8
i like how i spotted the broken inline assembly 3 hours ago but i didn't care about it because i miscompiled the code in my head
life could've been easier
also you're supposed to write 0 to the eoi register
not 1
surreal path
you want 0xB not 0x3, because the value is `_X__` not `___`
what
thorn bramble
i think so at least, i remember reading about this somewhere
tawdry mirage
and yet the comment says divide by 1
surreal path
oh yeah
tawdry mirage
make up your mind
surreal path
i changed it
lol
well now this epic gamer timer is working
do i hook it up to my scheduler for funny shanngains or what
wait ill need to like "calibrate" the timer
lol
uhhhh
how do i make the timer "calibrated" so the timer ticks at like
a proper value
that is quantifiable and not just random number 1000 divide by 1
tawdry mirage
you compare how fast it ticks against a different timer :^)
surreal path
bruh
☠️
i remember someone talking about the hpet
uhhh
i guess ill try and use that?
(i have absolutely no idea how im gonna "calibrate")
thorn bramble
hpet tells you how fast it ticks
you can measure how many lapic ticks elapse in a certain amount of time by polling the hpet
you pick that amount of time, the longer the better (more accuracy)
but you also dont want it to be too long for obvious reasons
surreal path
you can measure how many lapic ticks elapse in a certain amount of time by polli...
okay so do i set the lapic timer to be one shot, messure the hpet, wait for the lapic timer to fire an interrupt, once its interrupted i messure the hpet and thats the timer calibrated?
thorn bramble
no, you mask the lapic timer and read it's counter value
surreal path
oh
surreal path
kk
surreal path
what should i set the divider to?
thorn bramble
you set the lapic timer up as one shot, mask it, mark starting hpet tick count, set lapic timer ticks very high (0xffffffff or something, idk) wait for a certain amount of time to pass, mark current lapic counter, check how many ticks elapsed (0xffffffff - current) and save that somewhere so you can accurately configure it in the future
thorn bramble
what should i set the divider to?
probably 1 is the best
surreal path
okay
thorn bramble
it's your choice
surreal path
// set vector to 34 , ONE SHOT, MASK IT
write_lapic_register(lapic_addr, 0x320, 34 | (1 << 15));
okay
ill set inital count to somthin like
uhhh
0xffffffff
okay ill use trusty handy dandy uacpi to scan for the hpet table
btw i love u copyobject abuser for making uacpi
its SO much better then lai
thorn bramble
The APIC timer frequency will be the processor’s bus clock or core crystal clock frequency (when TSC/core crystal
clock ratio is enumerated in CPUID leaf 0x15) divided by the value specified in the divide configuration register
you might want to set the divide to 2/4, depending on how fast the clock actually is 
surreal path
wha
plush hearth
I noticed that divide by 1 can be very inconsistent on QEMU
thorn bramble
yeah you probably want to use a higher divisor then
surreal path
> The APIC timer frequency will be the processor’s bus clock or core crystal clo...
dunno what this means or why I have to use a higher divisor but I’ll do that cause u said so !!
thorn bramble
the apic timer ticks at the speed of the bus clock divided by what you configure
surreal path
oh that’s makes more sense lmao
thorn bramble
right
thorn bramble
yeah
surreal path
is it like a register thing with hpet as well