uACPI - a portable and easy-to-integrate ACPI implementation | Operating System Development | Page 67

crude summit Apr 30, 2026, 2:17 PM

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you could probably lift that file verbatim into your code and just implement the serial writer functions, it uses a preallocated memory region

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otherwise calling an allocator during profiling would be death

fiery ice Apr 30, 2026, 2:18 PM

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i send it via serial after i finish rn

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how do i make a flamegraph from your output btw

crude summit Apr 30, 2026, 2:35 PM

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fiery ice how do i make a flamegraph from your output btw

i dont do it by hand, kcachegrind does that sort of stuff

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and lots more

fiery ice Apr 30, 2026, 2:36 PM

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crude summit i dont do it by hand, kcachegrind does that sort of stuff

oh it's an app

crude summit Apr 30, 2026, 2:36 PM

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this is a big wheel i didnt want to reinvent

fiery ice Apr 30, 2026, 2:36 PM

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i tought you had a script

crude summit Apr 30, 2026, 2:36 PM

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yeah, an open source program

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the serial port output just redirects to a file called callgrind.out and that can parse it

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back later, work time

frank canopy Apr 30, 2026, 2:51 PM

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actually started thinking about this too when I saw the mention of rapid free and allocation of small things

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esp because zig has a lockless thread safe arena in the std

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(thread safe as long as it's backing is anyway)

loud ice Apr 30, 2026, 3:31 PM

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i mean you could also try allocating less trl

crude summit Apr 30, 2026, 3:33 PM

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allocate one huge arena and divvy it out

loud ice Apr 30, 2026, 3:33 PM

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dont

crude summit Apr 30, 2026, 3:33 PM

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I mean I give uacpi it's own standalone buddy arena anyway

loud ice Apr 30, 2026, 3:33 PM

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big allocations are harder to cover

crude summit Apr 30, 2026, 3:34 PM

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I think I give it 4mb

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it doesn't use anywhere near that

loud ice Apr 30, 2026, 3:35 PM

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imo you can get more from a better interpreter and better allocator usage than you can from a better allocator

flat badge Apr 30, 2026, 3:38 PM

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optimizing acpi interpreters for speed is useless

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it's better to optimize for stability

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that is, less code that can break and simpler code

loud ice Apr 30, 2026, 3:39 PM

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flat badge it's better to optimize for stability

100%

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and the warmup path is even more useless

crude summit Apr 30, 2026, 3:41 PM

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I don't really care how long it takes so long as it's not noticeable

loud ice Apr 30, 2026, 3:41 PM

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its already not

crude summit Apr 30, 2026, 3:42 PM

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in the grand scheme of things uacpi startup is a fraction of a hundredth of a percent of startup time (and startup time is already under 2s and dominated by a pci scan)

jaunty fox Apr 30, 2026, 4:14 PM

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great news for uacpi and for its users

fiery ice May 1, 2026, 3:50 PM

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@crude summit how do i see the graph?

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oh found it

crude summit May 1, 2026, 3:53 PM

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fiery ice <@189759562910400512> how do i see the graph?

having fun? 😊

fiery ice May 1, 2026, 3:53 PM

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lol

crude summit May 1, 2026, 3:53 PM

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seeing proper profile data for my os was a huge eye opener, I increased my performance 10x

fiery ice May 1, 2026, 3:54 PM

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i'll re-enable the log instrument

crude summit May 1, 2026, 3:54 PM

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8% of your time spent logging

fiery ice May 1, 2026, 3:54 PM

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nah, that's just flanterm

crude summit May 1, 2026, 3:55 PM

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yes .flanterm from your log function

fiery ice May 1, 2026, 3:55 PM

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nope

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part of it

hallow marten May 1, 2026, 3:55 PM

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You should try sampling rather than instrumenting

fiery ice May 1, 2026, 3:55 PM

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wdym sampling?

crude summit May 1, 2026, 3:56 PM

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you sure?

hallow marten May 1, 2026, 3:56 PM

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fiery ice wdym sampling?

sampling

crude summit May 1, 2026, 3:56 PM

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hallow marten You should try sampling rather than instrumenting

sampling doesn't give you a full picture only a sample data set, a subset

hallow marten May 1, 2026, 3:56 PM

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yes but instrumenting is slow

crude summit May 1, 2026, 3:56 PM

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and?

hallow marten May 1, 2026, 3:56 PM

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Doesn't necessarily represent real runtime

crude summit May 1, 2026, 3:56 PM

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if he's using my code it's not that slow

hallow marten May 1, 2026, 3:56 PM

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I'd say it's best to mix both

crude summit May 1, 2026, 3:57 PM

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everything is equally slower

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so the percentages are correct

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all the profiler hooks are O(1) or close to

hallow marten May 1, 2026, 3:57 PM

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crude summit so the percentages are correct

It's not just about the percentages but finer CPU details

crude summit May 1, 2026, 3:58 PM

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you could mix both just don't profile your sampler

hallow marten May 1, 2026, 3:58 PM

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Yeah or like do a sampled run and an instrumented run

fiery ice May 1, 2026, 4:01 PM

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crude summit you sure?

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seems like it didn't finish writing yet

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here is the full one

frank canopy May 1, 2026, 4:05 PM

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thats a lot of putchar

fiery ice May 1, 2026, 4:05 PM

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yeah

fiery turtle May 1, 2026, 4:05 PM

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fiery ice

Me when the entire profile is logging

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Maybe disable logging completely when profiling?

fiery ice May 1, 2026, 4:05 PM

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fiery ice May 1, 2026, 4:05 PM

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fiery turtle Maybe disable logging completely when profiling?

true

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and here it is

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and my alloc seems pretty good rn

fiery turtle May 1, 2026, 5:06 PM

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there are a lot of redudant deep copies in the interpreter that cause extra allocations

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but they arent easy to get rid of

hallow marten May 1, 2026, 5:06 PM

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yes they are

fiery turtle May 1, 2026, 5:06 PM

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since id need to know whether an object is a prvalue or not

fiery turtle May 1, 2026, 5:07 PM

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hallow marten yes they are

are u an aml expert now lmfao

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but tbh even as is it gets 10M ops/s

hallow marten May 1, 2026, 5:07 PM

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fiery turtle are u an aml expert now lmfao

They’re honestly pretty easy to deal with once you look at them the right way. Most of those deep copies aren’t fundamentally required—they’re usually just there for safety or convenience. In a lot of cases, you can replace them with shallow copies, references, or move semantics without changing behavior.

fiery turtle May 1, 2026, 5:08 PM

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which is miliseconds even on most bloated aml

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most bloated aml is like maybe 30k ops total

fiery turtle May 1, 2026, 5:08 PM

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hallow marten They’re honestly pretty easy to deal with once you look at them the right way. M...

lol

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go fix them make no mistake

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also switching to computed gotos is a possibility for increasing perf

hallow marten May 1, 2026, 5:16 PM

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I dont think computed gotos even do anything nowadays

fiery turtle May 1, 2026, 5:17 PM

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nah i saw some example recently where they had some simple bytecode interpreter

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and computed gotos boosted perf by a lot

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it was all tail call based

hallow marten May 1, 2026, 5:18 PM

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was it a recent example

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cuz I think I know what you're talking about

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but that post is pretty old

fiery turtle May 1, 2026, 5:18 PM

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maybe

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right now when microcode ops call into C it uses a dispatch table of function pointers

hallow marten May 1, 2026, 5:19 PM

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ah yeah thats probably not good

fiery turtle May 1, 2026, 5:19 PM

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yeah

craggy epoch May 1, 2026, 6:22 PM

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@fiery turtle Here's the ACPI dump from the CIX P1

📎 CIX_P1_OP6Plus_ACPI.txt

fiery turtle May 1, 2026, 6:23 PM

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thanks

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cool arm with proper acpi

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how it should always have been

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looks like power state transitions still require prorietary drivers tho

loud ice May 1, 2026, 6:35 PM

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fiery turtle looks like power state transitions still require prorietary drivers tho

i thought that on arm this was done with psci?

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which is as much of a proprietary driver as SMM

fiery turtle May 1, 2026, 6:35 PM

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yeah maybe idk, its not indicated by acpi

loud ice May 1, 2026, 6:35 PM

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the arm equivalent(ish) of smm has a defined api boundary

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you use it for AP startup and power management and shit

vast kestrel May 1, 2026, 6:36 PM

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Is it possible to invoke a psci via aml even

fiery turtle May 1, 2026, 6:36 PM

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like technically acpi has a proper power management spec for reduced hardware

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but its not used here

vast kestrel May 1, 2026, 6:36 PM

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Smi you can cause it's port Io

loud ice May 1, 2026, 6:36 PM

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fiery turtle like technically acpi has a proper power management spec for reduced hardware

how does that work

vast kestrel May 1, 2026, 6:36 PM

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But isn't psci done via some special opcode

loud ice May 1, 2026, 6:36 PM

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actually sounds interesting

fiery turtle May 1, 2026, 6:36 PM

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loud ice how does that work

via a generic address space register

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it can be any address space they want

loud ice May 1, 2026, 6:37 PM

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hmm does linux support that

fiery turtle May 1, 2026, 6:37 PM

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yeah

loud ice May 1, 2026, 6:37 PM

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also how does the whole interface work, anyway

loud ice May 1, 2026, 6:37 PM

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loud ice hmm does linux support that

i wonder if you could use this to implement sleep states etc on apple (where you dont have psci)

fiery turtle May 1, 2026, 6:37 PM

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u read the magic values to write into the register from the state object, e.g. _S5 for state 5

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then run _PTS, then write them into the register

loud ice May 1, 2026, 6:37 PM

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fiery turtle u read the magic values to write into the register from the state object, e.g. _...

ok sure but when does native code execution enter firmware

fiery turtle May 1, 2026, 6:38 PM

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multiple ways

loud ice May 1, 2026, 6:38 PM

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on x86 this works with smm

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but idk if there is a "plz jump to physical address 0x4141424243434444 with no paging now" aml op

fiery turtle May 1, 2026, 6:38 PM

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generic address register has a way to specify hardware-specific address space, which could mean call into firmware with that instruction

loud ice May 1, 2026, 6:38 PM

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ok sure but that would require kernel support anyway

fiery turtle May 1, 2026, 6:39 PM

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yeah ofc

loud ice May 1, 2026, 6:39 PM

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there isnt anything generic ig?

fiery turtle May 1, 2026, 6:39 PM

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nothing to call into the psci i dont think

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but i could be wrong

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these are the defined address spaces

#define ACPI_AS_ID_SYS_MEM       0x00
#define ACPI_AS_ID_SYS_IO        0x01
#define ACPI_AS_ID_PCI_CFG_SPACE 0x02
#define ACPI_AS_ID_EC            0x03
#define ACPI_AS_ID_SMBUS         0x04
#define ACPI_AS_ID_SYS_CMOS      0x05
#define ACPI_AS_ID_PCI_BAR_TGT   0x06
#define ACPI_AS_ID_IPMI          0x07
#define ACPI_AS_ID_GP_IO         0x08
#define ACPI_AS_ID_GENERIC_SBUS  0x09
#define ACPI_AS_ID_PCC           0x0A
#define ACPI_AS_ID_FFH           0x7F
#define ACPI_AS_ID_OEM_BASE      0xC0
#define ACPI_AS_ID_OEM_END       0xFF

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but i mean psci eventually does some mmio writes and stuff anyway right

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that could be expressed in aml

loud ice May 1, 2026, 6:41 PM

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fiery turtle but i mean psci eventually does some mmio writes and stuff anyway right

well usually you arent allowed to access that

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because the cpu resets into the secure monitor

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so if you could control the reset vector that would be bad™

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but anyway i dont think there is even any way to make acpi sleep work on arm

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other than with psci

fiery turtle May 1, 2026, 6:42 PM

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ah yeah i guess because of protections u cant yeah

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ig

loud ice May 1, 2026, 6:43 PM

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although i wonder if you could hack together an acpi table that would make acpi sleep work on m1

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would be so jank

fiery turtle May 1, 2026, 6:44 PM

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does apple stuff also rely on that for shutdown?

loud ice May 1, 2026, 6:44 PM

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apple has magic drivers

fiery turtle May 1, 2026, 6:46 PM

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wdym

loud ice May 1, 2026, 6:46 PM

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apple doesnt use psci at all

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and you cant make it work on apple hw without losing virt

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which is more important

fiery turtle May 1, 2026, 6:47 PM

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I guess that should be easy to express in aml then?

loud ice May 1, 2026, 6:48 PM

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i dont know if it is no

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i suspect the answer is more like "yeah no" though

fiery turtle May 1, 2026, 6:48 PM

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Lol

fiery turtle May 1, 2026, 6:49 PM

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loud ice and you cant make it work on apple hw without losing virt

U mean it needs el2 or smth?

loud ice May 1, 2026, 6:49 PM

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psci needs either el2 or el3

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virt needs el2

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and you cant use either for both at once

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oh and apple doesnt implement el3

fiery turtle May 1, 2026, 6:49 PM

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Why does virt need el2

loud ice May 1, 2026, 6:51 PM

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fiery turtle Why does virt need el2

thats just how virt works on arm

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x86 virt requires you to be outside of a vm too

fiery turtle May 1, 2026, 6:52 PM

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Yeah so you can run the kernel in el2 and run aml there too

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And virt runs in el1 no?

loud ice May 1, 2026, 6:53 PM

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virtualized code runs in el1

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yes

loud ice May 1, 2026, 6:53 PM

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fiery turtle Yeah so you can run the kernel in el2 and run aml there too

yes but i dont know if linux can do acpi suspend on arm at all tbh

fiery turtle May 1, 2026, 6:55 PM

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Well at least shutdown would be nice

loud ice May 1, 2026, 7:09 PM

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they have some kind of hack that makes it work without acpi

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and without psci

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ah its not a hack

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i think the jank is that it cant do suspend or smth idr

fiery turtle May 1, 2026, 7:16 PM

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is there like an adhoc driver for that in asahi

loud ice May 1, 2026, 7:16 PM

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its upstream

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for poweroff at least

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i dont think you could make that really work with aml tbh

and even if you could, aml is shit as a programming language lol

fiery turtle May 1, 2026, 7:17 PM

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Can you show it

loud ice May 1, 2026, 7:17 PM

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well so its two drivers

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driver one does a bunch of shit and then this: ```c
static int macsmc_power_off(struct sys_off_data *data)
{
struct macsmc_reboot *reboot = data->cb_data;

dev_info(reboot->dev, "Issuing power off (off1)\n");

if (apple_smc_write_u32_atomic(reboot->smc, SMC_KEY(MBSE), SMC_KEY(off1)) < 0) {
    dev_err(reboot->dev, "Failed to issue MBSE = off1 (power_off)\n");
} else {
    mdelay(100);
    WARN_ONCE(1, "Unable to power off system\n");
}

return NOTIFY_OK;

}

fiery turtle May 1, 2026, 7:17 PM

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loud ice i dont think you could make that really work with aml tbh and even if you could...

Its good you just have to know what code to avoid writing to prevent acpica from segfaulting trl

loud ice May 1, 2026, 7:18 PM

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fiery turtle Its good you just have to know what code to avoid writing to prevent acpica from...

lmfao

fiery turtle May 1, 2026, 7:18 PM

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loud ice driver one does a bunch of shit and then this: ```c static int macsmc_power_off(...

Is that just an mmio write?

loud ice May 1, 2026, 7:18 PM

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apple_smc_write_u32_atomic is ```c
int apple_smc_write_atomic(struct apple_smc *smc, smc_key key, const void *buf, size_t size)
{
guard(spinlock_irqsave)(&smc->lock);
u8 result;
int ret;
u64 msg;

if (size > SMC_MAX_SIZE || size == 0)
    return -EINVAL;

if (smc->boot_stage != APPLE_SMC_INITIALIZED)
    return -EIO;
if (!smc->atomic_mode)
    return -EIO;

memcpy_toio(smc->shmem.iomem, buf, size);
smc->msg_id = (smc->msg_id + 1) & 0xf;
msg = (FIELD_PREP(SMC_MSG, SMC_MSG_WRITE_KEY) |
       FIELD_PREP(SMC_SIZE, size) |
       FIELD_PREP(SMC_ID, smc->msg_id) |
       FIELD_PREP(SMC_DATA, key));
smc->atomic_pending = true;

ret = apple_rtkit_send_message(smc->rtk, SMC_ENDPOINT, msg, NULL, true);
if (ret < 0) {
    dev_err(smc->dev, "Failed to send command (%d)\n", ret);
    return ret;
}

while (smc->atomic_pending) {
    ret = apple_rtkit_poll(smc->rtk);
    if (ret < 0) {
        dev_err(smc->dev, "RTKit poll failed (%llx)", msg);
        return ret;
    }
    udelay(100);
}

if (FIELD_GET(SMC_ID, smc->cmd_ret) != smc->msg_id) {
    dev_err(smc->dev, "Command sequence mismatch (expected %d, got %d)\n",
        smc->msg_id, (unsigned int)FIELD_GET(SMC_ID, smc->cmd_ret));
    return -EIO;
}

result = FIELD_GET(SMC_RESULT, smc->cmd_ret);
if (result)
    return -EIO;

return FIELD_GET(SMC_SIZE, smc->cmd_ret);

}
EXPORT_SYMBOL(apple_smc_write_atomic);

loud ice May 1, 2026, 7:18 PM

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fiery turtle Is that just an mmio write?

lol no

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its a mailbox

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there is a whole ipc-y system used to talk to devices

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which is involved here

fiery turtle May 1, 2026, 7:18 PM

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Ah

loud ice May 1, 2026, 7:19 PM

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the smc also owns the rtc

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and apple_rtkit_send_message is another lots of code: ```c
int apple_rtkit_send_message(struct apple_rtkit *rtk, u8 ep, u64 message,
struct completion *completion, bool atomic)
{
struct apple_mbox_msg msg = {
.msg0 = message,
.msg1 = ep,
};

if (rtk->crashed) {
    dev_warn(rtk->dev,
         "RTKit: Device is crashed, cannot send message\n");
    return -EINVAL;
}

if (ep >= APPLE_RTKIT_APP_ENDPOINT_START &&
    !apple_rtkit_is_running(rtk)) {
    dev_warn(rtk->dev,
         "RTKit: Endpoint 0x%02x is not running, cannot send message\n", ep);
    return -EINVAL;
}

/*
 * The message will be sent with a MMIO write. We need the barrier
 * here to ensure any previous writes to buffers are visible to the
 * device before that MMIO write happens.
 */
dma_wmb();

return apple_mbox_send(rtk->mbox, msg, atomic);

}

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and apple_mbox_send is another screen of code

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and its DMA btw

fiery turtle May 1, 2026, 7:20 PM

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Why is it called an rt kit

loud ice May 1, 2026, 7:20 PM

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fiery turtle Why is it called an rt kit

i think its like a framework used to do realtime things that apple uses

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lol

fiery turtle May 1, 2026, 7:21 PM

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Framework as in like set of APIs?

loud ice May 1, 2026, 7:21 PM

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seems like its an rtos lol

fiery turtle May 1, 2026, 7:21 PM

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There's a coprocessor running it?

loud ice May 1, 2026, 7:21 PM

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ofc

fiery turtle May 1, 2026, 7:21 PM

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Lol

loud ice May 1, 2026, 7:22 PM

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its apple

fiery turtle May 1, 2026, 7:22 PM

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I guess thats a neat way to do it but

loud ice May 1, 2026, 7:22 PM

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everything is a coprocessor

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the display output thing is a coprocessor too

frank canopy May 1, 2026, 7:22 PM

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vast kestrel But isn't psci done via some special opcode

hvc or smc depending - the madt will tell you which

fiery turtle May 1, 2026, 7:22 PM

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Iirc the iPhone camera runs a separate Linux instance or something?

loud ice May 1, 2026, 7:22 PM

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well its not linux lol

fiery turtle May 1, 2026, 7:23 PM

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Someone said it literally was Linux

loud ice May 1, 2026, 7:23 PM

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that would be very weird

pine leaf May 1, 2026, 7:23 PM

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fiery turtle Iirc the iPhone camera runs a separate Linux instance or something?

the touchbar on Macs that have that is just an elongated iPhone

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trl

loud ice May 1, 2026, 7:23 PM

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pine leaf the touchbar on Macs that have that is just an elongated iPhone

i dont think thats the case on m1

pine leaf May 1, 2026, 7:23 PM

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I remember it's the case on some at least

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people have gotten Linux running on specifically the touchbar

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not the mac itself

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the touchbar individually

loud ice May 1, 2026, 7:24 PM

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the touchbar was its own thing yeah iirc

fiery turtle May 1, 2026, 7:25 PM

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pine leaf the touchbar individually

Bruh

loud ice May 1, 2026, 7:25 PM

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apple loves putting too many cpus in things

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its so dumb

fiery turtle May 1, 2026, 7:25 PM

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Isn't that really increasing the cost for everything

pine leaf May 1, 2026, 7:25 PM

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Nintendo did it first in 2006 trl

loud ice May 1, 2026, 7:26 PM

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fiery turtle Isn't that really increasing the cost for everything

dont think so

pine leaf May 1, 2026, 7:26 PM

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(probably not first; but before Apple at least)

loud ice May 1, 2026, 7:26 PM

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or not significantly anyway

fiery turtle May 1, 2026, 7:26 PM

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pine leaf people have gotten Linux running on specifically the touchbar

Whats the cpu in it

loud ice May 1, 2026, 7:26 PM

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its probably some arm thing

pine leaf May 1, 2026, 7:26 PM

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fiery turtle Whats the cpu in it

I don't remember, I saw that ages ago

fiery turtle May 1, 2026, 7:26 PM

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Does it run some customized Darwin kernel by default or

loud ice May 1, 2026, 7:26 PM

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i think it was vulnernable to the same bootrom bug as iphone bootroms were lol

pine leaf May 1, 2026, 7:27 PM

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fiery turtle Does it run some customized Darwin kernel by default or

I'd imagine so, since it uses iBoot, and that's how they got Linux running on it

pine leaf May 1, 2026, 7:27 PM

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loud ice i think it was vulnernable to the same bootrom bug as iphone bootroms were lol

^^^

loud ice May 1, 2026, 7:27 PM

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its arm64 too

loud ice May 1, 2026, 7:28 PM

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fiery turtle Does it run some customized Darwin kernel by default or

seems like its based off of watchos??? lol

fiery turtle May 1, 2026, 7:38 PM

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lol

hallow marten May 1, 2026, 7:49 PM

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fiery turtle Does it run some customized Darwin kernel by default or

Yeah it's a constrained Darwin, but I think apple also has another kernel for something which I forgot

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Like they have a distinct thing from Darwin that they use somewhere

craggy epoch May 1, 2026, 7:56 PM

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vast kestrel But isn't psci done via some special opcode

smc

Secure monitor call

craggy epoch May 1, 2026, 7:59 PM

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fiery turtle looks like power state transitions still require prorietary drivers tho

That is extremely disappointing. I wonder if PSCI still works though.

loud ice May 1, 2026, 8:03 PM

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craggy epoch That is extremely disappointing. I wonder if PSCI still works though.

i mean whats the alternative

craggy epoch May 1, 2026, 8:04 PM

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loud ice i mean whats the alternative

Some kind of proprietary driver like Qualcomm pulled with Windows for Snapdragon X.

loud ice May 1, 2026, 8:04 PM

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oh lol

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i think that wont fly for linux but idk

craggy epoch May 1, 2026, 8:05 PM

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It would fly just fine for a vendor Linux. Android does stuff like that all over the place.

frank canopy May 1, 2026, 8:10 PM

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craggy epoch `smc` Secure monitor call

it can be hvc instead btw, if the hypervisor is intercepting it

fiery turtle May 1, 2026, 8:26 PM

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craggy epoch That is extremely disappointing. I wonder if PSCI still works though.

yeah

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all pci stuff is described properly including allowed bar ranges etc tho

hollow elm May 1, 2026, 8:26 PM

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loud ice apple loves putting too many cpus in things

once you have wafer space adding more logic is free halfmemeright

craggy epoch May 1, 2026, 8:44 PM

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hollow elm once you have wafer space adding more logic is free <:halfmemeright:715831702164...

https://tenor.com/view/eating-pet-lover-gif-25156411

Tenor

#

He's got a wafer

kind mantle May 1, 2026, 10:38 PM

#

Is uacpi-rs reasonably up to date and maintained?

fiery turtle May 1, 2026, 10:45 PM

#

might be worth asking in #1287451030241542205

vocal geyser May 2, 2026, 12:27 PM

#

fiery ice

how to do graphs like this

fiery ice May 2, 2026, 3:22 PM

#

vocal geyser how to do graphs like this

using qcachegrind

#

and you have to output the correct log syntax

fiery ice May 3, 2026, 3:04 PM

#

@fiery turtle if i want to use uAcpi in userspace, i would have to use ioperm, but where should i use it?

#

i could do it in the io_read and write ops

#

and that should be pretty straightforward, but i am worried it might cause slowdowns

hollow elm May 3, 2026, 3:06 PM

#

io_map and io_unmap?

#

that seems like a natural point to grant permissions

fiery ice May 3, 2026, 3:07 PM

#

should i just use ioperm with the base?

#

i am worried it won't work with the offset later

hollow elm May 3, 2026, 3:08 PM

#

i mean in the tss io bitmap just set bits corresponding to the ports in range [base, base+len)

calm latch May 3, 2026, 3:08 PM

#

I just iopl 3 it

fiery ice May 3, 2026, 3:08 PM

#

💀

hollow elm May 3, 2026, 3:08 PM

#

for the acpi server might as well tbh

calm latch May 3, 2026, 3:08 PM

#

but you can probably refcount it in userspace, and call your kernel helpers to enable/disable it in tss

hollow elm May 3, 2026, 3:08 PM

#

given aml can just request arbitrary ports anyway

calm latch May 3, 2026, 3:08 PM

#

from io_map/io_unmap

fiery ice May 3, 2026, 3:09 PM

#

hollow elm i mean in the tss io bitmap just set bits corresponding to the ports in range [b...

and unmap? just remove the perms for the handle?

calm latch May 3, 2026, 3:09 PM

#

yeah

fiery ice May 3, 2026, 3:09 PM

#

thx

calm latch May 3, 2026, 3:09 PM

#

Or you can just call kernel

#

like io is slow anyway so an extra roundtrip won't be noticeable I guess

#

you also need to think about pci discovery and stuff probably

fiery ice May 3, 2026, 3:11 PM

#

i'm gonna use messages + a dedicated pci service for that

calm latch May 3, 2026, 3:11 PM

#

cool

#

(also, why is everyone writing microkernels all of a sudden?)

fiery ice May 3, 2026, 3:11 PM

#

i already have a messaging interface done

calm latch May 3, 2026, 3:11 PM

#

like last week was the init server week

fiery ice May 3, 2026, 3:11 PM

#

calm latch (also, why is everyone writing microkernels all of a sudden?)

this was in the works for at least 1 year

#

lol

calm latch May 3, 2026, 3:12 PM

#

cool

#

how are you doing your ipc?

fiery ice May 3, 2026, 3:12 PM

#

i have a central service that handles registration of the others

#

and you can call that to get the other services tid and port to send messages to

calm latch May 3, 2026, 3:13 PM

#

no, I mean what's your ipc model, out of curiosity

#

not the discovery

#

(also, I'm thinking I can walk away from having a central discovery mechanism in my os)

fiery ice May 3, 2026, 3:14 PM

#

i just made a custom message struct and use this to send messages between threads, messages are stored in a server queue and routed accordingly

#

this struct could prob be reduced tbh

calm latch May 3, 2026, 3:15 PM

#

it's fine

#

mine is larger

loud ice May 3, 2026, 3:15 PM

#

and in kernelmode its an unbounded message queue?

fiery ice May 3, 2026, 3:15 PM

#

yeah it's unbounded

calm latch May 3, 2026, 3:15 PM

#

so is it async send sync receive like mine?

fiery ice May 3, 2026, 3:16 PM

#

i should probably put limits on it tho

fiery ice May 3, 2026, 3:16 PM

#

calm latch so is it async send sync receive like mine?

ye

calm latch May 3, 2026, 3:16 PM

#

fiery ice i should probably put limits on it tho

I've been telling that to myself for the past 3 years and haven't gotten to it yet lol

fiery ice May 3, 2026, 3:16 PM

#

XD

#

@calm latch what would be the best method for a per thread IOPB?

#

or per process

#

copying the iopb array would be expensive, no?

calm latch May 3, 2026, 3:31 PM

#

I guess just allocate a tss when you enable it

fiery ice May 3, 2026, 3:31 PM

#

so a TSS per thread?

calm latch May 3, 2026, 3:32 PM

#

idk

torpid root May 3, 2026, 3:34 PM

#

CoW it if you want

calm latch May 3, 2026, 3:38 PM

#

I'd imagine per-process would be problematic because you need to store the kernel stacks somewhere

#

I guess you could allocate one per cpu for each process and rotate through them though

rustic compass May 3, 2026, 3:46 PM

#

or given that io ports are rarely used today have a syscall for io port reads

fiery ice May 3, 2026, 4:10 PM

#

calm latch I guess you could allocate one per cpu for each process and rotate through them ...

just point the rsps and ists to a per cpu one

calm latch May 3, 2026, 4:14 PM

#

but then you'd be copying the bitmap

fiery ice May 3, 2026, 4:17 PM

#

calm latch but then you'd be copying the bitmap

no?

#

the tss is still per process

#

if you do per process

calm latch May 3, 2026, 4:18 PM

#

yeah, but what I mean is that you need to allocate tss per cpu per process

fiery ice May 3, 2026, 4:18 PM

#

no?

#

oh wait

#

you would have to update the pointers

#

fuck it, syscall it is

flat badge May 3, 2026, 4:38 PM

#

calm latch I just iopl 3 it

iopl is removed with FRED

calm latch May 3, 2026, 4:39 PM

#

I can just not support FRED then trl

flat badge May 3, 2026, 4:39 PM

#

or support the tss bitmap

calm latch May 3, 2026, 4:40 PM

#

extra work anyway

flat badge May 3, 2026, 4:40 PM

#

you can emulate iopl by just storing an all ones bitmap in the tss

calm latch May 3, 2026, 4:41 PM

#

I can also catch gpfs

flat badge May 3, 2026, 4:41 PM

#

and then you can swap the pointer to the bitmap

#

this requires minimal effort

calm latch May 3, 2026, 4:41 PM

#

no, if I'm doing it, I'm doing it properly, and with capabilities and stuff, and the proper bitmap

#

capabilities for everything is very nice anyway

#

like you don't have to do anything, and your system has suddenly got very good access control infrastructure

flat badge May 3, 2026, 4:45 PM

#

you can also have a cap that gives access to all ports

calm latch May 3, 2026, 4:45 PM

#

yeah, but that's boring

#

because otherwise it's very nice for drivers

#

especially if (when) I end up supporting iommu

#

(like as a whole)

#

I already have capabilities for interrupts, I'm planning to implement capabilities for timers and physical memory

fierce kiln May 4, 2026, 9:28 PM

#

is dis fast

#

idk

#

i never pay attention to my benchmarks unless they become abominable

#

which is less frequent these days

#

this is emulated x64 on apple silicon m4

fiery turtle May 4, 2026, 9:30 PM

#

TCG is usually an order of magnitude slower so good job

fiery ice May 4, 2026, 9:32 PM

#

i think mine will work even better when i move uacpi to userspace

frank canopy May 4, 2026, 10:18 PM

#

fierce kiln is dis fast

qemu tcg or whatever the apple compat layer thing is? i keep hearing people say they have one but idk how good it is lol

left orbit May 4, 2026, 10:21 PM

#

rosetta

#

?

#

but that's for running native applications

#

i belive it does aot x86->arm64

#

at least to some degree, idk how much you can really translate ahead of time

flat badge May 4, 2026, 10:23 PM

#

I think it also links the transpiled apps against native libs

#

such that for example the gpu driver etc. runs natively

rustic compass May 8, 2026, 9:31 AM

#

@fiery turtle is the string passed by uacpi_kernel_log changed after the function returns?

#

so is the lifetime limited to the function invocation?

fiery turtle May 8, 2026, 9:32 AM

#

yes

loud ice May 8, 2026, 9:32 AM

#

if you have formatted logging probably not tho

fiery turtle May 8, 2026, 9:32 AM

#

i assume its talking about the non-printf version

#

since its for rust bindings

loud ice May 8, 2026, 9:33 AM

#

ah yeah

rustic compass May 8, 2026, 9:39 AM

#

fiery turtle i assume its talking about the non-printf version

downgraded to an object death

#

anyway,
how should i handle if the user of uacpi-rs hasnt implemented memory map/unmap as there isnt a status return

fiery turtle May 8, 2026, 9:43 AM

#

in for-5.0 there's a UACPI_MAP_FAILED

fiery turtle May 8, 2026, 9:44 AM

#

rustic compass downgraded to an object <a:death:816178972672131083>

sorry idk what that means

loud ice May 8, 2026, 9:55 AM

#

rustic compass anyway, how should i handle if the user of uacpi-rs hasnt implemented memory map...

return null?

loud ice May 8, 2026, 9:55 AM

#

rustic compass downgraded to an object <a:death:816178972672131083>

just make uacpi logs map to the log crate ngl

rustic compass May 8, 2026, 10:09 AM

#

fiery turtle sorry idk what that means

i assume its talking about the non-printf version

fiery turtle May 8, 2026, 10:10 AM

#

lol

rustic compass May 8, 2026, 10:10 AM

#

loud ice just make uacpi logs map to the log crate ngl

tbh i'm not really a fan of this, it locks you into a somewhat specific logging framework even if you dont need/want one

fiery turtle May 8, 2026, 10:10 AM

#

i wasnt referring to you lmao

rustic compass May 8, 2026, 10:11 AM

#

fiery turtle in `for-5.0` there's a `UACPI_MAP_FAILED`

currently still on 3.2 should probably update

fiery turtle May 8, 2026, 10:12 AM

#

on older versions returning NULL is treated as an error

fiery turtle May 8, 2026, 3:44 PM

#

@pallid lava btw why did u need to trace ec events in linux

pallid lava May 8, 2026, 3:44 PM

#

i wanted to know whatever is being called on my laptop

#

so when i get to write an ec driver i can make sure i am not reading garbage from the ec

fiery turtle May 8, 2026, 3:46 PM

#

Ah ok

pallid lava May 8, 2026, 6:03 PM

#

so uh

#

should there be an _EXX or something similar in \_GPE for the EC's GPE?

#

i am trying to install the gpe handler and i am getting not found error

fiery turtle May 8, 2026, 6:06 PM

#

pallid lava should there be an _EXX or something similar in \\_GPE for the EC's GPE?

nope

#

_EXX are run by uacpi automatically

fiery turtle May 8, 2026, 6:06 PM

#

pallid lava should there be an _EXX or something similar in \\_GPE for the EC's GPE?

https://github.com/managarm/managarm/blob/master/kernel/thor/system/acpi/ec.cpp

GitHub

managarm/kernel/thor/system/acpi/ec.cpp at master · managarm/managarm

Pragmatic microkernel-based OS with fully asynchronous I/O - managarm/managarm

#

just use this as an example

pallid lava May 8, 2026, 6:08 PM

#

okay, yeah, my issue is with uacpi_install_gpe_handler, that's the thing that is erroring

fiery turtle May 8, 2026, 6:08 PM

#

did u verify that you're passing the right index?

pallid lava May 8, 2026, 6:19 PM

#

Nvm, I was not calling finalize_gpe..., and i was supposed to pass null as first argument to install and enable handler

#

Now everything works

fiery turtle May 8, 2026, 6:22 PM

#

yeah it expects a GPE device, which is either \_GPE or a custom installed GPE block

#

or NULL which implies the former

fiery turtle May 8, 2026, 6:22 PM

#

pallid lava Now everything works <:ok:877289200880324678>

cool cool

pallid lava May 9, 2026, 6:57 PM

#

got ec events and method dispatch working chad

#

as a fun fact, the ec apparently intercepts some fn + something keys in my laptop

#

the arrow keys for controlling the backlight brighness of the keyboard, and f7/f8 for the display backlight brighness

#

however, the aml code for the keyboard does not do anything unless you discover the wmi object that controls the keyboard and other memes and you initialize it (aka call some magic function with some magic values)

fiery turtle May 9, 2026, 7:00 PM

#

Yeah wmi is a funny thing

pallid lava May 9, 2026, 7:02 PM

#

and after you initialize it

#

that thing only sets a variable to 1, which is tested in the _Qxx method, and if set, does a notify() on the wmi object

fiery turtle May 9, 2026, 7:02 PM

#

Ye

pallid lava May 9, 2026, 7:02 PM

#

and then you have to handle that natively and call some other magic method and shi

fiery turtle May 9, 2026, 7:02 PM

#

That's pretty normal

fiery turtle May 9, 2026, 7:02 PM

#

pallid lava and then you have to handle that natively and call some other magic method and s...

Yeah

pallid lava May 9, 2026, 7:03 PM

#

for the display brightness it gets a bit more weird

#

because it complains about objects that do not exist

fiery turtle May 9, 2026, 7:03 PM

#

Lol

pallid lava May 9, 2026, 7:04 PM

#

it complains about \blablabla...VGA.EDP

fiery turtle May 9, 2026, 7:04 PM

#

Does it do that on Linux

pallid lava May 9, 2026, 7:04 PM

#

letme check

fiery turtle May 9, 2026, 7:04 PM

#

Also I mean

#

Just dump aml and check if its supposed to

pallid lava May 9, 2026, 7:04 PM

#

yes

#

it complains in linux too

fiery turtle May 9, 2026, 7:04 PM

#

Ah ok

#

Good firmware u got

pallid lava May 9, 2026, 7:04 PM

#

extremely epic one

#

May 09 21:04:25 AtiePC kernel: ACPI BIOS Error (bug): Could not resolve symbol [^PCI0.GPP0.PEGP.EDP1], AE_NOT_FOUND (20251212/psargs-332)
May 09 21:04:25 AtiePC kernel: ACPI Error: Aborting method \_SB.BRTN due to previous error (AE_NOT_FOUND) (20251212/psparse-529)
May 09 21:04:25 AtiePC kernel: ACPI Error: Aborting method \_SB.PCI0.SBRG.EC0.QLIB due to previous error (AE_NOT_FOUND) (20251212/psparse-529)
May 09 21:04:25 AtiePC kernel: ACPI Error: Aborting method \_SB.PCI0.SBRG.EC0._Q17 due to previous error (AE_NOT_FOUND) (20251212/psparse-529)
May 09 21:04:26 AtiePC kernel: ACPI BIOS Error (bug): Could not resolve symbol [^PCI0.GPP0.PEGP.EDP1], AE_NOT_FOUND (20251212/psargs-332)
May 09 21:04:26 AtiePC kernel: ACPI Error: Aborting method \_SB.BRTN due to previous error (AE_NOT_FOUND) (20251212/psparse-529)
May 09 21:04:26 AtiePC kernel: ACPI Error: Aborting method \_SB.PCI0.SBRG.EC0.QLIB due to previous error (AE_NOT_FOUND) (20251212/psparse-529)
May 09 21:04:26 AtiePC kernel: ACPI Error: Aborting method \_SB.PCI0.SBRG.EC0._Q17 due to previous error (AE_NOT_FOUND) (20251212/psparse-529)

#

during namespace initialization both linux and uacpi complain about some other objects not existing

fiery ice May 9, 2026, 7:06 PM

#

pallid lava ``` May 09 21:04:25 AtiePC kernel: ACPI BIOS Error (bug): Could not resolve symb...

PCI errors

mortal yoke May 9, 2026, 7:06 PM

#

reminds me that iirc on my laptop the ec fn keys were interacting weirdly with my ps2 driver at some point so then it stopped working or something, idr if that was with the old bad osdev wiki driver tho or the new better one that's based on linux's KEKW or it could have been qacpi weirdness somehow as there were also the spurious power button events during boot

fiery turtle May 9, 2026, 7:06 PM

#

Lmao

fiery turtle May 9, 2026, 7:06 PM

#

mortal yoke reminds me that iirc on my laptop the ec fn keys were interacting weirdly with m...

Iirc u fixed those power button events right

fiery turtle May 9, 2026, 7:06 PM

#

pallid lava during namespace initialization both linux and uacpi complain about some other o...

Which laptop is this btw

mortal yoke May 9, 2026, 7:08 PM

#

fiery turtle Iirc u fixed those power button events right

I don't think they actually got fixed, I did remove the ec clearing code that was also causing qookie's laptop to hang there but I think they did still happen when I last tried (I just though they were fixed because they didn't happen for a decent amount of boots)

pallid lava May 9, 2026, 7:08 PM

#

otoh i have backlight methods in aml

#

the standard ones, specified in the acpi specification appendix

#

i have to see whether they work

fiery turtle May 9, 2026, 7:09 PM

#

mortal yoke I don't think they actually got fixed, I did remove the ec clearing code that wa...

Ah

fiery turtle May 9, 2026, 7:09 PM

#

pallid lava otoh i have backlight methods in aml

Thats kinda rare

pallid lava May 9, 2026, 7:09 PM

#

ASUS TUF Gaming A15 FA506NC

fiery turtle May 9, 2026, 7:09 PM

#

yeah those usually have shit aml

pallid lava May 9, 2026, 7:09 PM

#

lol

#

i remember when i bought the laptop, i thought it would be a good idea to install the asus linux kernel

fiery turtle May 9, 2026, 7:10 PM

#

Thats a thing?

pallid lava May 9, 2026, 7:10 PM

#

it's a community kernel

fiery turtle May 9, 2026, 7:10 PM

#

Huh lol

pallid lava May 9, 2026, 7:10 PM

#

after rebooting to it, the keyboard backlight stopped working after the firmware phase

fiery turtle May 9, 2026, 7:11 PM

#

Lol

pallid lava May 9, 2026, 7:11 PM

#

i was ultra panicking

#

i tried everything to get them back to work, including trying to write values to the sysfs attributes for the backlight

#

it resulted that idfk what they had done but their wmi driver was nuts

#

after cross referencing the mainline kernel source code with what the writes to the attributes should do

#

then i got back to an original kernel and the keyboard backlight started working again

#

those were the 2 scariest days in my life because i had just bought the laptop and i tried everything in whatever forum i found, including pressing the power button for 40 seconds to clear the ec, which i am not still sure whether that works

hollow elm May 9, 2026, 7:17 PM

#

mortal yoke reminds me that iirc on my laptop the ec fn keys were interacting weirdly with m...

on my laptop pressing fn+f2/f3 (brightness down/up) causes linux to log unknown keys in dmesg (the brightness control does work so it's a little bonus)

#

[85585.698385] atkbd serio0: Unknown key pressed (translated set 2, code 0xab on isa0060/serio0).
[85585.698396] atkbd serio0: Use 'setkeycodes e02b <keycode>' to make it known.
[85585.781303] atkbd serio0: Unknown key released (translated set 2, code 0xab on isa0060/serio0).
[85585.781310] atkbd serio0: Use 'setkeycodes e02b <keycode>' to make it known.
[85586.546999] atkbd serio0: Unknown key pressed (translated set 2, code 0xab on isa0060/serio0).
[85586.547011] atkbd serio0: Use 'setkeycodes e02b <keycode>' to make it known.
[85586.673181] atkbd serio0: Unknown key released (translated set 2, code 0xab on isa0060/serio0).
[85586.673187] atkbd serio0: Use 'setkeycodes e02b <keycode>' to make it known.

pallid lava May 9, 2026, 7:19 PM

#

btw, has anyone here got sleep working?

#

i wonder if it would be possible to have the display working after waking up without having to write native video drivers, or only using aml methods

fiery turtle May 9, 2026, 7:20 PM

#

@north holly and @calm latch did

#

oberrow had it working on real hw

#

but no display, that requires full gpu re-init

calm latch May 9, 2026, 7:21 PM

#

I mean me too, but I didn't have GPU drivers

north holly May 9, 2026, 7:21 PM

#

fiery turtle oberrow had it working on real hw

then the big regression™ broke everything

#

nooo

#

in theory sleep code still is correct

pallid lava May 9, 2026, 7:21 PM

#

so you know you're awake via serial or some other mechanism, that is not by video?

north holly May 9, 2026, 7:21 PM

#

north holly in theory sleep code still is correct

but the rest of the kernel is the reason it broke

north holly May 9, 2026, 7:22 PM

#

pallid lava so you know you're awake via serial or some other mechanism, that is not by vide...

i know it woke up because i made it shutdown after wake

pallid lava May 9, 2026, 7:22 PM

#

oh okay

fiery turtle May 9, 2026, 7:22 PM

#

u also need a real mode wake trampoline and own smp bringup code etc

#

its fun

north holly May 9, 2026, 7:22 PM

#

north holly but the rest of the kernel is the reason it broke

speaking of kernel that project has been dead for a good while nooo i'll work on it soon

#

u need to restore pci state too

#

which was fun to do

pallid lava May 9, 2026, 7:23 PM

#

D0uninitialized by beloved

fiery turtle May 9, 2026, 7:23 PM

#

it clears all BARs etc

pallid lava May 9, 2026, 7:23 PM

#

i guess that it is not possible to use the boot services after waking up

fiery turtle May 9, 2026, 7:24 PM

#

yeah ofc

#

u become the firmware

pallid lava May 9, 2026, 7:24 PM

#

well nooo

mortal yoke May 9, 2026, 7:24 PM

#

what would you even use them for

calm latch May 9, 2026, 7:24 PM

#

pallid lava so you know you're awake via serial or some other mechanism, that is not by vide...

Yeah, I have 2 PCs with serial out, and my kernel had woken up and printed so on serial

fiery turtle May 9, 2026, 7:24 PM

#

mortal yoke what would you even use them for

video mode i guess

calm latch May 9, 2026, 7:24 PM

#

fiery turtle u also need a real mode wake trampoline and own smp bringup code etc

I reuse the same trampoline as for my SMP init

pallid lava May 9, 2026, 7:25 PM

#

fiery turtle video mode i guess

yeah, exactly that

mortal yoke May 9, 2026, 7:25 PM

#

ah

pallid lava May 9, 2026, 7:25 PM

#

to get a fb with gop

#

but in that case the firmware would have to reinitialize the video card too

fiery turtle May 9, 2026, 7:25 PM

#

but yeah no u need suspend/resume callbacks for all drivers

fiery turtle May 9, 2026, 7:26 PM

#

pallid lava but in that case the firmware would have to reinitialize the video card too

yeah

north holly May 9, 2026, 7:26 PM

#

on qemu u can make a bochs vbe driver to restore the fb fwiw

pallid lava May 9, 2026, 7:26 PM

#

yeah but real hw is more exciting

fiery turtle May 9, 2026, 7:26 PM

#

north holly on qemu u can make a bochs vbe driver to restore the fb fwiw

qemu wake after suspend wont work

#

because u havent upstreamed the seabios fix

#

or rather, it disables ecam iirc

north holly May 9, 2026, 7:26 PM

#

oh yeah forgot about that

pallid lava May 9, 2026, 7:26 PM

#

wait, whats the problem with it

mortal yoke May 9, 2026, 7:26 PM

#

fiery turtle u also need a real mode wake trampoline and own smp bringup code etc

kinda related to this is the better trampoline that's supposed to be entered at protected mode also entered at real mode? or is it actually protected mode, that's what I have been assuming when writing the trampoline code

fiery turtle May 9, 2026, 7:26 PM

#

pallid lava wait, whats the problem with it

ECAM is disabled after wake

north holly May 9, 2026, 7:26 PM

#

pallid lava wait, whats the problem with it

ECAM isn't restored

pallid lava May 9, 2026, 7:26 PM

#

lol

#

seabios skill issue

north holly May 9, 2026, 7:27 PM

#

or well it is but something else prevents it from being restored

fiery turtle May 9, 2026, 7:27 PM

#

mortal yoke kinda related to this is the better trampoline that's supposed to be entered at ...

it is actually protected mode

#

but idk if any firmware supports that trampoline

pallid lava May 9, 2026, 7:27 PM

#

like seabios already has code for handling s3 wakes

#

how did they forget that, or qemu has had a nasty regression

fiery turtle May 9, 2026, 7:27 PM

#

its just a logic bug in seabios

#

it write protects that

#

so writes do nothing

north holly May 9, 2026, 7:28 PM

#

yeah that's it

#

i'd upstream my fixes but that's a lot of work

pallid lava May 9, 2026, 7:28 PM

#

welp

north holly May 9, 2026, 7:28 PM

#

if anyone wants to takeover it's a really simply patch

pallid lava May 9, 2026, 7:28 PM

#

the seabios mailing list has very low traffic

north holly May 9, 2026, 7:29 PM

#

(it's a lot of work because it interrupts my hyperfixation)

pallid lava May 9, 2026, 7:29 PM

#

you could get it upstreamed in a few days

mortal yoke May 9, 2026, 7:29 PM

#

iirc the problem wasn't that, it was that it left the mmconfig pointing to the ecam space and then after resuming the pci accesses it does (like enabling the ecam itself) try to use the mmconfig that isn't enabled

fiery turtle May 9, 2026, 7:29 PM

#

seabios should be easy to upstream yeah

#

oh yeah maybe

#

it uses ecam to enable ecam

#

which fails

pallid lava May 9, 2026, 7:29 PM

#

galaxybrain

fiery turtle May 9, 2026, 7:30 PM

#

@north holly can u post the patch here

north holly May 9, 2026, 7:30 PM

#

i don't think i have it anymore

#

u would have to search the seabios mailing list for it

mortal yoke May 9, 2026, 7:30 PM

#

I think this is enough for it

📎 resume.patch

pallid lava May 9, 2026, 7:31 PM

#

make_bios_writable?

north holly May 9, 2026, 7:31 PM

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mortal yoke I think this is enough for it

lgtm

north holly May 9, 2026, 7:31 PM

#

pallid lava make_bios_writable?

it's in ROM

pallid lava May 9, 2026, 7:31 PM

#

yeah ik

#

but what does it have to do with the ecam thing

#

ah okay

mortal yoke May 9, 2026, 7:31 PM

#

it has to do with being able to write the variable

pallid lava May 9, 2026, 7:31 PM

#

to modify the variable, right

north holly May 9, 2026, 7:32 PM

#

ye

north holly May 9, 2026, 7:32 PM

#

north holly lgtm

i think they had a problem with just doing that in a random place if u wanted to find my post on the mailing list

#

before u submit the patch

fiery turtle May 9, 2026, 7:34 PM

#

https://patchew.org/Seabios/CAFtnJrMDQAjqTZMrP1dBf13ZPE69df6TdswVbmzrX2M7R0EmTw@mail.gmail.com/

#

north holly May 9, 2026, 7:35 PM

#

yeah mainly just my own patch skill issues

mortal yoke May 9, 2026, 7:36 PM

#

I think the comment about the bios readonly doesn't really even apply here as the commented out code wasn't there originally to begin with (and its made read-only later on in the same function anyway)

north holly May 9, 2026, 7:36 PM

#

north holly yeah mainly just my own patch skill issues

i would've followed up but i was thousands of KMs from home

#

and forgot to when i got back

fiery turtle May 9, 2026, 7:37 PM

#

would be nice if someone picked that up

north holly May 9, 2026, 7:37 PM

#

sure would

pallid lava May 9, 2026, 8:58 PM

#

well

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_BCM seems to do nothing

#

it does some magic stuff and then a notify

fiery turtle May 9, 2026, 9:12 PM

#

sadge

#

maybe u need some igpu pre-init before u can use it or smth

#

or hook the notify and do something

#

https://github.com/uACPI/uACPI/issues/153

GitHub

Can it generate an ACPI 1.0 BIOS? · Issue #153 · uACPI/uACPI

Can it generate an ACPI 1.0 BIOS like something from 1998-1999? Something period correct for Windows 98/NT/2000/ME?

#

what an issue

calm latch May 9, 2026, 9:29 PM

#

I think it comes from this? https://github.com/joncampbell123/dosbox-x/issues/6260

GitHub

Implementing ACPI in DOSBox-X with uACPI · Issue #6260 · joncampb...

Question I and some others are wondering if some developers here could help implement ACPI for DOSBox-X via https://github.com/uACPI/uACPI if possible. ACPI is currently a stub, as you know, and it...

calm latch May 9, 2026, 9:31 PM

#

fiery turtle https://github.com/uACPI/uACPI/issues/153

I think the question was if it works with ACPI 1.0

fiery turtle May 9, 2026, 9:31 PM

#

lol

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how did u even uncover that

calm latch May 9, 2026, 9:32 PM

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stalking that person's profile

fiery turtle May 9, 2026, 9:32 PM

#

lol

#

yeah idk maybe thats what they meant

calm latch May 9, 2026, 9:36 PM

#

They just use gcc, so I guess uACPI could be compatible?

fiery turtle May 9, 2026, 9:38 PM

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im not sure it will compile in 16 bit mode but who knows

calm latch May 9, 2026, 9:38 PM

#

why wouldn't it?

fiery turtle May 9, 2026, 9:39 PM

#

UACPI_POINTER_SIZE checks for phys_addr etc

fiery ice May 9, 2026, 9:39 PM

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calm latch why wouldn't it?

#

random u64s

fiery turtle May 9, 2026, 9:39 PM

#

16 bit gcc doesnt support u64?

fiery ice May 9, 2026, 9:39 PM

#

idk if 16 bit supports them

fiery ice May 9, 2026, 9:39 PM

#

fiery turtle 16 bit gcc doesnt support u64?

it does?

fiery turtle May 9, 2026, 9:39 PM

#

no idea

fiery ice May 9, 2026, 9:40 PM

#

clanker time

#

fiery turtle May 9, 2026, 9:41 PM

#

honestly im not sure how that would even work considering the DSDT is definitely larger than 64k

fiery ice May 9, 2026, 9:41 PM

#

calm latch May 9, 2026, 9:41 PM

#

oh no, uacpi is AI tainted now nooo trl

fiery turtle May 9, 2026, 9:41 PM

#

so u need segment support also

calm latch May 9, 2026, 9:41 PM

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calm latch oh no, uacpi is AI tainted now <:nooo:750466870993223750> <:trl:8293166411918868...

(sorry, I can't get over openslopware)

kindred beacon May 9, 2026, 9:44 PM

#

https://github.com/uACPI/uACPI/issues/153 lmfao, I wouldn't have understood what this is about

GitHub

Can it generate an ACPI 1.0 BIOS? · Issue #153 · uACPI/uACPI

Can it generate an ACPI 1.0 BIOS like something from 1998-1999? Something period correct for Windows 98/NT/2000/ME?

fiery turtle May 9, 2026, 9:45 PM

#

yeah lol

fiery ice May 9, 2026, 9:45 PM

#

fiery turtle so u need segment support also

fiery turtle May 9, 2026, 9:45 PM

#

this is for open watcom

fiery ice May 9, 2026, 9:45 PM

#

then clanker is stupid

#

lol

calm latch May 9, 2026, 9:46 PM

#

yeah

fiery turtle May 9, 2026, 9:46 PM

#

but clanker is right about other aspects

#

like 16-bit aml interpreter makes no sense

#

u literally cant even read the entire dsdt in one segment

calm latch May 9, 2026, 9:46 PM

#

Is their thing 16 bit?

fiery turtle May 9, 2026, 9:46 PM

#

i thought so since its DOS

calm latch May 9, 2026, 9:46 PM

#

https://github.com/joncampbell123/dosbox-x/blob/master/build

fiery turtle May 9, 2026, 9:48 PM

#

maybe its fine then

calm latch May 9, 2026, 9:49 PM

#

Like if they're talking about windows, maybe they target i386 or something?

#

They're using uint64_t's in their latest commit https://github.com/joncampbell123/dosbox-x/commit/de5b0961a4b11243d54c6977e6a5530cf0f90d19

#

whatever is this

#

No, it's an emulator?? https://dosbox-x.com/wiki/#Home

#

So maybe they do want to generate AML or something

#

I'm confused

fiery turtle May 9, 2026, 9:53 PM

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who knows what they want lmfao

calm latch May 9, 2026, 9:58 PM

#

I think I'm gonna go back to doing what I was doing before, which is figuring out how tf linux manages its io bitmap/tss on x86...

fiery ice May 9, 2026, 9:59 PM

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calm latch I think I'm gonna go back to doing what I was doing before, which is figuring ou...

i am doing lazy tss rn

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works fine

calm latch May 9, 2026, 9:59 PM

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fiery ice i am doing lazy tss rn

wdym by that

#

do you just copy all 16kb of memory?

#

8kb*

fiery ice May 9, 2026, 9:59 PM

#

basically i have a per core tss, that is used by all the normal processes

#

then, if a thread needs an io bitmap

#

the tss gets cloned only for that thread

calm latch May 9, 2026, 10:00 PM

#

https://elixir.bootlin.com/linux/v7.0.5/source/arch/x86/kernel/process.c#L446 linux seems to just memcpy it...

fiery ice May 9, 2026, 10:00 PM

#

my approach is faster and more reliable tbh

#

i just have a set of common pointers

#

that all the TSSes use

#

for each core

#

and the tss does not need to be copied

#

so it's faster

calm latch May 9, 2026, 10:03 PM

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I don't get what you're doing

#

oh

fiery ice May 9, 2026, 10:03 PM

#

basically i allocate a new tss per thread

#

if they need one

#

for io stuff

calm latch May 9, 2026, 10:03 PM

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but that's the easy part

fiery ice May 9, 2026, 10:03 PM

#

and if the thread does have one, the scheduler loads that one

#

if it does not, it just uses the cpu one

calm latch May 9, 2026, 10:04 PM

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What's complicated is that I'd need a TLB-shootdown like thing

#

for this

fiery ice May 9, 2026, 10:04 PM

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for cpu i mean the local shared tss

#

wdym

calm latch May 9, 2026, 10:04 PM

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when you take the permissions away

fiery ice May 9, 2026, 10:04 PM

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hmm

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i just reload the tss using ltr

calm latch May 9, 2026, 10:05 PM

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I don't think it gets cached

fiery ice May 9, 2026, 10:05 PM

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wdym gets cached?

#

like it doesn't update the perms?

calm latch May 9, 2026, 10:05 PM

#

like you don't need to reload it since the cpu looks it up on every access iirc

fiery ice May 9, 2026, 10:06 PM

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hmm

#

i change the gdt entry every time i have to switch it

#

so i tought i had to reload it

calm latch May 9, 2026, 10:06 PM

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in that case you do

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but like when you change the tss itself you don't

fiery ice May 9, 2026, 10:07 PM

#

yeah in that case no

#

tho i do it bc of how my syscall works

calm latch May 9, 2026, 10:09 PM

#

Or I can just make it a syscall trl

fiery ice May 9, 2026, 10:09 PM

#

wdym

calm latch May 9, 2026, 10:09 PM

#

like not bother with tss and just call the kernel to i/o in ring 0

fiery ice May 9, 2026, 10:09 PM

#

💀

calm latch May 9, 2026, 10:11 PM

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Osdev forums have a genius solution https://f.osdev.org/viewtopic.php?t=21251

#

I'm gonna steal it

#

and this shit should be trivial to do

#

omg wtf

fiery turtle May 9, 2026, 11:22 PM

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calm latch Osdev forums have a genius solution https://f.osdev.org/viewtopic.php?t=21251

I kinda didn't understand it but

#

W/e I guess

#

Not that I care about Userspace pio

calm latch May 9, 2026, 11:25 PM

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fiery turtle I kinda didn't understand it but

Just abuse shared memory to have the same bitmap inside different per-CPU TSS instances

fiery turtle May 9, 2026, 11:25 PM

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calm latch Just abuse shared memory to have the same bitmap inside different per-CPU TSS in...

But the tss mask is needed per thread no?

calm latch May 9, 2026, 11:26 PM

#

fiery turtle But the tss mask is needed per thread no?

I'd do it per process

#

Because per-thread makes no sense

fiery turtle May 9, 2026, 11:26 PM

#

Even so, the process can migrate between cpus right

calm latch May 9, 2026, 11:27 PM

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Yeah, and the process can have more than 1 thread running on more than 1 CPU at any given time

fiery turtle May 9, 2026, 11:27 PM

#

So how do u sync stuff

fiery ice May 9, 2026, 11:27 PM

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calm latch Yeah, and the process can have more than 1 thread running on more than 1 CPU at ...

and that's why you need per thread

#

lol

#

if you don't wanna nuke stacks

calm latch May 9, 2026, 11:28 PM

#

fiery ice and that's why you need per thread

No

fiery ice May 9, 2026, 11:28 PM

#

how do you plan on not nuking rsp0?

#

or the ists

calm latch May 9, 2026, 11:29 PM

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fiery turtle So how do u sync stuff

So my plan is to allocate 4 page frames virtual window, where the first page will be the per-CPU stuff, the two pages in the middle will be swapped in the page tables between the threads/processes (so the TSS stays in the same place in virtual memory, but the underlying memory changes between the processes), and the last one would also be the same (for the Intel's skill issue 0xFFFF terminator byte)

fiery ice May 9, 2026, 11:30 PM

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ah right if you only swap the 4 iopb pages the stacks won't get touched

#

tho wait

fiery turtle May 9, 2026, 11:30 PM

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calm latch So my plan is to allocate 4 page frames virtual window, where the first page wil...

Crazy stuff

fiery ice May 9, 2026, 11:30 PM

#

why 4 pages?

#

i think you only need 3

calm latch May 9, 2026, 11:31 PM

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calm latch So my plan is to allocate 4 page frames virtual window, where the first page wil...

So, the two pages in the middle (which have the actual bitmap) have the same shared underlying memory, so when you change per-process bitmap, it changes in all of the TSSs because it's basically shared physical memory, just mapped at different virtual memory location

fiery ice May 9, 2026, 11:31 PM

#

the iopb is just 8k

#

a third page for the extra byte

calm latch May 9, 2026, 11:31 PM

#

And switching is not too bad since you're just changing two leaf page table entries

fiery ice May 9, 2026, 11:31 PM

#

ah wait, 4 pages is the full TSS you mean

calm latch May 9, 2026, 11:33 PM

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fiery ice why 4 pages?

1 page for TSS (per-CPU), 2 pages for the bitmap (64K entries, 8KB of RAM per-process), and extra page (which will 1 page shared between everyone) for the meme in the screenshot

calm latch May 9, 2026, 11:34 PM

#

fiery turtle Crazy stuff

Just casual osdev forums gem

calm latch May 9, 2026, 11:35 PM

#

calm latch 1 page for TSS (per-CPU), 2 pages for the bitmap (64K entries, 8KB of RAM per-pr...

So you switch the bitmap by fiddling with page tables on task switch

#

Also, while I'm at it, I might as well fix my stack allocation code and add guard pages as well...

calm latch May 9, 2026, 11:39 PM

#

calm latch 1 page for TSS (per-CPU), 2 pages for the bitmap (64K entries, 8KB of RAM per-pr...

I think I also have all the logic in kernel to do this already

flat badge May 10, 2026, 9:12 AM

#

That scheme sounds way more convoluted than simply loading another tss

calm latch May 10, 2026, 9:26 AM

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No

#

It's very simple

#

The only issue is that I need to decide if I want to trap GPFs and have a small instruction decoder, or to IPI other cores...

#

The first option sounds like an absolute nightmare on x86

#

I think I'll just hijack my TLB shootdown thing for this

flat badge May 10, 2026, 9:47 AM

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calm latch It's very simple

It requires process private kernel PTEs

calm latch May 10, 2026, 9:47 AM

#

So?

flat badge May 10, 2026, 9:48 AM

#

which is not very simple + has design implications on the rest of the virtual memory subsystem

calm latch May 10, 2026, 9:48 AM

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I'll never free them once allocated

#

And I'll track them lazily

loud ice May 10, 2026, 9:48 AM

#

just make an outb syscall tbh

flat badge May 10, 2026, 9:48 AM

#

the alternative is a ltr instruction which doesn't have any impact on the rest of the kernel at all

calm latch May 10, 2026, 9:48 AM

#

I thought about it yesterday, and didn't come up with any obvious issues

calm latch May 10, 2026, 9:49 AM

#

flat badge the alternative is a `ltr` instruction which doesn't have any impact on the rest...

It will be ltr to sometimes change the tss size

flat badge May 10, 2026, 9:50 AM

#

what's even the benefit over just ltr in all cases?

calm latch May 10, 2026, 9:50 AM

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That I don't have to allocate a million of TSSes, and syncrhonize them on every bitmap change

flat badge May 10, 2026, 9:51 AM

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Just make it per thread

calm latch May 10, 2026, 9:51 AM

#

And that it can be faster

calm latch May 10, 2026, 9:51 AM

#

flat badge Just make it per thread

Per thread is complicated

flat badge May 10, 2026, 9:51 AM

#

calm latch And that it can be faster

citation needed

calm latch May 10, 2026, 9:51 AM

#

With uACPI

flat badge May 10, 2026, 9:51 AM

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I don't buy "it is faster" w/o benchmarks

loud ice May 10, 2026, 9:52 AM

#

at least for this kind of thing yeah its dicey

#

i would really just have an inb/outb syscall tbh, or iopl

flat badge May 10, 2026, 9:53 AM

#

You're trading one instruction for extra effort in the VMM

#

that sounds like it's really not worth it to me

calm latch May 10, 2026, 9:53 AM

#

The only extra "expensive" part compared to per-thread TSS is (maybe) swapping 2 pages in the page tables, but userspace stuff becomes a lot easier if it's per-process

flat badge May 10, 2026, 9:54 AM

#

loud ice i would really just have an inb/outb syscall tbh, or iopl

iopl doesn't exist if FRED is on so betting on it sounds like a bad idea

#

the syscall is probably fine

loud ice May 10, 2026, 9:54 AM

#

flat badge iopl doesn't exist if FRED is on so betting on it sounds like a bad idea

oh right

#

just trap it with fred

flat badge May 10, 2026, 9:54 AM

#

but supporting the bitmap is also not hard

loud ice May 10, 2026, 9:54 AM

#

actually i have an even better idea

#

just make a jit

calm latch May 10, 2026, 9:55 AM

#

flat badge You're trading one instruction for extra effort in the VMM

that effort is only there if there are 2 different drivers, using different bitmaps, scheduled on the same CPU one after the other

flat badge May 10, 2026, 9:55 AM

#

calm latch The only extra "expensive" part compared to per-thread TSS is (maybe) swapping 2...

wdym by "swapping 2 pages"

#

if you swap pages you need to TLB invalidate

calm latch May 10, 2026, 9:55 AM

#

calm latch So, the two pages in the middle (which have the actual bitmap) have the same sha...

I tried to explain it here

calm latch May 10, 2026, 9:55 AM

#

flat badge if you swap pages you need to TLB invalidate

Yeah, swap the PTEs and invlpg 2 pages

#

No remote shootdowns

flat badge May 10, 2026, 9:56 AM

#

uh that becomes hard to reason about

calm latch May 10, 2026, 9:56 AM

#

The TSS is per-CPU

#

Idk I'll implement it and you can look at the code trl

loud ice May 10, 2026, 9:56 AM

#

calm latch Yeah, swap the PTEs and invlpg 2 pages

invlpg isnt that cheap right?

flat badge May 10, 2026, 9:57 AM

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I'm aware but if you do it like this you can accessible-but-not-referenced-anymore pages over extended periods of time

calm latch May 10, 2026, 9:57 AM

#

flat badge I'm aware but if you do it like this you can accessible-but-not-referenced-anymo...

Yes, but there's no problem with that

loud ice May 10, 2026, 9:57 AM

#

tbh i doubt any of the approaches are meaningfully better

flat badge May 10, 2026, 9:57 AM

#

the entire argument is moot until you have benchmarks on the cost of ltr

#

I bet this scheme is not worth it

calm latch May 10, 2026, 9:58 AM

#

But I will ltr anyway

loud ice May 10, 2026, 9:58 AM

#

ltr is certainly more annoying

flat badge May 10, 2026, 9:58 AM

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flat badge I bet this scheme is not worth it

or rather: I bet that it has negative overall impact

calm latch May 10, 2026, 9:58 AM

#

Like what this saves me from is trying to figure out how to synchronize multiple bitmaps in userspace

loud ice May 10, 2026, 9:59 AM

#

invlpg is 200+ cycles on intel

#

and 100+ on amd

calm latch May 10, 2026, 10:00 AM

#

calm latch Like what this saves me from is trying to figure out how to synchronize multiple...

E.g. with deferred work with uACPI/ multithreaded drivers in general

calm latch May 10, 2026, 10:00 AM

#

loud ice invlpg is 200+ cycles on intel

Then my temp mapping thing is screwed as well

flat badge May 10, 2026, 10:00 AM

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calm latch Like what this saves me from is trying to figure out how to synchronize multiple...

for all threads in my thread pool
    thread.schedule_job(|| syscall_to_enable_bits())

loud ice May 10, 2026, 10:01 AM

#

i would have two tsses, one with all bits set and one with no perms and just switch between the two with ltr tbh

calm latch May 10, 2026, 10:01 AM

#

loud ice i would have two tsses, one with all bits set and one with no perms and just swi...

You can just have one tss and slide its size in GDT

#

But I don't really want iopl emulation

loud ice May 10, 2026, 10:02 AM

#

well really youd need two entries anyway

#

imo iopl is just the better way to solve the problem for the like one driver which needs it

calm latch May 10, 2026, 10:02 AM

#

Not if you have per-CPU GDT

loud ice May 10, 2026, 10:02 AM

#

encoding a gdt entry isnt free either

calm latch May 10, 2026, 10:02 AM

#

(or like you can wrap it with a lock or whatever, since ltr is cached)

loud ice May 10, 2026, 10:03 AM

#

a lock is even worse tbh

calm latch May 10, 2026, 10:03 AM

#

loud ice encoding a gdt entry isnt free either

You're changin a couple of bytes in it

#

But sure

loud ice May 10, 2026, 10:03 AM

#

yeah idk which fields contain the size tbh

calm latch May 10, 2026, 10:03 AM

#

Idk either tbh but it doesn't matter

calm latch May 10, 2026, 10:04 AM

#

loud ice imo iopl is just the better way to solve the problem for the like one driver whi...

But something something microkernel something something capabilities something something process isolation

flat badge May 10, 2026, 10:04 AM

#

I'd just have per-thread bitmaps

#

which is what Managarm exposes

#

then you just ltr on task switch

loud ice May 10, 2026, 10:05 AM

#

calm latch But something something microkernel something something capabilities something s...

you have a capability for yolo

#

you are never creating a capability which only lets you do acpi and nothing else

calm latch May 10, 2026, 10:05 AM

#

but you don't have uacpi in userspace...

loud ice May 10, 2026, 10:05 AM

#

calm latch but you don't have uacpi in userspace...

well i dont have uacpi at all

flat badge May 10, 2026, 10:05 AM

#

except for switches between tasks with no enabled io ports, for these you just keep a global tss

calm latch May 10, 2026, 10:05 AM

#

yeah, ofc

loud ice May 10, 2026, 10:05 AM

#

loud ice you are never creating a capability which only lets you do acpi and nothing else

like thats not really a thing in practice

flat badge May 10, 2026, 10:06 AM

#

well, for acpi i agree that just iopl-like control is fine but you also need pio for some pcie drivers

loud ice May 10, 2026, 10:06 AM

#

its not on the fast path for them though, right?

calm latch May 10, 2026, 10:07 AM

#

you need pio for a bunch of stuff on x86

loud ice May 10, 2026, 10:07 AM

#

@fiery turtle you shouldnt be using volatile loads when you do sync btw (this is source/mutex.c)

#

and also cmpxchg_weak is a thing

calm latch May 10, 2026, 10:08 AM

#

Like idk, I have ns16550 and PS/2 drivers for example, both of those need 2-4 IO ports, like it would be nice to not have to give them out full iopl

loud ice May 10, 2026, 10:08 AM

#

i guess

#

~~this is where kernlets come in~~

fiery turtle May 10, 2026, 10:09 AM

#

yeah we discussed this before

#

i just never fixed it

loud ice May 10, 2026, 10:09 AM

#

ah ok

calm latch May 10, 2026, 10:09 AM

#

how many cycles is in/out stuff?

fiery turtle May 10, 2026, 10:09 AM

#

loud ice and also cmpxchg_weak is a thing

not in the uacpi atomic bindings

#

how does it help anyway

loud ice May 10, 2026, 10:09 AM

#

calm latch how many cycles is in/out stuff?

many

loud ice May 10, 2026, 10:09 AM

#

fiery turtle how does it help anyway

on arm its faster

#

sometimes by a lot

fiery turtle May 10, 2026, 10:09 AM

#

arm doesnt have a global lock

#

this is for non-hw-reduced

loud ice May 10, 2026, 10:10 AM

#

oh is it an x86 meme

#

okay then yeah it doesnt matter

fiery turtle May 10, 2026, 10:10 AM

#

whast the diff btw

loud ice May 10, 2026, 10:10 AM

#

weak is allowed to randomly fail

fiery turtle May 10, 2026, 10:10 AM

#

ah ok

#

when would u use a non-weak if its faster?

calm latch May 10, 2026, 10:10 AM

#

Like would 200-400 cycles for 2 invlpgs even matter compared to the IO itself?

loud ice May 10, 2026, 10:10 AM

#

fiery turtle when would u use a non-weak if its faster?

if you need it to not fail spuriously

calm latch May 10, 2026, 10:10 AM

#

calm latch Like would 200-400 cycles for 2 invlpgs even matter compared to the IO itself?

(and mind you, only if you have two different servers running on the same CPU)

fiery turtle May 10, 2026, 10:11 AM

#

ah ok basically where u dont expect it to fail

loud ice May 10, 2026, 10:11 AM

#

calm latch Like would 200-400 cycles for 2 invlpgs even matter compared to the IO itself?

lol no

#

#

the really big number is throughput

calm latch May 10, 2026, 10:11 AM

#

Also, I don't have PCIDs, so I just TLB flush anyway

loud ice May 10, 2026, 10:11 AM

#

(in order: alder lake P, aalder lake E, zen5)

#

also lol doing an OUT on alder lake causes the JMP unit to do things

#

i wonder why meme

calm latch May 10, 2026, 10:12 AM

#

Syscall is also like 50 cycles for the instruction itself + however long the kernel takes to do its stuff

loud ice May 10, 2026, 10:12 AM

#

its a lot more than 50 iirc

calm latch May 10, 2026, 10:13 AM

#

loud ice

What about ltr? (and also, which website is this?)

loud ice May 10, 2026, 10:13 AM

#

calm latch What about ltr? (and also, which website is this?)

uops.info

#

they dont list ltr

loud ice May 10, 2026, 10:13 AM

#

calm latch Syscall is also like 50 cycles for the instruction itself + however long the ker...

on linux on arm (apple m1 p core), its 350 cycles end to end so its actually not that bad

#

i think its a bit more on x86

calm latch May 10, 2026, 10:14 AM

#

Also, I guess it could be faster with FRED?

#

Since they've gotten rid of GDT memes

loud ice May 10, 2026, 10:16 AM

#

loud ice on linux on arm (apple m1 p core), its 350 cycles end to end so its actually not...

so actually maybe a syscall is faster

#

because you gain however much time loading a tss takes

#

and you lose a few hundred cycles for a syscall which is not that much compared to the actual op

calm latch May 10, 2026, 10:20 AM

#

How slow is FP/vector stuff save/restore on x86?

loud ice May 10, 2026, 10:21 AM

#

no idea

flat badge May 10, 2026, 10:52 AM

#

fiery turtle when would u use a non-weak if its faster?

non-weak compiles to a retry loop where weak sometimes does not need one

#

so if you do the non-weak version in a retry loop you have nested retry loops

#

which is unnecessary

fiery turtle May 10, 2026, 10:53 AM

#

makes sense

#

maybe its relevant for itanium

#

which is the other non-hw-reduced platform

flat badge May 10, 2026, 10:53 AM

#

it's relevant for all ll/sc archs

fiery turtle May 10, 2026, 10:53 AM

#

is itanium one?

flat badge May 10, 2026, 10:53 AM

#

idk ¯_(ツ)_/¯

fiery turtle May 10, 2026, 10:54 AM

#

The Intel Itanium (IA-64) architecture does not use the traditional Load-Link/Store-Conditional (LL/SC) paradigm for atomic operations found in many RISC architectures (like MIPS or ARM).Instead, Itanium utilizes a combination of predication, speculation, and explicit, serialized memory instructions within its EPIC (Explicitly Parallel Instruction Computing) design to handle atomic operations and synchronization.

#

looks like it has cmpxchg in the isa

calm latch May 10, 2026, 11:26 AM

#

Does Itanium have defined PE format and clang PE target? ultrameme

#

(Ultra meme)

fiery turtle May 10, 2026, 11:27 AM

#

yes but no emulator support

#

trust me i wish it was relevant

calm latch May 10, 2026, 11:38 AM

#

This is so sad...

#

The used servers are expensive

#

(I need to stop geting sad about random things which don't matter)

fiery ice May 10, 2026, 12:46 PM

#

@fiery turtle What stage of the normal init i have to be to use uacpi_table_find_by_signature?

fiery turtle May 10, 2026, 12:53 PM

#

fiery ice <@353593948523986945> What stage of the normal init i have to be to use uacpi_ta...

uacpi_table_subsystem_available()

fiery ice May 10, 2026, 12:54 PM

#

oh cool

#

thx

calm latch May 10, 2026, 1:38 PM

#

calm latch Idk I'll implement it and you can look at the code <:trl:829316641191886888>

Well, I've gotten this insanity to work (as iopl emulation for now trl )
https://gitlab.com/mishakov/pmos/-/commit/113af29a8ea0eb11ebfbb0ae026e58ed72255a87

#

What's missing is capability and logic to set/clear the right bits (and i686), which is like nothing

#

And also I'm missing an invlpg when coming from tlb shoptdown routine

gentle peak May 10, 2026, 9:28 PM

#

loud ice many

isn't that heavily dependent on what hardware you're accessing with it

loud ice May 10, 2026, 9:41 PM

#

gentle peak isn't that heavily dependent on what hardware you're accessing with it

my understanding is that even in the best case scenario its many

calm latch May 12, 2026, 5:36 PM

#

Does uacpi_namespace_node never get freed after getting it in uacpi_namespace_for_each_child?

#

I need it for a IPC thing where the drivers can request interrupts from my server with uACPI, where I plan to save the namespace node in some per-device thing, and then call _CRS to get the resources

#

(I mean managarm doesn't seem to free it at any point?)

fiery turtle May 12, 2026, 6:01 PM

#

nodes exposed to client code are permanent

calm latch May 12, 2026, 6:45 PM

#

So, do I need to go through ISA int overrides to get IOAPIC for this?

fiery turtle May 12, 2026, 6:49 PM

#

Yes

rustic compass May 13, 2026, 6:36 AM

#

@fiery turtle when will uacpi 5.0 likely be released?

fiery turtle May 13, 2026, 10:04 AM

#

Tbh it only depends on my laziness to write tests and finish what I wanted

#

Soon ™

uneven wave May 14, 2026, 12:16 PM

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Could uacpi_kernel_wait_for_work_completion be replaced with a call to uacpi_kernel_schedule_work where the work item signals a semaphore? Would make the kernel API simpler.

pallid lava May 14, 2026, 12:18 PM

#

and why not do that in wait_for_work_completion?

#

it's up to you how you implement workqueues

fiery turtle May 14, 2026, 12:19 PM

#

uneven wave Could uacpi_kernel_wait_for_work_completion be replaced with a call to uacpi_ker...

Because it must also wait for inflight interrupts, but also I don't see much benefit in this

pallid lava May 14, 2026, 12:19 PM

#

also that would imply adding a new type of work

fiery turtle May 14, 2026, 12:19 PM

#

Yeah

#

Also a lot of people using uacpi have completely broken or stubbed event api support, so the less thats used the better

pallid lava May 14, 2026, 12:22 PM

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everyone knows that the best workqueue is executing the work in place trl

fiery turtle May 14, 2026, 12:23 PM

#

Technically if you execute uACPI interrupts in a preemptible context, nothing wrong with that

calm latch May 14, 2026, 1:58 PM

#

uneven wave Could uacpi_kernel_wait_for_work_completion be replaced with a call to uacpi_ker...

I spin up a pthread for work queue stuff, and pthread_join it untill there are no more threads

fiery ice May 16, 2026, 3:24 PM

#

@fiery turtle in uacpi_kernel_install_interrupt_handler, irq is an external interrupt that will go trough the IOAPIC, right?

torpid root May 16, 2026, 3:28 PM

#

__ensure(irq == 9);

fiery ice May 16, 2026, 3:34 PM

#

torpid root __ensure(irq == 9);

?

frank canopy May 16, 2026, 3:35 PM

#

fiery ice <@353593948523986945> in uacpi_kernel_install_interrupt_handler, irq is an exter...

yes. it's almost always gsi 9 though

#

fwiw

fiery ice May 16, 2026, 3:36 PM

#

oh

frank canopy May 16, 2026, 3:36 PM

#

but yeah it goes through ioapic

fiery ice May 16, 2026, 3:36 PM

#

perfect, thx

frank canopy May 16, 2026, 3:37 PM

#

(and the isa interrupt stuff in madt too)

fiery turtle May 16, 2026, 3:37 PM

#

fiery ice <@353593948523986945> in uacpi_kernel_install_interrupt_handler, irq is an exter...

Its a legacy isa interrupt number

#

Thats subject to the same translation as any other legacy interrupt

fiery ice May 16, 2026, 3:37 PM

#

ok so ioapic it is

#

time to make an interrupt allocator

fiery turtle May 16, 2026, 3:37 PM

#

But yeah you can hardcode it to 9 which it is always

fiery turtle May 17, 2026, 9:33 AM

#

From the @fiery ice acpi dump that tried to map a bogus addres in @calm latch pmos:

OperationRegion (HBUS, PCI_Config, Zero, 0x0100)
Field (HBUS, DWordAcc, NoLock, Preserve)
{
    Offset (0x40), 
    EPEN,   1, 
        ,   11, 
    EPBR,   20, 
    Offset (0x48), 
    MHEN,   1, 
        ,   14,
    // 17 bit value, some sort of a base register? 
    MHBR,   17, 
}

Name (MH_B, Zero)

Method (GMHB, 0, Serialized)
{
    If ((MH_B == Zero))
    {
        MH_B = (MHBR << 0x0F)
    }

    Return (MH_B)
}

OperationRegion (MBAR, SystemMemory, (\_SB.PC00.GMHB () + 0x7100), 0x1000)
Field (MBAR, ByteAcc, NoLock, Preserve)
{
    Offset (0x10), 
    RBAR,   64
}

Method (IOMA, 0, NotSerialized)
{
    Return ((^RBAR & 0xFFFFFFFFFFFFFFFE))
}

Method (PIDS, 0, NotSerialized)
{
    Return (0x00C10000)
}

// The region that tried to map bogus value
OperationRegion (IOMR, SystemMemory, (IOMA () + PIDS ()), 0x0100)

#

I've extracted the important parts

#

so it gets some sort of a 17-bit base address from PCI config space, then shifts it up by 0xF bits. The it offsets it by 0x7100 and reads a 64-bit base address from that, which it ANDs with 0xFFFFFFFFFFFFFFFE

#

#

this was the address

#

@fiery ice i think we need a managarm test here before digging deeper or smth

#

Also whats funny is that aml has a shit ton of non stripped debug logs

#

calm latch May 17, 2026, 9:42 AM

#

But what's weird is that all other addresses looked fine?

fiery turtle May 17, 2026, 9:42 AM

#

Yeah hard to say why it could be bogus

calm latch May 17, 2026, 9:43 AM

#

Maybe my kernel map is broken?

fiery turtle May 17, 2026, 9:43 AM

#

thats why i said we should try managarm or smth before continuing

#

also make sure the pci map is correct as well

calm latch May 17, 2026, 9:44 AM

#

Which is this https://gitlab.com/mishakov/pmos/-/blob/main/userspace/devicesd/generic/uacpi.c?ref_type=heads#L34

calm latch May 17, 2026, 9:44 AM

#

fiery turtle also make sure the pci map is correct as well

Yeah, it could be broken

calm latch May 17, 2026, 9:44 AM

#

calm latch Which is this <https://gitlab.com/mishakov/pmos/-/blob/main/userspace/devicesd/g...

But no, it can't be

#

Wait a sec, I'm not at my PC, but I've printed what was given to me by uACPI directly

fiery turtle May 17, 2026, 9:45 AM

#

well it could be a result of the previous mapping being incorrect

#

since that value is fetched as 10 indirections

calm latch May 17, 2026, 9:47 AM

#

The mapping should be correct though

#

Was it above 4GB?

#

Maybe I'm truncating uint64_t somewhere

fiery turtle May 17, 2026, 9:48 AM

#

who knows, we're only seeing a tiny portion of the log

calm latch May 17, 2026, 9:48 AM

#

Though flanterm wouldn't work then

#

Since the framebuffer is at 512GB on my PCs

#

Also, I've added code to deduce caching types from e820, so in theory that should also be correct

#

Not that long ago

fiery turtle May 17, 2026, 9:50 AM

#

that probably doesnt matter that much on x86 since MTRRs

calm latch May 17, 2026, 9:51 AM

#

Yeah, but like in case they are broken

#

Another thing that can be tried is the i686 build trl

fiery turtle May 17, 2026, 9:58 AM

#

yeah

#

i checked that the 17-bit load from the exact geometry register layout is performed correct

#

just compared the result against acpica runner

calm latch May 17, 2026, 10:00 AM

#

But my PC doesn't want to turn on, and my laptop doesn't have disk space for that build

#

via etherwake

#

But still, how would that address go through AND?

fiery turtle May 17, 2026, 10:07 AM

#

That and only removes the bottom 1 bit

#

Which you can see is not set in the map request

#

Why did you refuse to map it btw, what check do you have there

calm latch May 17, 2026, 10:10 AM

#

Idr, I think it checks that the address is below 1 << 52

#

Idr if I get it from cpuid or not

#

Maybe even 1 << 48

fiery turtle May 17, 2026, 10:11 AM

#

Ah

calm latch May 17, 2026, 10:13 AM

#

trl

calm latch May 17, 2026, 10:14 AM

#

fiery turtle

But this addr is beyong 1 << 52, no?

fiery turtle May 17, 2026, 10:16 AM

#

Yeah I'm not saying its right

#

I was just curious

calm latch May 17, 2026, 10:18 AM

#

Was the maximum phys addr in some cpuid thing?

#

on x86

fiery turtle May 17, 2026, 10:20 AM

#

Yes

calm latch May 17, 2026, 10:23 AM

#

Wtf is TME-MK?

#

Who needs memory encryption

fiery turtle May 17, 2026, 10:24 AM

#

SEV etc is a popular thing as of recent

calm latch May 17, 2026, 10:27 AM

#

This is nice

#

Up to 40 (3) with no (3)

#

Oh, it was on the next page, nevermind

fiery ice May 17, 2026, 11:38 AM

#

fiery turtle <@573903151472836609> i think we need a managarm test here before digging deeper...

ok, what do i have to do after booting it? and do you have an ISO?

fiery turtle May 17, 2026, 11:40 AM

#

just press the power button

fiery turtle May 17, 2026, 11:41 AM

#

fiery ice ok, what do i have to do after booting it? and do you have an ISO?

https://builds.managarm.org/projects/managarm/success/repo/files/x86_64/image.xz

fiery ice May 17, 2026, 11:42 AM

#

fiery turtle https://builds.managarm.org/projects/managarm/success/repo/files/x86_64/image.xz

oh it's there, thx

fiery ice May 17, 2026, 11:44 AM

#

fiery turtle https://builds.managarm.org/projects/managarm/success/repo/files/x86_64/image.xz

wait, how do i boot this via an usb?

#

fiery turtle May 17, 2026, 11:44 AM

#

unxz + dd

fiery ice May 17, 2026, 11:44 AM

#

ah pain

#

time to find another usb

#

ok writing

fiery turtle May 17, 2026, 11:47 AM

#

Hopefully it doesn't crash for other unrelated reasons

#

This is one of those cases where I wish there was a reference uacpi kernel

fiery ice May 17, 2026, 11:47 AM

#

fiery turtle Hopefully it doesn't crash for other unrelated reasons

let's hope

torpid root May 17, 2026, 11:47 AM

#

sudo dd if=image of=/dev/sda

fiery ice May 17, 2026, 11:47 AM

#

rn rufus is being slow to write

#

lol

fiery turtle May 17, 2026, 11:50 AM

#

We can try obos if this doesn't work trl

fiery ice May 17, 2026, 11:51 AM

#

lol

calm latch May 17, 2026, 11:53 AM

#

fiery turtle This is one of those cases where I wish there was a reference uacpi kernel

How are Haiku and ROS going?

fiery turtle May 17, 2026, 11:53 AM

#

No idea tbh, im not monitoring that closely

fiery ice May 17, 2026, 11:57 AM

#

this is slow XD

fiery turtle May 17, 2026, 11:58 AM

#

Is this like a usb1 drive lol

calm latch May 17, 2026, 12:04 PM

#

I recently bought a Kingston drive in a store without research, and even though it's USB 3 and from a reputable manufacturer, it has very slow write speeds as well

fiery ice May 17, 2026, 12:15 PM

#

fiery turtle Is this like a usb1 drive lol

usb2

#

it is just rufus that is slow af

#

ok, booting managarm weston

hallow marten May 17, 2026, 12:16 PM

#

no its probably just your drive lol

fiery ice May 17, 2026, 12:17 PM

#

hallow marten no its probably just your drive lol

i can copy an iso to it very fast

#

but writing with rufus is slow

#

lol, managarm is misreading my battery XD

#

by a lot

#

it says it has like 1MWh XD

#

and is charging

#

while it's def not

fiery turtle May 17, 2026, 12:18 PM

#

What about the pwr BTN tho

fiery ice May 17, 2026, 12:19 PM

#

it's still booting...

fiery turtle May 17, 2026, 12:19 PM

#

Bruh

fiery ice May 17, 2026, 12:19 PM

#

it's at PRNG reseeding rn

fiery ice May 17, 2026, 12:20 PM

#

fiery turtle Bruh

#

i pressed the power btn while here and it threw assertion failed

#

and now it is not doing anything

fiery turtle May 17, 2026, 12:21 PM

#

Ffs I thought that assert was fixed lol

fiery ice May 17, 2026, 12:21 PM

#

XD

fiery turtle May 17, 2026, 12:21 PM

#

@north holly can you give an obos ISO

fiery ice May 17, 2026, 12:23 PM

#

the latest iso on their server is from 2025....

fiery turtle May 17, 2026, 12:24 PM

#

Wait wtf

fiery ice May 17, 2026, 12:24 PM

#

fiery turtle Wait wtf

fiery turtle May 17, 2026, 12:41 PM

#

Oh u mean obos

#

Tbh u can probably use this one just find

fiery turtle May 17, 2026, 12:41 PM

#

fiery ice

Try the minimal one maybe

fiery ice May 17, 2026, 12:42 PM

#

fiery turtle Try the minimal one maybe

but does that version even have uacpi?

fiery turtle May 17, 2026, 12:43 PM

#

Ofc

fiery ice May 17, 2026, 12:45 PM

#

it went into instant kernel panic 💀

calm latch May 17, 2026, 12:45 PM

#

trl

#

Do I ask clanker to verify my PCI code?

fiery ice May 17, 2026, 12:45 PM

#

try

calm latch May 17, 2026, 12:46 PM

#

Tbh, I also saw some weirdness with it on my macbook in ahci driver, before I moved it to devicesd

#

Though it's weird...

#

I'm also compiling a i686 build

#

I also added a check to get the proper max phys addr now...

fiery turtle May 17, 2026, 12:49 PM

#

fiery ice it went into instant kernel panic 💀

what was the reason

calm latch May 17, 2026, 12:49 PM

#

calm latch I also added a check to get the proper max phys addr now...

📎 pmos-hyper.iso

fiery turtle May 17, 2026, 12:49 PM

#

bruh how is there not a single bootable hobby kernel trl

calm latch May 17, 2026, 12:49 PM

#

Mine is bootable trl

#

Who else had a competent kernel?

#

(i mean with a power button/shutdown driver)

fiery ice May 17, 2026, 12:50 PM

#

fiery turtle what was the reason

idk, right after it prints the logo

#

it crashes

calm latch May 17, 2026, 12:50 PM

#

Ironclad uses uACPI??

fiery ice May 17, 2026, 12:50 PM

#

calm latch

should i try this?

calm latch May 17, 2026, 12:51 PM

#

You could

#

Like it's the same image, just with max phys addr from CPUID

#

My i686 image is still compiling

#

I mean you can also just replace devicesd with a 32 bit version

fiery ice May 17, 2026, 12:53 PM

#

calm latch You could

calm latch May 17, 2026, 12:53 PM

#

If my compat mode hadn't bitrotted

#

Don't think it would change anuthing though

fiery ice May 17, 2026, 12:54 PM

#

fiery ice

#

one new message now

#

devicesd just GPF'd after a bit

calm latch May 17, 2026, 12:54 PM

#

pthread_exit is broken

#

because it couldn't shut down

fiery turtle May 17, 2026, 12:54 PM

#

oh btw

calm latch May 17, 2026, 12:54 PM

#

this is normal-ish given the circumstances trl

fiery turtle May 17, 2026, 12:55 PM

#

@calm latch can u enable debug logs in uacpi

#uACPI - a portable and easy-to-integrate ACPI implementation