yeah i think that would be cool
#uACPI - a portable and easy-to-integrate ACPI implementation
fiery turtle
gentle peak
alright sounds good
fiery turtle
thanks
fiery turtle
lmao
gentle peak
oh wait i should change the error message for the pointer size thing
fiery turtle
any pr is tiny compared to that one
fiery turtle
very nice, this fixes a lot of code style issues basically
fiery turtle
yeah, pretty cool
gentle peak
decided to make that the subject of the pr anyway since there is one owc-exclusive change (the __386__ one)
gentle peak
i'm diffing rdos's fork against upstream and wtf
at least change it in fucking config.h
fiery turtle
fuck config.h amirit
gentle peak
god windows ci is so slow
fiery turtle
yeah
slim panther
i'm diffing rdos's fork against upstream and wtf
bruh
fiery turtle
gentle peak
alright i rebased test-runner-rewrite on top of watcom-c90
and made it compile in c89 mode
fiery turtle
nice!
gentle peak
one thing that does leave a slightly bad taste in my mouth is that the resource tests will never get executed on owc because they're 64-bit only and owc is 32-bit only
like i'm sure it's fine since all the other test cases pass but i don't really like it
fiery turtle
hmm true thats kinda unfortunate
the only thing gating it is pointer offsets i guess, which is annoying
gentle peak
and due to the pointer size being different the native blobs have different sizes in 32 bit mode
fiery turtle
true
gentle peak
like i commented out the return; to see what would happen and even a bunch of resources without pointer offsets fail due to different sizes
fiery turtle
makes sense
gentle peak
in any case, this is a delight to see in upstream gh actions
fiery turtle
very cool
left orbit
wtf
calm latch
just some small pull request
gentle peak
Weird that I didn't get those on CI since it's supposed to be on max warning level with warnings as errors
They might be getting disabled by the options I added to disable unused parameter warnings
I should probably remove those and use uacpi_unused() instead
fiery turtle
yeah i guess
gentle peak
right, when those ones are fixed you get the same for table_array_calloc, table_array_pop, and table_array_last
and i don't think UACPI_MAYBE_UNUSED can be implemented for owc
i could mark those inline as well but that's a bit ugly imo since they're in a .c file instead of a .h file
and they're not particularly small functions
gentle peak
and i don't think UACPI_MAYBE_UNUSED can be implemented for owc
owc does have unused warning suppression, but it's via pragmas so it'd have to be something like #define UACPI_MAYBE_UNUSED(decl) _Pragma("on (unreferenced)"); decl; _Pragma("off (unreferenced)");
that'd require refactoring every use of UACPI_MAYBE_UNUSED
fiery turtle
bruh
gentle peak
tbf i just looked and uacpi_maybe_unused is only used in dynamic_array.h
so it wouldn't be a huge change
fiery turtle
is this only for unused symbols or parameters?
maybe_unused is only used there iirc yeahy
gentle peak
uacpi_maybe_unused is only used for marking dynamic array functions as potentially unused
it's not used for parameters anywhere (which is good because with this change it wouldn't be possible to use it for that)
gentle peak
i could also see UACPI_NO_UNUSED_PARAMETER_WARNINGS_BEGIN being an issue, there's no separate pragma for parameters and the pragma in question isn't on a stack
so it'd conflict with UACPI_MAYBE_UNUSED(...)
oh and it seems like the pragma doesn't even work lol
unreferenced warnings are still being emitted even with the pragma
fiery turtle
ffs lol
gentle peak
oh wait seems like there is a stack for it at least
not really useful given that the pragma appears to be a no-op, but still
i guess i could make UACPI_MAYBE_UNUSED expand to inline
it seems that's the only way to block unused warnings
fiery turtle
lol
gentle peak
there's also #pragma warning <num> <level> but that can't be pushed/popped
real jetty
Man supporting this compiler is such a chain around your neck
calm latch
uACPI 4.0.0: deprecate openwatcom 
gentle peak
defining uacpi_maybe_unused as inline seems to work well enough
gentle peak
fiery turtle
nice, left a small nit
gentle peak
fixed
gentle peak
once it's merged i'll rebase the ci pr on top of this so that i can get rid of the warning suppression options
fiery turtle
yeah nice
fiery turtle
@trim frost hey I have your PR noted, I'll add you to the leaderboard a bit later when im doing readme changes or other leaderboard additions (since i try to batch them)
keep it open, ill close myself later
fiery turtle
@gentle peak i swear ill get to that pr, work has been a bit insane this week
gentle peak
dw about it lol
fiery turtle
darkfire is taking a break from power managment
the haiku guy always disappears for a month after a bit of activity
fiery turtle
whats the issue
slim panther
but i thought rust was safe :(
trim frost
whats the issue
no issue (well technically there is an issue as putting uacpi init on a thread makes the os hang in debug mode for some reason but i dont plan on doing that))
fiery turtle
it's a bit concerning to run SMP that early lol
I still dislike the limine smp feature because u have to do SMP yourself anyway if you wanna support CPU hotplugging or suspend
also for e.g. large systems linux recently did a big upgrade which improved smp startup speed by a ton
so it can be a bottle neck for large systems
id rather do it myself in this case
gentle peak
wow the GitHub mobile app's review stuff is horrible
fiery turtle
the mobile app is pretty crappy overall
gentle peak
you can't jump to the quoted code at all so all you get is the 3 or 4 lines of context
fiery turtle
lmao
Apparently win32 doesnt have a way to sleep for less than a millisecond
event their STL does milliseconds for the C++ stdlib api i've been using
lilac knoll
Apparently win32 doesnt have a way to sleep for less than a millisecond
that's not really too surprising is it?
this can be quite unreliable
fiery turtle
it is reliable if you use the api correctly
it's not for precise waits, but rather specifying the minimum amount of time you want to sleep
lilac knoll
I mean the scheduler might not schedule you for a ms or two anyway
fiery turtle
sure, who cares, it's an implementation detail
if it can tho, thats still better than making it not schedule the thread because it thinks it wanted to sleep for a ms instead of say 500 us
POSIX has nanosleep and they survived
gentle peak
Yeah it's annoying
Although in this case the microsecond_sleep is only used by kernel_stall, kernel_sleep, and some lock/wait-with-timeout emulation that would still work if the sleep period was 1 ms
I might just increase said sleep periods to 1 ms and make stall actually stall instead of sleep
Then I don't have to do the waitable timer BS
fiery turtle
yeah I guess thats better, I was just too lazy to implement stalling initially
so i used the easy api
but now it doesnt exist
gentle peak
I think I addressed everything that can be addressed without changing code, I'll do the rest tomorrow
hollow crescent
it's a bit concerning to run SMP that early lol
No it is not.
It's easier to make an SMP kernel from the start than a single processor kernel that's then upgraded to SMP
gentle peak
Pretty sure he meant the point within the init sequence, not within development
fiery turtle
^
fiery turtle
It's easier to make an SMP kernel from the start than a single processor kernel ...
That's true
fiery turtle
I think I addressed everything that can be addressed without changing code, I'll...
Yeah makes sense, thx
trim frost
it's a bit concerning to run SMP that early lol
i meant a scheduler thread lmao
gentle peak
addressed all the comments
vast kestrel
it's a bit concerning to run SMP that early lol
I mean, I basically setup memory management and then immediately start the scheduler and smp, and the rest runs from an init thread, and I initialize uacpi from there
gentle peak
i do memory management, uacpi early table access, interrupts, timing, scheduler, vfs, smp, uacpi proper
gentle peak
i've been thinking of implementing something similar
fiery turtle
addressed all the comments
thanks, will take a look in a bit
fiery turtle
we just do dependency based init
does it detect recursive dependencies?
flat badge
wdym by recursive dependencies?
The kernel will only run a step once all deps are done
fiery turtle
what if there's a dependency of a step that has depedencies that accidentally depend on this step
gentle peak
this is how i handle that (i just started implementing an init task thing)
fiery turtle
makes sense
flat badge
what if there's a dependency of a step that has depedencies that accidentally de...
Then it errors out before running anything
Cyclic deps are not allowed
trim frost
no issue (well technically there is an issue as putting uacpi init on a thread m...
it was because my dumass also moved lapic init to the thread
fiery turtle
@gentle peak LGTM as far as contents, but i think the per-commit split is broken atm
fiery turtle
how do u usually add changes to commits?
gentle peak
normally an interactive rebase to the commit i want to edit and change pick to edit
but in this case my split was broken in a different way that i tried to fix
fiery turtle
i find that its easier to just do them on top of the last commit and name them as "fixup! <target-commit>" then just git rebase -i HEAD~N --autosquash and it automatically puts stuff where it needs to go
gentle peak
oo didn't know that existed
fiery turtle
yeah it really helps with this sort of stuff
mortal yoke
also you can make that a git fixup you can run with the changed added + an interactive thing using fzf where you can choose the target commit ```
[alias]
fixup = "!git log -n 50 --pretty=format:'%h %s' --no-merges | fzf | cut -c -7 | xargs -o git commit --fixup"
idr where I got this from but its nice
fiery turtle
damn, no idea what fzf is but thats interesting
mortal yoke
you get this kind of thing where you can select with arrow keys or mouse + enter to choose
fiery turtle
ohh damn
fiery turtle
also you can make that a `git fixup` you can run with the changed added + an int...
is this in your .gitconfig thing?
mortal yoke
yes
fiery turtle
ill definitely try this
mortal yoke
I found the site where I got that from, https://jordanelver.co.uk/blog/2020/06/04/fixing-commits-with-git-commit-fixup-and-git-rebase-autosquash
gentle peak
alright fixed
fiery turtle
I found the site where I got that from, https://jordanelver.co.uk/blog/2020/06/0...
ill be stealing this
didnt know autosquash could be on by default
my fingers hurt from typing it all the time
fiery turtle
alright fixed
nice
alright merged
I hope that completes the OpenWatcom journey lol
almost 1k commits now
gentle peak
I hope that completes the OpenWatcom journey lol
i hope so too lol, it's been interfering with my proxima momentum
gentle peak
yeah i saw that
"why do mutexes have timeouts" when aml literally exposes an acquire with timeout op
fiery turtle
like he has been using acpica previously and it literally has the same api
has that never occured or something
Somehow the uACPI thread has 250k views on osdev forums
wtf
lol
vibe coding acpica
fiery turtle
copy/pasting verbose AI slop should be a criminal offense
it's the only acpica maintainer doing it too
crazy stuff
kindred beacon
rip out ACPICA from linux, replace with uACPI
unironically
ACPICA has been lost entirely now, there's no going back
fiery turtle
lmao
calm latch
I think I should try and implement that to see how it works...
fiery turtle
he's right tho, you must use refcounting here unfortunately
calm latch
Though it would have been more convenient if it was per thread
I don't know/haven't though much about how to do it globally
fiery turtle
while unlikely, there might be multiple opregions in aml mapping the same io range
calm latch
that is not the issue
How do you handle one thread mapping io port, and then other one using it?
fiery turtle
u must synchronize the tss for all threads
calm latch
I guess it's a similar issue to paging
Wait, does x86 look into TSS every time IO port is accessed?
fiery turtle
u can do it lazily as well but u would need an instruction decoder in kernel lol
fiery turtle
Wait, does x86 look into TSS every time IO port is accessed?
probably
calm latch
IO instructions shouldn't be too difficult to decode
fiery turtle
probably
calm latch
u can do it lazily as well but u would need an instruction decoder in kernel lol
I have that already for RISC-V 
fiery turtle
why
calm latch
For lazy FP/vector stuff
calm latch
My kernel doesn't enable them for threads until they're used for the first time
Then it's eager
fiery turtle
hm fair but probably still useless work
unless risc-v is not like x86 and compilers dont use sse unconditionally
calm latch
Not that much work
calm latch
unless risc-v is not like x86 and compilers dont use sse unconditionally
They don't
Also vector extension has only been standardized very recently?
And on LoongArch it's undocumented and to be replaced
mortal yoke
u can do it lazily as well but u would need an instruction decoder in kernel lol
you need that for virtualization stuff too 
calm latch
Though their exceptions are nicer
calm latch
probably
I guess I could allocate TSS per thread
But that's anoying
I guess I could use my TLB shootdowns mechanism
Or something similar
To make sure CPUs use the latest IO bitmap
Though it would be kinda annoying, since the scheduler would have to take locks and stuff...
Maybe I can make per-thread TSS conditional
Since it would only be used by drivers
fiery turtle
microkernel problems 
fiery turtle
you need that for virtualization stuff too <:meme:575445094589661215>
tru
calm latch
Just a couple more syscalls
(I have too many of them)
Also, how does this work on ia32?
flat badge
https://github.com/acpica/acpica/pull/1022
Doesn't this break disassembly?
calm latch
Oh, it's the same
calm latch
Oh, it's the same
basically
fiery turtle
Doesn't this break disassembly?
are u saying u dont trust chatgpt slop to review PRs?
real jetty
Have copilot create a pr and chatgpt review it
calm latch
Maybe I can make per-thread TSS conditional
I think I'll just do conditional TSS and handles for IO port ranges
And slap a lock on that whole thing
The C++ and Rust abstractions should also be nice 
fiery ice
double digits
wtf, how??
frank canopy
is the timer just off by a factor or something??
trim frost
no lol i was messing around with memcpy and other mem functions
fiery ice
no lol i was messing around with memcpy and other mem functions
how did you even manage to make it so slow??
trim frost
how did you even manage to make it so slow??
not accidentally
fiery ice
lol
trim frost
i actually tried spinlooping inside them but couldnt get it to work
crashes
so i did something else
calm latch
I think emulating RISC-V and whatnot also gives very low scores
fiery turtle
double digits
x86 emulation on the gameboy?
trim frost
x86 emulation on the gameboy?
on my nonexistent toaster
keen shard
vibe coding acpica
What does vibe coding even mean
I’ve genuinely never used Ai for programming besides the intellisense which idek if that counts
jaunty fox
What does vibe coding even mean
it's when you just ask an llm to do everything for you
i have no idea why they call it "vibe coding"
rarted terminology
dense steppe
because you're vibing while someone something else codes
surreal current
i have no idea why they call it "vibe coding"
It was coined by a really corny tech bro tweet about how like "i feel so much more in touch with my program... im freed from the irrelevant little details that make programming so tedious... im just vibing with the big picture..." or something
torpid root
isn't it a good idea to use appropriate caching modes for different mappings?
fiery turtle
yea
torpid root
may I ask why uacpi doesn't use it?
calm latch
I think there was already discussion about it, but I can't find it
Iirc ACPI just doesn't give you that information?
torpid root
ah
dense steppe
caching modes also differ heavily between different architectures, and ideally we would keep that away from the kernel interface
frank canopy
the one thing i would like to maybe have if possible actually is a way to differentiate temporary vs long-term mappings
just because of how my memory management works
calm latch
Though on x86 you can probably just get away with mapping everything as cached, wt?
frank canopy
not a big deal to not have but would be nice
dense steppe
the lowest-hanging fruit that I see is a flag passed to uacpi_kernel_map_memory that tells it whether or not this is an ACPI table mapping
calm latch
but even then you've got to modify the tables sometimes
fiery turtle
ah
basically the problem is AML just tells you: map this with this length
uacpi cant possibly know what the hell its mapping
it could be normal ram, or device memory
only the os can know by looking at the memory map and deciding based on that
thats what linux does with acpica mappings for example
fiery turtle
Though on x86 you can probably just get away with mapping everything as cached, ...
yes
calm latch
but even then you've got to modify the tables sometimes
even the global lock is in FACS?
gentle peak
isn't it a good idea to use appropriate caching modes for different mappings?
proxima does this :)
fiery turtle
even the global lock is in FACS?
yep
calm latch
I have to change pmOS to do this as well
gentle peak
it checks whether the range is fully occupied by ram and if so uses wb, if not uc
fiery turtle
AML is also allowed to request table mappings via a special opcode
and write to them all it wants
calm latch
I have to change pmOS to do this as well
The issue is that I don't have good abstractions for memory types across architectures
But like it's probably gonna be super important when I begin porting to ARM
gentle peak
i just use the x86 memory types and let each arch map them to whatever it uses
calm latch
(I mean RISC-V is also probably broken)
gentle peak
(I mean RISC-V is also probably broken)
with risc-v you should have PMA taking care of it for you
but i don't know whether that actually happens in practice
dense steppe
i just use the x86 memory types and let each arch map them to whatever it uses
beware that these don't map one-to-one to e.g. arm
calm latch
I've started with RISC-V types, and it didn't translate well to x86 types, so I just map all normal memory as cached, and everything else as UC
calm latch
beware that these don't map one-to-one to e.g. arm
I think I'll have RAM, MMIO, DMA and framebuffer
frank canopy
i really want to get the FACS mapped somewhere separate so it doesnt stay long term in syspte space tbh. other than that i just map everything as writeback and it seems to work for now
gentle peak
beware that these don't map one-to-one to e.g. arm
yeah i might need to change them to intent flags (i.e. ram/mmio/framebuffer instead of wb/uc/wc)
frank canopy
(i rely on MTRRs to be set up correctly by the loader/bios)
gentle peak
I think I'll have RAM, MMIO, DMA and framebuffer
i feel like dma memory being a separate memory type would get very annoying for zero-copy i/o (aka io directly into the page cache)
dense steppe
i really want to get the FACS mapped somewhere separate so it doesnt stay long t...
I'm pretty sure the FACS resides in normal RAM
fiery turtle
I think I'll have RAM, MMIO, DMA and framebuffer
There's two types of mmio
Strong and normal
Well technically more but
These should do it
gentle peak
what's the difference?
calm latch
Strong and normal
What's the difference?
dense steppe
I'm pretty sure the FACS resides in normal RAM
just based on the semantics of the global lock
frank canopy
(specifically, iirc on x86 the MTRRs can prevent caching even if i say writeback for the cache type on the mapping)
calm latch
i feel like dma memory being a separate memory type would get very annoying for ...
Idk what to do then
frank canopy
I'm pretty sure the FACS resides in normal RAM
oh neat. doesnt actually help my case here because the issue is fragmentation of a buffer of PTEs but still good to know
fiery turtle
what's the difference?
Aarch64 has ridiculously precise caching controls, some devices work with ngnre some require ngnrne iirc
calm latch
Idk what to do then
Maybe I should just add flush caches syscall or something?
I do have zero copy
calm latch
Aarch64 has ridiculously precise caching controls, some devices work with ngnre ...
How do you know the difference then?
gentle peak
Idk what to do then
on sane platforms you just use fences and the platform takes care of it, on arm you need to run cache flushing instructions on the range iirc?
fiery turtle
How do you know the difference then?
You just do
Its device specific
Its normal unless you know otherwise
E.g. most M1 devices require strong mmio
calm latch
So the mapping syscall should take normal ram/mmio/strong mmio/framebuffer/guess argument?
fiery turtle
Yea
calm latch
it checks whether the range is fully occupied by ram and if so uses wb, if not u...
I think I'll just do it per page, since my kernel maps everything lazily anyway
torpid root
proxima does this :)
how does it know which one to use?
torpid root
it checks whether the range is fully occupied by ram and if so uses wb, if not u...
ah
gentle peak
(in this case ram includes acpi reclaimable and such regions)
(actual kernel-owned ram is not allowed to be accessed by acpi, and the kernel enforces this)
torpid root
one more entry in my todo list
frank canopy
ok now i want to know why the debug info thinks uacpi_set_waking_vector is at address 0
fiery turtle
lol
fiery turtle
let me just quickly disable semaphores
calm latch
What's the issue with having them in the first place?
slim panther
cant he just admit his kernel is trash
calm latch
Does he not have multithreading?
Like even if the kernel is complete trash, you can implement those in userspace
slim panther
what a great os
calm latch
surreal current
part of me just wants to ignore him
yk how im always shitting on the forums boomers
slim panther
me when I'm stupid
i 100% bet that this guy does not have the skills to write assembly that's faster than gcc
fiery turtle
How did he run acpica before even
no idea tbh
slim panther
i mean it makes sense that he says that because owcc doesn't seem to do any optimizations 
real jetty
If I had to work with that compiler id be tempted to use asm instead too...
surreal current
wonder if hes even aware of the concept of mapping a file into kernel space as demand-paged memory and doing cached io by memcpying through that window
which bypasses toooooons of layering machinery in the cached case
reduces it to a window lookup and copy
real jetty
I can't imagine anyone reasonable would write page cache in asm honestly
jaunty fox
some say you don't need to optimize the file-system since the disk drives are slow anyway
some say? who says that
gentle peak
the voices in his head
jaunty fox
what a lot of people really say: you need to optimise BECAUSE the disk drives are slow
slim panther
like the rest of his delusions
jaunty fox
wonder if hes even aware of the concept of mapping a file into kernel space as d...
his buffer cache appears to be http://svn.rdos.se/rdos/trunk/kernel/fs/dev/vfsbuf.asm
slim panther
bro what
this guy has been at it for over 20 years???
what is that copyright date
gentle peak
rdos is ancient
slim panther
and no fucking acpi?????
surreal current
his buffer cache appears to be http://svn.rdos.se/rdos/trunk/kernel/fs/dev/vfsbu...
appears to be what
jaunty fox
appears to be what
a traditional buffer cache
slim panther
wow this guy has actually lost the plot
gentle peak
and no fucking acpi?????
he had acpica before i think
slim panther
still
jaunty fox
it might not be, i haven't looked in any depth
jaunty fox
anyway his fat driver is written in c++ http://svn.rdos.se/rdos/trunk/kernel/fs/fat/
slim panther
jaunty fox
so i'm not sure why he slates C for filesystems so much if his in C++
hasty plinth
surreal current
i must outdo the 20 yr old boomer project in like 2 years
torpid root
it's not that bad
gentle peak
why put the name in the fucking comment when it's right above the member it's documenting
slim panther
calm latch
Does he have SMP?
fiery turtle
why put the name in the fucking comment when it's right above the member it's do...
lmao
fiery ice
https://github.com/uACPI/uACPI/issues/132
oof, he is back
mortal yoke
btw I tested this again because I couldn't get it to work last time I tried it but now I got it to work on an alderlake igpu with these changes to qemu on top of the changes those patch introduced which are now upstreamed to make it set up the opregion for it even when its not the boot gpu as its not reported as vga compatible if its not + this https://github.com/tomitamoeko/VfioIgdPkg (with the other patch applied because of the same reason) + IntelGopDriver.efi extracted from a bios update (also needs a patch to nop out a check at 0xa3d when the igpu is not the primary boot gpu as it checks for the vga class)
now the real question is whether the shotplug register is broken with this, hopefully not
fiery turtle
maybe upstream it as well?
there were some new patches i saw on the mailing list
about igd stuff i think
like literally today
mortal yoke
looks like there is some typo fix + a patch to respect x-igd-opregion=off
yeah I should probably upstream these (though I can't really do anything about the IntelGopDriver patch except make a mention of it somewhere)
hollow crescent
why put the name in the fucking comment when it's right above the member it's do...
Redundancy
Because what if you document the wrong function with your comment
/j
gentle peak
good point
mortal yoke
lol
also for tables you have basically no way of knowing which ones you can make read-only (except the ones that are defined by acpi as static tables you don't write to ig)
fiery turtle
also aml might remap them and write to them if it wants to
via DataRegion or wahtever its called
dense steppe
how does an AML interpreter deal with self-modifying AML at all?
like it just sounds like a nightmare to wrap your head around
fiery turtle
methods are stored in heap allocated buffers (at least in uacpi and nt) so its not possible
well it could technically modify the dsdt as it's being loaded
that would not go well
vast kestrel
Have a template ssdt that patches and loads as required :^)
Also imagine deprecating Unload 😔
Can't have dynamic code loading/unloading smh
flat badge
how does an AML interpreter deal with self-modifying AML at all?
self modifying AML is not supported
AML has explicit opcodes that you could use to load code
at runtime
flat badge
also for tables you have basically no way of knowing which ones you can make rea...
well, everything that is in AddressRangeACPI can be maped as r/o
fiery turtle
Also imagine deprecating Unload 😔
The world is not ready for it
Aml is ahead of its time
flat badge
nah AML is just completely broken
fiery turtle
Shh
slim panther
bro just give up
fiery turtle
what happens if I try to unload a control method by doing `CopyObject` over it?
Don't try with acpica instances near you
gentle peak
well, everything that is in AddressRangeACPI can be maped as r/o
aren't you supposed to write to the FACS at times? or is that not in addressrangeacpi?
flat badge
nah AML is just completely broken
seriously though, the main problem is that nobody designed AML in a consistent way
it's basically just Intel and Microsoft adding whatever adhoc stuff they needed to solve their next problem
fiery turtle
It was designed by incompetent firmware devs, not language designers
flat badge
it's object model is completely broken
the core VM is also completely broken
like, why are there 8 registers available
without any compiler support to do register allocation
that's just lazy AF
fiery turtle
Should have been wasm 😔
Or any non recursive bytecode with well defined semantics
fiery ice
jvm is one of the best
flat badge
wasm as not a thing at that time but the jvm was
vast kestrel
Shhhhh
kind mantle
Riscv as a vm :^)
The V stands for virtual machine
fiery ice
he should learn how to code his kernel and apis properly
slim panther
fiery ice
(and use a good compiler)
slim panther
tell him that uacpi requires a mature kernel
kind mantle
This seems like the kind of person to think they know everything but actually not
fiery ice
mine is not mature but still works, lol
you just need to implement the apis
lol
i still need to add PCI tho
kind mantle
mine is not mature but still works, lol
mine is damn near the slowest one on the leaderboard
fiery ice
mine is damn near the slowest one on the leaderboard <:KEKW:913708372329644042>
how fast?
kind mantle
I am a prophesshional kernle dev trust me (fr fr)
1.02M ops/s
The next up is 1.5M ops/s
fiery ice
that's still better than most
vast kestrel
Uacpi-os was done in a weekend :^)
fiery ice
well, still better than Nyaux
kind mantle
The slowness was probably down to my mutexes, which I have re-worked since.
kind mantle
I'll measure again later but first I need to fix a lot of other stuf f
fiery ice
(and prob bc i am using PIT to measure the time too)
kind mantle
well, still better than Nyaux
Well you see not by much
fiery ice
i hope to finish the scheduler soon
so i can add threads to uACPI
and then finish the APICs
torpid root
@fiery ice can you try this one
fiery ice
k
torpid root
that just uses the old bitmap allocator
if it doesn't work, the problem is somewhere else
kind mantle
btw did we end up settling on a standard way to test kernel performance for uACPI?
torpid root
1.02M ops/s
what's your memcpy and memset?
fiery ice
it's a different RIP
kind mantle
what's your memcpy and memset?
torpid root
https://github.com/badgeteam/BadgerOS/blob/6eaf51d5336d5f7531431b39c83404a1c3202...
do movsb
keen shard
i 100% bet that this guy does not have the skills to write assembly that's faste...
I don’t even think he knows any mnemonic besides mov
slim panther
mov is turing complete
kind mantle
do movsb
This is non arch-specific, I won't hardcode something like that
BadgerOS has both RISC-V and x86_64 support
torpid root
This is non arch-specific, I won't hardcode something like that
make that a weak symbol and define memcpy/memset in x86_64 code
fiery ice
This is non arch-specific, I won't hardcode something like that
my mem things if you want
try with these
kind mantle
lmao you think that's gonna be faster than mine
torpid root
lmao you think that's gonna be faster than mine
or just use phd memcpy from mammogram
kind mantle
mammogram
flat badge
as if that memcpy was that complicated
fiery ice
what
flat badge
it's just thinking about how it'd work in asm and then hacking C until it generates the desired asm :^)
kind mantle
Managarm memcpy does misaligned access if the pointers are misaligned, mine doesn't. On RISC-V, misaligned access can be slow or even cause a trap.
torpid root
make that a weak symbol and define memcpy/memset in x86_64 code
^
uacpi points are x86_64 only
kind mantle
I know
Either way, though, I'm going to phinnish my device refactor first.
x86_64 probably won't boot before then
flat badge
Managarm `memcpy` does misaligned access if the pointers are misaligned, mine do...
what do you do instead? fall back to single byte accesses?
kind mantle
what do you do instead? fall back to single byte accesses?
If misaligned, yes, single-byte access. I don't bother measuring unaligned access speed on RISC-V yet.
flat badge
i'm aware that Managarm's memcpy does this but i don't think it's a problem: unless misaligned accesses are implemented in software, doing the misaligned accesses will still be faster than single byte accesses. you're correct that RISC-V allows M mode to implement them in software and hence they can be very slow. however, a physical CPU that does implement them in SW will likely not be powerful enough to run Managarm anyway
kind mantle
i'm aware that Managarm's memcpy does this but i don't think it's a problem: unl...
SiFive FU740 SOC has no hardware misaligned access and it's definitely capable of booting Managarm provided the drivers appropriate work, which they didn't seem to last time.
flat badge
are you sure that it has no hw misaligned access?
kind mantle
Yes. I read the datasheet.
fiery turtle
btw did we end up settling on a standard way to test kernel performance for uACP...
I'm gonna get a 9950x3d soon and I'm gonna remove all leaderboard scores
Will do all tests on my desktop probably
flat badge
Yes. I read the datasheet.
ah, you're right
fiery turtle
To remove that CPU column
flat badge
tbh that surprises me
kind mantle
https://www.sifive.com/document-file/freedom-u740-c000-manual page 52 for anyone wondering.
flat badge
yeah in that case you have to do the check first and resort to single byte accesses or similar
kind mantle
yeah in that case you have to do the check first and resort to single byte acces...
There's probably slightly more optimal things possible but yeah
Like cursed bit shift memes
Will be faster on any RISC-V cpu larger than a literal microcontroller.
kind mantle
or emulate the unaligned access using the trap
Well that's what we're avoiding in a memcpy routine
flat badge
fwiw all rva profile implementations will need to support this going forward
Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.
kind mantle
Good.
fiery turtle
https://www.sifive.com/document-file/freedom-u740-c000-manual page 52 for anyone...
Trying to squeeze every penny to save
kind mantle
RISC-V really didn't put their foot down enough for profiles meant to be desktop or server or whatever chips.
flat badge
Like cursed bit shift memes
that's true, but it sounds kinda annoying to implement
- the more conditions you need to test for the slower the fast path gets
kind mantle
that's true, but it sounds kinda annoying to implement
It probably would be, but still faster than single-byte.
For large sizes at least.
flat badge
unclear if it's worth it tbh
kind mantle
idk.lol
flat badge
you can still do pipelining with single byte accesses
like, load ~16 bytes or so, store 16 bytes
kind mantle
Yeah but the memory ports can usually still do word-sized accesses.
flat badge
sure but you need at least 3 instructions or so to do the shift
kind mantle
I love that we somehow went from an ACPI discussion to discussing how unaligned memcpy would be implemented on a CPU without HW misaligned access
calm latch
#lounge2
kind mantle
`#lounge2`
true
gentle peak
"i don't keep that information" then either start keeping it or accept that you're mapping everything as rw and relying on mtrrs for caching
fiery turtle
how is that our problem that his kernel is poorly designed
left orbit
why even support acpi if you dont want power management
frank canopy
enumeration of devices yeah
calm latch
He said he was using it for PCI interrupts routing
frank canopy
for discovering ioapics then or something? ig?
calm latch
You don't need AML for that
frank canopy
yeah i know
thats why im confused
so far im only using AML support for device discovery/enumeration
keen shard
What's his issue with mapping everything as r/w?
He has issues with making a decent kernel
It’s dogshit
Like
Holy crap
Do not even look at his PR’s
Like , I know I’m not the best at it, but damn, rdos is cancer
hollow crescent
@fiery turtle https://github.com/uACPI/uACPI/blob/master/include/uacpi/kernel_api.h#L358
when should scheduled work be executed?
"as soon as possible?"
i.e. as soon as interrupts are enabled AND the IPL is low (in my case)
fiery turtle
yes
dense steppe
"as soon as possible?"
uacpi_status
uacpi_kernel_schedule_work (uacpi_work_type type, uacpi_work_handler fn, uacpi_handle ctx)
{
(void) type;
fn (ctx);
return UACPI_STATUS_OK;
}
kind mantle
XD
dense steppe
```c
uacpi_status
uacpi_kernel_schedule_work (uacpi_work_type type, uacpi_work_h...
in any sane kernel, this doesn't work, for obvious reasons.
calm latch
define sane kernel
keen shard
define sane kernel <:trl:829316641191886888>
Something impossible is a good description
There’s no os kernel without some dogshit bits
Even Linux, its TTY is ATROCIOUS and its build system is… yeah.
sterile egret
how is that our problem that his kernel is poorly designed
WONTFIX
dense steppe
#if defined(__RDOS__)
return UACPI_STATUS_WONTFIX;
#endif
-EWONTFIX sounds like an errno
hollow crescent
```c
uacpi_status
uacpi_kernel_schedule_work (uacpi_work_type type, uacpi_work_h...
luckily i have this machinery already so easy
except that uacpi_kernel_schedule_work doesn't give me a DPC object to enqueue
which sucks
i need to dynamically allocate them or some shit
dense steppe
yeah
hollow crescent
and i do not really want to allow memory allocation in interrupt unsafe regions
dense steppe
you can do the very valid solution which is to use threaded IRQs
hollow crescent
what's that?
dense steppe
that's what I intend to do once I figure out how to do those
dense steppe
what's that?
basically you do IRQ handling in a "normal" thread
calm latch
My kernel does that
hollow crescent
so switch to a separate "fake" interrupts thread when handling interrupts
for each processor
right?
calm latch
My kernel does that
I just create a thread for each interrupt, and when I get one, the thread gets woken up and dels with it
hollow crescent
I just create a thread for each interrupt, and when I get one, the thread gets w...
oh my
for each interrupt???
calm latch
But they are normal threads
calm latch
I mean not allocated during interrupt
dense steppe
like it should just be
- interrupt handler ("top half" in Linux parlance) is entered
- the handler disables the relevant IRQ line before unblocking a kernel thread and returning from the IRQ handler
- when the kernel thread has finished handling the IRQ, it enables the IRQ line and sleeps
hollow crescent
okay, i should mention that my kernel allows you to enqueue DPCs during interrupt routines so that you have access to some more services than you normally do, in those DPCs
calm latch
with a stack and everything?
My kernel uses 1 stack per CPU
hollow crescent
My kernel uses 1 stack per CPU
What.
calm latch
Like no kernel stacks for threads
kind mantle
Threaded interrupts? That's new to me.
dense steppe
okay, i should mention that my kernel allows you to enqueue DPCs during interrup...
yeah but to do that you need free DPC blocks
hollow crescent
Like no kernel stacks for threads
How do system calls execute then
calm latch
As normal
hollow crescent
Do you just never preempt a thread if it's running a system call?
dense steppe
yeah but to do that you need free DPC blocks
\approx you need malloc
hollow crescent
yeah but to do that you need free DPC blocks
Not necessarily
calm latch
Like I don't switch stacks during task switches
frank canopy
my plan is to give each interrupt a preallocated DPC object to use
hollow crescent
Just enqueue the same DPC
kind mantle
What's a DPC?
frank canopy
and re-setup the dpc each time
hollow crescent
If it wasn't processed by the time a subsequent enqueue call is made then nothing happens
hollow crescent
What's a DPC?
Deferred procedure call
frank canopy
What's a DPC?
deferred procedure call
kind mantle
ah
hollow crescent
Basically it defers a procedure call to an interrupt safe context
dense steppe
If it wasn't processed by the time a subsequent enqueue call is made then nothin...
isn't one of the uacpi_kernel_schedule_work()'s lost in that case?
frank canopy
runs at a lower IRQL and gets enqueued for whatever
calm latch
But they are normal threads
Like actual notmal userspace threads created with pthread_create
hollow crescent
isn't one of the uacpi_kernel_schedule_work()'s lost in that case?
Oh I was talking about what my kernel already does
calm latch
Like actual notmal userspace threads created with pthread_create
With no strings attached
frank canopy
NT runs them at IRQL 2 (dispatch level), i think by scheduling a self-ipi but not sure
kind mantle
I was just gonna allocate a buncha structs ahead of time for uacpi_kernel_schedule_work
hollow crescent
NT runs them at IRQL 2 (dispatch level), i think by scheduling a self-ipi but no...
Depends on architecture I think
kind mantle
And use them with a spinlock for protection
dense steppe
like it should just be
1. interrupt handler ("top half" in Linux parlance) is en...
@calm latch is this similar to what you've done?
frank canopy
my plan is to use a self-ipi for dpc scheduling which then gets hit once i drop out of the true ISR
hollow crescent
Boron does it in software even on x86_64
It used to do a self IPI but I think it's slower
I should do a latency benchmark at some point
calm latch
<@350748255929499649> is this similar to what you've done?
Yeah
but in userspace
Since my kernel only deals with timers
frank canopy
i can only imagine self-ipi is slower but it makes it real easy to handle the irql stuff
dense steppe
It used to do a self IPI but I think it's slower
it is probably different in emulators vs bare metal
calm latch
i can only imagine self-ipi is slower but it makes it real easy to handle the ir...
there are other ways to do this?
hollow crescent
i can only imagine self-ipi is slower but it makes it real easy to handle the ir...
It's honestly not that hard the way I did it
dense steppe
there are other ways to do this?
yes
you check "are there any DPCs" before exiting the IRQ handler
calm latch
Ok, I need to stop with ?
dense steppe
if there are, run them
calm latch
it was supposed to be a statement, not a question
frank canopy
i initially had a system where the return from interrupt would drop to dispatch level and then check dpcs yeah
hollow crescent
Basically, if the preempted IPL is < IPL DPC, then lower down to IPL DPC and see if you have any DPCs running, if so, then run them, and return from the interrupt handler
dense steppe
it was supposed to be a statement, not a question
lol
hollow crescent
The hardware interrupt "becomes" the DPC interrupt, so to speak
frank canopy
yeah
calm latch
You can emulate irql and stuff afaik
Like you would ususally assume that the the kernel can be preempted
frank canopy
its not hard i just couldnt be bothered to implement a good way to handle checking preempted ipl stuff
calm latch
But you can toggle a cpu-local variable, and if you get an interrupt, you just exit immediately as if there wasn't one in the first place
frank canopy
so self-ipi is easiest
calm latch
I was thinking about making timers preempt my kernel
dense steppe
The hardware interrupt "becomes" the DPC interrupt, so to speak
yeah.
but you do have to remember to enable interrupts and also ensure that the ppr is correct if you do priorities like that
hollow crescent
its not hard i just couldnt be bothered to implement a good way to handle checki...
when entering the hardware interrupt, before updating IPL to your new level and enabling interrupts, store the old one somewhere
calm latch
I was thinking about making timers preempt my kernel
(but I have too many things that I want to do)
hollow crescent
yeah.
but you do have to remember to enable interrupts and also ensure that the ...
Yes, interrupts are enabled for every hardware interrupt routine
So that a higher priority interrupt can preempt this one of course
dense steppe
https://github.com/dbstream/davix/blob/master/arch/x86/kernel/irql.cc I'm pretty sure this is where I do the "dispatch DPCs if there are any" stuff in my kernel
hollow crescent
My kernel core (read: scheduler) is "preemptible" in the way that it can be interrupted by hardware
dense steppe
like it should just be
1. interrupt handler ("top half" in Linux parlance) is en...
I guess it is also possible to instead enqueue a DPC, removing the need for a full-blown kernel thread
kind mantle
wait but even if you do this, how are you adding the DPC to the list? Do you just have some fixed-size list somewhere?
hollow crescent
wait but even if you do this, how are you adding the DPC to the list? Do you jus...
Linked list
kind mantle
Linked list
Where do you get the memory for the links
hollow crescent
There is a list of enqueued DPCs for each CPU
kind mantle
You're in an interrupt
hollow crescent
Where do you get the memory for the links
The DPC struct
It's an intrusive linked list
kind mantle
The DPC struct
So you mean yes, you do have a fixed size list, or a static allocation anyway.
dense steppe
https://github.com/dbstream/davix/blob/master/arch/x86/kernel/irql.cc I'm pretty...
this is kinda a "fake" IRQL system
hollow crescent
So you mean *yes*, you *do* have a fixed size list, or a static allocation anywa...
It's not a fixed size list
It's a linked list
dense steppe
this is kinda a "fake" IRQL system
it's more similar to preempt_{disable,enable} really
hollow crescent
https://github.com/iProgramMC/Boron/blob/master/boron/include/ke/dpc.h#L27 here is the thing that's added to the linked list representing the DPC queue
kind mantle
It's not a fixed size list
I mean static (or relatively static anyway) allocated
hollow crescent
Yes, DPCs are statically allocated (usually)
Actually a device driver can do whatever the hell it wants
kind mantle
But it's not fixed size
its 23:37 i can misspeak ok?
hollow crescent
As long as the memory the DPC is in is nonpaged it's fair game
hollow crescent
its 23:37 i can misspeak ok?
00:37 here
kind mantle
lmao
hollow crescent
It's fine
dense steppe
https://github.com/dbstream/davix/blob/master/arch/x86/kernel/irql.cc I'm pretty...
oh yea and I also do soft/lazy interrupt disabling, which is fun
kind mantle
we are good at sleeping
dense steppe
I guess it is also possible to instead enqueue a DPC, removing the need for a fu...
thinking about it, one advantage of fully threaded IRQs is that you can now grab any lock whatsoever, e.g. a mutex, from the IRQ handler without fear of deadlocking against someone you've preempted
hollow crescent
@dense steppe https://github.com/dbstream/davix/blob/master/kernel/dpc.cc#L51 why dont you typedef the function pointer
dense steppe
to raise the barrier of entry into understanding my kernel 
no but I probably should do that, actually.
definitely do look at arch/x86/kernel/irq.cc and arch/x86/include/asm/irql.h too
dense steppe
it's more similar to preempt_{disable,enable} really
honestly I should abandon the IRQL parlance and just do dpc_{disable,enable} and irq_{disable,enable}
because this right now is just unnecessary and annoying
dense steppe
thinking about it, one advantage of fully threaded IRQs is that you can now grab...
thinking about it even more, from the type of work uACPI can enqueue, it probably needs to run at thread level.
calm latch
Linux just creates a new thread for it every time?
(my OS does as well since it was the easiest thing to do)
(for enqueue work callback)
lilac knoll
dont open xnu source
slim panther
flat badge
Forth is would be less horrible than AML, yes
dense steppe
Linux just creates a new thread for it every time?
no, Linux has very nice workqueues for this sort of thing
dense steppe
thinking about it _even more_, from the type of work uACPI can enqueue, it proba...
and I should not do kernel design at 23:48 because the time probably contributed to me getting the interrupt handler and work scheduling mixed up.
fiery turtle
my new motheboard prints ACPI-related codes at runtime, pretty cool
damn, debugging S3 should be nice
calm latch
Does it let you write to 0x80 like my motherboard?
vast kestrel
It's probably 0x80 display yeah
fiery turtle
That's pretty cool for debugging gpu drivers lmao
calm latch
Serial port is more convenient though
fiery turtle
ofc, but its not a thing on my mobo
frank canopy
neat
slim panther
my new motheboard prints ACPI-related codes at runtime, pretty cool
nice
@fiery turtle do you think multi-cpu systems would be interesting to you?
i might be building a dual epyc testbench
fiery turtle
u mean uacpi-wise? yeah any special hw is interesting
left orbit
acpi dump appreciated :^)
fiery turtle
and test some OSes from here
slim panther
I'm building it mostly because numa is going to be interesting
and I've never owned a pc with more than one cpu xd
left orbit
you can just emulate numa in qemu
left orbit
free in fact
slim panther
ebay really wants me to buy them
friday is paycheck day
wait aren't intel x99 xeons also dirt cheap
calm latch
i might be building a dual epyc testbench
Which Epyc?
calm latch
Because I think there were Epycs which give you 786 threads in one system?
calm latch
not bad
fiery turtle
Btw uACPI has surpassed Astral in github stars
slim panther
rustic compass
I have a Dell r730xd server lying around
fiery turtle
probably because of osdev forums?
nah it hasnt sped up really
its because of astral death lol
calm latch
Still 208 stars and almost 250k forum views is like ... a lot
fiery turtle
yeah im honestly confused why its that high
for example the FYSOS post from 2016 has less views
and somehow that didnt generate much traffic for the repo
yeah idk
fiery turtle
dunno
hollow elm
vogons huh
fiery turtle
no idea what that is
slim panther
pci device tree???
fiery turtle
the future of linux
slim panther
every time this guy makes a new comment i'm more and more baffled by the ignorance
like i know i say some pretty stupid stuff sometimes
but never ever on this level
does he mean the fucking pci bridge hierarchy???
fiery turtle
it's astonishing that he has like 20 years of experience in osdev and somehow says stuff like that
slim panther
how can you market yourself as a serious os and not know about any of this
like
what devices does he even target???
storage via i2c or what
kindred beacon
fiery turtle
lol
dusky glade
real
dire owl
every time this guy makes a new comment i'm more and more baffled by the ignoran...
keep in mind this person has more commerical users than all of us combined
kindred beacon
dire owl
yes, RDOS is used commercially iirc
slim panther
omfg
kindred beacon
(according to Mr. Dunning-Kruger)
slim panther
lol
dire owl
as a RTOS or something
slim panther
menix is actually used commerically on over 50 computers
(suse machines that i hijacked)
median crest
fiery turtle
lol
slim panther
cooked
gentle peak
is there a list of kernel api functions that uacpi can call from interrupt handlers?
gentle peak
alright that works thanks
fiery turtle
he gets more confused by the minute
vast kestrel
Just wait until he discovers the job of MCFG
gentle peak
is there some kind of centralized database or something where i can look up pnp ids for devices?
hollow elm
rg PNP... /usr/src/linux :^)
hollow elm
on most distros that path probably doesn't exist or only contains headers for building modules
fiery ice
on widnows you can dump the aml
hollow elm
just use a path to your local copy of the linux kernel sources
fiery ice
but you can only see the ones you have
gentle peak
`rg PNP... /usr/src/linux` :^)
fair enough
calm latch
he gets more confused by the minute
Tbh PCI is not that straightforward
Though how did he have ACPICA working before?
frank canopy
is there some kind of centralized database or something where i can look up pnp ...
https://uefi.org/PNP_ACPI_Registry exists but its just a registry of vendors not of devices
frank canopy
no idea
hollow elm
https://uefi.org/PNP_ACPI_Registry exists but its just a registry of vendors not...
i imagine that's because vendors can assign whatever ids they want, afaik pcisig also doesn't list any device ids for vendors
frank canopy
https://uefi.org/sites/default/files/resources/devids (5).txt is how i reference the standard/compat ids
frank canopy
i imagine that's because vendors can assign whatever ids they want, afaik pcisig...
yup
i actually helped a guy figure out the device id for a thing for support the other week because a flight sim hardware company had just released a new thing that i got but he didnt lol
the actual device id is whatever the vendor wants
if you want the well known ones look at linux source
calm latch
Don't they have a weird south-bridge like thing?
hollow elm
they do yeah, but they don't officially ship acpi/uefi firmware
calm latch
I mean ARM SBCs seem to be getting semi-competent ACPI
With Windows and stuff
What if the next Raspbery Pi...
fiery turtle
@calm latch thanks for replying to him
fiery turtle
who is this
A watcom user
dusky glade
A watcom user
lmaoooo
can we make it possible to ban people from repos
specifically this person
rustic compass
wouldnt loading the namespace, then enumerate it for pci(e) stuff and then initializing the namespace solve his problem?
calm latch
It's what my kernel does
But the question was weird
Why would you need names?
And uACPI should give them to you anyway
fiery turtle
I have no idea what he meant by names
slim panther
wtf is he on about now
frank canopy
i get the sense that he doesnt understand that pci config space access doesnt require enumerating devices first
frank canopy
can we just port rdos to gcc
idk does he use segmented memory model for 32-bit x86? if so then youd have to change the entire memory model lmao
slim panther
force him to use paging
frank canopy
he believes its faster that way
slim panther
(it's not)
calm latch
tbh I think that page was written 30 years ago, and never updated
though still
one would remove it...
yeah that's a bad argument
frank canopy
there might have been an argument for asm being faster 30 yearrs ago but even then doubtable
calm latch
I mean if you were using watcom
frank canopy
yeah its definitely possible with watcom, open or otherwise
rustic compass
compile times are definetly faster for assembly
surreal current
he gets more confused by the minute
Just point him to a kernel project that already successfully uses it and be done with it
Say "do it like this"
calm latch
I think I've left a link to mine in one of the messages 
fiery turtle
Just point him to a kernel project that already successfully uses it and be done...
I've tried talking and explaining stuff at the very beginning but it doesn't seem to go through nor register in any way
slim panther
then close it as off topic
calm latch
"ask on discord"
fiery turtle
"ask on discord"
Unironically this
slim panther
fiery turtle
I will probably just answer with this
sterile egret
rustic compass
i want popcorn for when he reads the old messages in ths channel
slim panther
mortal yoke
then just wait until he gets mad and ban them
fierce kiln
oh this is the uacpi yap station
#osdev-misc-0 message
oops posted it in the wrong place
kindred beacon
oh god I didn't see that the rdos saga continued
sterile egret
oh no
sterile egret
oh god I didn't see that the rdos saga continued
on github? I'm afraid to look
kindred beacon
yeah
sterile egret
Also github isn't loading commits properly rn for me lol
kindred beacon
works for me
fiery turtle
someone should tell him to read a spec of how _PRT works
actually no it's fine, good thing he stole mishakov's code
fiery turtle
hollow scaffold
That sucks
calm latch
actually no it's fine, good thing he stole mishakov's code
The issue is that my code is not the best in the first place
fiery turtle
looks fine to me
calm latch
The error handling is not great
slim panther
or result propagation
fiery turtle
not biased opinion btw
kindred beacon
clearly superior because managarm is superior 
fiery turtle
real
left orbit
when ultra kernel progress thread
left orbit
come on i need inspiration
idk what im doing
i should honestly just drop the idea of making a cool kernel and go back to shitty non-preemptive kernel and get bash running or smth
fiery turtle
im waiting for qwinci intel driver to get inspired
fiery turtle
i should honestly just drop the idea of making a cool kernel and go back to shit...
thats the way
surreal current
come on i need inspiration
there are other inspiring hobby kernels
like min
oca
whatd u think i was gonna say
fiery turtle
mintemple os
fiery turtle
kinda hate my brain
slim panther
i should honestly just drop the idea of making a cool kernel and go back to shit...
real
chad realist mindset
left orbit
no it's the beta *ux developer mindset
dusky glade
brian?
left orbit
i want to make something good
slim panther
me too but my brian is null
dusky glade
i should honestly just drop the idea of making a cool kernel and go back to shit...
nahh
calm latch
i should honestly just drop the idea of making a cool kernel and go back to shit...
my kernel is nonpreemptive and I like to think that it's cool 
calm latch
(like the sceduling is preemptive, but the kernel can't preempt itself)
fiery turtle
linux couldnt until recently as well
surreal current
linux couldnt until recently as well
Sounds wrong
You almost get kernel preemption for free when you add smp support
Cuz both require you to support multiple executing contexts inside the kernel simultaneously
calm latch
how so?
surreal current
Unless you do a big kernel lock that is