so simple fixes overall but finding the bugs is time consuming and involved
#Managarm and related projects
carmine current
trim eagle
and there was a small problem with registering some qml plugin which we had to do some patching for
(Where small is the entire thing crashed)
alpine yacht
plasmashell?
how do you guys usually find bug when it comes to such a huge projects
although being able to compile from source probably makes it a lot easier
alpine yacht
true
trim eagle
Outside of that
A fuckload of determination, and if something is “impossible” then usually it isn’t
native prairie
Letsgo
molten meteor
year of managarm desktop
trim eagle
rich glade
i can only imagine
trim eagle
Full KDE powered IRC moment
trim eagle
That’s what Qemu reports I’d think. I’ll cross reference it with Linux-mlibc some day
limber grail
Any work on some web server? Either python http server or Apache or nginx
Maybe I’ll try to port Apache again
But the docs are so bad
rare prism
120hz doesn't seem so crazy
it's a vm man
serene portal
?
serene portal
idk if the connector is reporting that as a mode it must be true
trim eagle
Any work on some web server? Either python http server or Apache or nginx
Yeah we have it on the todo list as part of our NLNet grant
dense umbra
no longer a hobby os smh
trim eagle
wait, managarm is financed?
We just got accepted into a NLNet grant
trim eagle
no longer a hobby os smh
If only they paid enough to employ one of us full time (not even close, it isn’t employment even)
It’s all voluntary work and that work can result in donations
carmine current
Any work on some web server? Either python http server or Apache or nginx
Python's htpt.server module just works
But ofc it's not a replacement for a proper web server
limber grail
Python's htpt.server module just works
iirc when i ran it it didnt wanna connect
vestal sapphire
native prairie
Lfg
carmine current
2026 year of Managarm security
molten meteor
if managarm does not have a hypervisor prekernel and runs in it dont talk to me about security 
upbeat smelt
maybe one day for virt on aarch64 without vhe
fervent zodiac
if managarm does not have a hypervisor prekernel and runs in it dont talk to me ...
true!
fervent zodiac
well yeah i mean i cant be the first to an iommu
but i can be the first to an iommu on aarch64 on real hardware on m1
native prairie
tbh you're like the only person on here who cares about apple stuff
fervent zodiac
exactly
fervent zodiac
yeah thats why you choose an extremely weird technicality
not that i will ever be first anyway since i got slightly bored of doing osdev for now and i might try doing a little langdev instead
native prairie
langdev sounds fun also
its definitely nicer because u can test the shit out of it with ease
quaint fern
the great thing with compilers used to be that you just had to make it do its one-off job but now that people expect language servers you've got to do more
fervent zodiac
you can always go the rust route
make a compiler that does a one-off job, then make a half assed language server, then wait for the community to write a slightly better one
(where the language server just reimplements half of the language)
magic marsh
tbh you're like the only person on here who cares about apple stuff <:meme:57544...
me who somewhat cares about Apple PowerMacs: 
native prairie
make a compiler that does a one-off job, then make a half assed language server,...
isnt it kinda better when theres one single source of truth
forest bear
not that i will ever be first anyway since i got slightly bored of doing osdev f...
join zag
the greatest project
fervent zodiac
whats zag
serene portal
tbh you're like the only person on here who cares about apple stuff <:meme:57544...
lmaooo
carmine current
fwiw Managarm boots on M1 up to the point where it needs a disk
although the patches to make that happen are not all upstream yet
serene portal
although the patches to make that happen are not all upstream yet
@nocturne tide
carmine current
actually part of the NLnet funded work is to get dwc3 working in host mode
so atp (+ apple specific fixes) it should be possible to boot from usb on M1
native prairie
actually part of the NLnet funded work is to get dwc3 working in host mode
how different is that from xhci
upbeat smelt
how different is that from xhci
extra gunk glued on to support device mode
for host mode afaicu you need to do some config and then you can hand it off to the xhci driver
native prairie
ah
nocturne tide
i remember now that nvme irqs were broken (?)
all of the irqs were broken 
i had no device irqs at all
and thats bad considering on m1 mailbox irqs are hardwired and you can't disable them lol
aic was probably misconfigured
i need to get back to work on thaaaat bruh
native prairie
hows the nt port going @nocturne tide
trim eagle
Rip
native prairie
no one working on it atm
Whats left atm?
nocturne tide
uh, well, all the drivers i guess
the aic hal extension
drivers doubled for uefi and nt btw
native prairie
Cant the clanker roll those? Or is it no ai strictly
nocturne tide
we follow the asahi linux ai policy
native prairie
Ah
nocturne tide
which is strict no ai, and idk if i want to try and change their mind
native prairie
Fair
nocturne tide
but from my experience, even if i point the clanker at linux it couldn't generate a good driver lol
i did that for fun
carmine current
Yeah AI is not really good at drivers
nocturne tide
i used claude to get a better grip on how to write windows drivers but it was not very good at writing them
carmine current
that's not surprising at all
Drivers are a tiny fraction of the training set
And in contrast to self contained code, iterating on a driver is really hard
To make it work, you'd need to give claude access to a physical machine where it can test
nocturne tide
well, i'm running it under a hypervisor :^)
so i could give it access to that + windbg
forest bear
no one working on it atm
Wait what are you working on
nocturne tide
porting nt to apple silicon
nocturne tide
it boots, no drivers though
nocturne tide
forest bear
Wait so it's not your project
nocturne tide
it consists of three parts, m1n1_windows which is a m1n1 fork that adds a vgic - needed because apple platforms don't have a gic and windows needs that (for now) to boot
nah lol
of course not
forest bear
Ah I thought it was
nocturne tide
i joined it at a later point, basically when all the fun stuff was done :(
but it's still a cool project and you should contribute :)
nocturne tide
it consists of three parts, m1n1_windows which is a m1n1 fork that adds a vgic -...
m1n1_windows, apple_silicon_platforms_mu which is a project mu port to apple silicon - that's basically edk2 with some goodies on top iirc, and apple_silicon_nt_drivers which will be the drivers themselves
current hardware support is basically m1, m2 boots but no usb because of the irq number allocations on m2
but hopefully once windows gets an aic driver that should no longer be an issue
vestal sapphire
you need to install y4
celest cave
I always get this when booting
trim eagle
yeah
native prairie
Force smbios to 64 bit
carmine current
we don't use it for paravirt
we don't have paravirt support beyond e9
the nvidia driver uses it
and we can run dmidecode
native prairie
linux uses it also to detect populated/empty ram slots
- obviously device/firmware quirks
fervent zodiac
we don't have paravirt support beyond e9
dmalog?
carmine current
ah true
fervent zodiac
what is that
its like e9 but big fast because thats how many logs managarm has
and no ivshmem
native prairie
yeah but is that like virtio-console or something
fervent zodiac
i think its way simpler
native prairie
wait is that like a device managarm invented?
fervent zodiac
yes
native prairie
ah
blissful bluff
Btw, isn't this kinda broken?
https://github.com/managarm/managarm/blob/master/kernel/thor/system/acpi/acpi.cpp#L119
brittle mauve
Btw, isn't this kinda broken?
https://github.com/managarm/managarm/blob/master/k...
because of the fact that irqs is an u8 vector?
blissful bluff
It doesn't seem to distinguish between GSIs and ISA interrupts
true kernel
it has generic infrastructure to handle that iirc
carmine current
@flat hearth @slow reef for the profiling ring change, is that required because we're hitting this case in that qemu configuration: https://github.com/managarm/managarm/blob/master/kernel/thor/generic/profile.cpp#L42 ?
flat hearth
<@618537432002068491> <@1482737888390021284> for the profiling ring change, is t...
yes! that does end up getting hit when i remove thoes checks
And then it later crashes
carmine current
ah i see
that can probably be reproduced on tcg qemu w/o fred, let me check
yeah it can
flat hearth
lol
I guess that fix works then? Or is there something else that should be done
Or do I just drop it from the patch altogether
slow reef
iirc globalProfileRing.initialize is never called but wantKernelProfile will stay true?
thought I am very tired and probably misremembering 😭
carmine current
yeah
the code assumes that wantKernelProfile == profiling works but that's not true
slow reef
yeah
carmine current
Or do I just drop it from the patch altogether
yeah i think the patch is fine
you can put it into a separate commit
basically it's a fix for situations in which profiling is requested by not available
slow reef
you can put it into a separate commit
yeah it probably should be a separate commit
flat hearth
alright the isolated crash fix patch is there and the existing FRED stuff is in a commit
@carmine current should i go do a final test and make a PR?
carmine current
yeah
ig you could log at simics serial logs to see what goes wrong there but it might be unrelated to fred
or it might be just a config issue
flat hearth
ig you could log at simics serial logs to see what goes wrong there but it might...
it happened with none of my patches applied
carmine current
yeah i think it's probably a config issue
flat hearth
it works!
worst case i can just debug it more later if it fucks up on SIMICS for real
i do not wana mess with SIMICS config shit because its so annoying
slow reef
(or being real you pawn it off to me to debug :P)
flat hearth
😭
carmine current
is it that annoying to just get the serial log?
slow reef
I straight up didn't bother with serial for simics but it's probably not terribly hard
carmine current
fwiw to make Managarm write to serial you need to pass serial on the kernel command line
flat hearth
is it that annoying to just get the serial log?
oh i meant for the actual issue if it was a hardware problem
and editing what hardware it emulated
blissful bluff
I straight up didn't bother with serial for simics but it's probably not terribl...
I couldn't get the framebuffer on it, but the serial worked for me, so it's definitely possible
(with my OS)
slow reef
I couldn't get the framebuffer on it, but the serial worked for me, so it's defi...
huh I had the complete opposite problem
I could not get serial to work for the life of me but the framebuffer worked fine
flat hearth
I could not get serial to work for the life of me but the framebuffer worked fin...
both of them work fine for me
skill issue ig
cc: @carmine current
https://github.com/managarm/managarm/pull/1366
graceful flax
It’s too peak
flat hearth
Lmk if anything needs changing to be merged
graceful flax
I- I can’t handle it
carmine current
nice ty
flat hearth
all hail fred
All hail FRED
carmine current
I'll review + test it later
flat hearth
🤞
slow reef
I'll review + test it later
welp if it breaks hopefully it isn't my fault 😭
slow reef
fuck 😭
carmine current
this can be done by running xbstrap run --pkg managarm-kernel clang-format
flat hearth
slow reef
welp that would of been nice to know 26 minutes ago :P
carmine current
welp that would of been nice to know 26 minutes ago :P
well, the non-lint jobs succeeded, so that's good
slow reef
I stg if the linter yells at me again
See if you had used a good editor this wouldn’t of happened
flat hearth
See if you had used a good editor this wouldn’t of happened
KATE is an editor granted to me by the gods
slow reef
KATE is an editor granted to me by the gods
Is this what you tell yourself to sleep better :p
carmine current
lol
flat hearth
lol
Any idea what tf went wrong with it?
Or if it wasn’t a me issue
Because I see other PRs with similar failures
carmine current
Might be a spurious failure, I'll restart later
flat hearth
it does work on my machine
running with the IDT
huh wtf?
i never touched that file
and the VM should be running without FRED?
slow reef
seems like getCpuData()->activeExecutor->currentUar() for handleUserAccessFault just decided to be misaligned
why :P
flat hearth
i dont think this has to do with my code?
carmine current
Is the ubsan issue reproducible?
slow reef
im fighting trying to get my lsp to work right now so I can look into it 😭
flat hearth
Is the ubsan issue reproducible?
Is there a way I can test this localy
What’s the command to test it
carmine current
I thought this was locally
carmine current
Ah
native prairie
cc: <@358943271151468555>
https://github.com/managarm/managarm/pull/1366
Nice
native prairie
Details
flat hearth
just ship it :3
Honestly probably is fine
slow reef
Honestly probably *is* fine
I would prefer to know why ubsan trips
flat hearth
I mean ofc
slow reef
Sadly I can no longer be helpful as I am far to eepy for this 😭
carmine current
wait where do you see the ubsan failure on gha?
ah nvm found it
that's not fatal for the CI
what's fatal is that a posix test hangs
but that's probably unrelated to the PR
carmine current
what's fatal is that a posix test hangs
CC @vestal sapphire
carmine current
btw why is this a posix test and not an mlibc test?
blissful bluff
im ~~fighting~~ trying to get my lsp to work right now so I can look into it 😭
Lsp is for the weak
flat hearth
Lsp is for the weak
I made the entire PR with my LSP fucked lmao
vestal sapphire
carmine current
evalyn did you even sleep? lol
blissful bluff
I made the entire PR with my LSP fucked lmao
My lsp doesn't work with Jinx
lament grove
I thought we had established by now that nobody sleeps 
flat hearth
evalyn did you even sleep? lol
I just slept 2 hours and just woke up
And then I had like 4 hours after I took a break on the patch
😭
Wokeup at 12am and decided welp might aswell work on it some more
carmine current
Let's let Claude do an audit of the rwlock impl
to see if the hang can be caused by the rwlock itself
(this is ofc unrelated to FRED)
and maybe also of the futex implementation since you never know
blissful bluff
You do futex with wait primitives?
carmine current
wdym
golden maple
what's fatal is that a posix test hangs
is this managarm or mlibc issue
carmine current
is this managarm or mlibc issue
unclear
carmine current
yes, futexes are not a primitive at the kernel level
they are exposed as syscalls but implemented on top of more fundamental primitives
blissful bluff
But you could emulate then in userspace I'd assume?
carmine current
no because the kernel internal primitives are not exposed to userspace
blissful bluff
Because I'm thinking about only having the park/unpark API available to userspace
carmine current
Let's let Claude do an audit of the rwlock impl <:meme:575445094589661215>
it did find a bug
https://github.com/managarm/mlibc/blob/master/options/posix/generic/pthread.cpp#L1259-L1262 these two error returns do not unlock the internal mutex via rwlock_m_unlock
it's probably best to use frg::scope_exit here and to .release() it on the success path
vestal sapphire
solution: buy a DGX spark and turn it into a LLM reviewer bot for PRs
(half-meming)
spring oak
solution: buy a DGX spark and turn it into a LLM reviewer bot for PRs
nah, the framework with the amd apu is cheaper
and better
dgx spark is slow AF
carmine current
flat hearth
It could be useful but it definitely would fuck with alot of perfectly normal PRs
carmine current
yeah there is still a lot of noise in the output
flat hearth
yeah but ive seen stories of people doing it at work and having to gaslight the ai to take the PR 😭
carmine current
wth
flat hearth
Or at the very least being way too heavily AI driven
Some people are fucking crazy with it
dense umbra
solution: buy a DGX spark and turn it into a LLM reviewer bot for PRs
Go to anthropic hq to ask for mythos github bot access
carmine current
okay, claude did find no issues in the futex impl
helFutexWait and the FutexRealm/GlobalFutexSpace primitives are correct. The only real cleanup is the unreachable return kHelErrNone;.
which obviously doesn't mean that there can't be error but at least it's a good sign lol
slow reef
evalyn did you even sleep? lol
I’ve asked her this so many times and I feel like 9/10 she’s said “no” or “not enough”
flat hearth
@carmine current ive got the serial log
carmine current
does it only hang with profiling enabled?
does it hang in a different way if profiling is off?
flat hearth
it does the same thing with it off
dying on clock tracker
though it gets a little further without it on
with the nack
randomly gets a little futher somtimes
carmine current
Hm
flat hearth
You wana grab SIMICS yourself and test it?
carmine current
is it possible to inspect what the CPUs are doing?
flat hearth
It did this without any of my patches so I’ve got no clue
flat hearth
is it possible to inspect what the CPUs are doing?
No idea 💀
carmine current
how easy is it to build and set up?
flat hearth
they have a ton of stuff here
quaint fern
Let's let Claude do an audit of the rwlock impl <:meme:575445094589661215>
i asked claude to review my new turnstiles and he proceeded to use my entire session allowance thinking about them
hopefully it will go better for you
flat hearth
yeah its in some infinite loop??
carmine current
yeah its in some infinite loop??
can you run this addr through
xbstrap runtool host-llvm-toolchain -- llvm-addr2line -e pkg-builds/managarm-kernel/kernel/thor/thor 0x1234
with 0x1234 replaced by the addr obviously
uhm, llvm-addr2line instead of addr2line actually
flat hearth
its somthing with the RTC?
well
that would explain it
Something with the CMOS in SIMICS is fucked
carmine current
ig it never sets update in progress
flat hearth
Is there a way to disable it grabbing the CMOS or a way this could be patched?
carmine current
ig you can return 12345678 from the function
flat hearth
carmine current
obviously the time will be wrong
flat hearth
that makes things die in qemu amd SIMICS but it dies later
none of the FRED patched added either
i tried making it change over time but it did the same effect
ah it is with my patches my IDE just borked for a sec 
but im not having it with FRED on so
and QEMU works fine withut the RTC "fix"
carmine current
okay but it gets far enough in simics to see if FRED worked
flat hearth
carmine current
you could test now in simics with FRED + profiling
flat hearth
this is with no profiling w/ FRED (should be)
and prodiling works too
So 🤞 should be good enough to merge
flat hearth
this one right?
carmine current
yeah
carmine current
lol
flat hearth
I mean it’s technically more spec complaint I guess
Along with the flags
Let me test SIMICS
carmine current
did you re-run `make-image? :^)
flat hearth
Anything else I need to do?
carmine current
no, at least not for now. I'll review the PR in detail in a few h
i think it should be mostly good but maybe require some minor fixes
flat hearth
Probably
If I have to do some minor cleanup/fixes the commit name should be like thor: minor FRED cleanup and fixes
vestal sapphire
git commit --amend --no-edit
or even better for reviewing, fixup commits
damn I really should write my git workflow tips thingy
flat hearth
But idk if I should do that if it’s already pushed
Thoughhhhh
git push —force and I cleanup my local tree
Then I only need the original 3 commits with all the fixes
vestal sapphire
force-pushing to PRs is fine
even desired even, how else do you want to incorporate reviews
flat hearth
Yeah il force push at the very end of this and get it clean
native prairie
If I have to do some minor cleanup/fixes the commit name should be like thor: mi...
you just git commit -m "fixup! <commit name or hash that this fix belongs to>
and then git rebase -i HEAD~N --autosquash
Where N is approximately the number of commits ago
and this fix will automatically be fixed up into the commit that u targeted
then just git push -f
flat hearth
Oooo
Then I can target it to the main Fred commit
And then also get the formatting one out
Thank you
I lowkey was just gonna undo all the commits and redo them all manually 💀
native prairie
yeah in the interactive rebase menu u can move commits around, drop them, reword them, or even fix them up if u prefix them with f
so they will be merged into their parent commit
vestal sapphire
you just `git commit -m "fixup! <commit name or hash that this fix belongs to>`
NO JESSE NO
git commit --fixup=sha
or even better, have a git alias for fuzzy-searching
native prairie
`git commit --fixup=sha`
does that like auto append that?
vestal sapphire
[alias]
fixup = "!git log -n 50 --pretty=format:'%h %s' --no-merges | fzf | cut -c -7 | xargs -o git commit --fixup"
put that in your ~/.gitconfig and then you can just use git fixup, which opens up a fuzzy search of the past 50 commits where you can select the one you want to fixup
native prairie
put that in your `~/.gitconfig` and then you can just use `git fixup`, which ope...
thats nice
i might steal that
vestal sapphire
and if you git rebase --autosquash later, it will automatically mark that fixup commit as fixup (squash without edit)
carmine current
does that like auto append that?
git commit --fixup <sha> auto generates the fixup! ... commit msg
native prairie
yeah leo told me
flat hearth
so i should be able to make the fixup commit and squash them all into the one FRED support commit?
also ping me when i need to clean some things up as im off to bed
native prairie
here u can just git reset HEAD^ && git add . && git commit --amend --no-edit
because its only one commit behind
vestal sapphire
even better, git reset --soft @~ && git commit --amend --no-edit does the same
native prairie
what the hell is --soft @~ ☠️
carmine current
--soft is a no-op
vestal sapphire
--soft makes the reset changes staged, and the @~ is just a shorthand for HEAD^
native prairie
ah yeah thats better
vestal sapphire
the difference between --soft and not using it is that without it, the reset changes are not staged
native prairie
ye makes sense
vestal sapphire
you can also use @~3 as a shorthand for the third-to-last commit
native prairie
yeah it works with HEAD~3 also
native prairie
same
flat hearth
here u can just `git reset HEAD^ && git add . && git commit --amend --no-edit`
this seems to work; after i had to reset back to the head of the branch because i had unstaged broken changes i fotgot to nuke 💀
looks proper now
native prairie
yeah leo's stuff would've been better for that
carmine current
the difference between `--soft` and not using it is that without it, the reset c...
ah, i see
vestal sapphire
even better, `git reset --soft @~ && git commit --amend --no-edit` does the same
this wouldn't have had that problem unless you had staged changes already
native prairie
u can just reset the commit and unstage them
flat hearth
I will just use that command again when I need to apply the fixes if needed by korana
native prairie
git restore --staged fred.c
flat hearth
git reflog though is very nice
native prairie
also in such cases git add -p is convenient
so u can add hunks instead of everything
carmine current
if you want do undo changes you can also git checkout -p <the right version>
native prairie
I don't even know what fixup does
Adds changes to an existing commit
vestal sapphire
no
vestal sapphire
it makes a new commit, but if you rebase with --autosquash it is squashed into the correct one
I am shit at explaining stuff
native prairie
Can't you just rebase or something
When u rebase and mark it as f aka fixup yes
Thats what that does
carmine current
well you don't need fixups
fixups are just a convenience feature
you can also do it manually
vestal sapphire
first managarm boot with both XHCI and NVMe using IOMMU DMA remapping 🥳
flat hearth
So thanks again to <@618537432002068491> and <@1482737888390021284>
No problem ^^
If there is anything smaller you need me to work on ping me and il try and cook some stuff up
flat hearth
wanna do an ATA driver <:meme:575445094589661215>
i mean, i probally was gonna do one for my kernel. if i finish that i could work om porting it?
after my x11 stuff i was gonna do nvme/ata things
vestal sapphire
thing is you will have to deal with the managarm interfaces, including the new DMA spaces
flat hearth
will be easier than writing it from scratch atleast, and i am not in the mood to read the ATA spec rn
carmine current
first boot on the k3
okay, so let's see, it's looking quite good actually:
- eir-linux just works
- thor seems to mostly work but it panics here:
thor: Synchronous exception with interrupts disabled at IP 0xffffffff80001bc2 - AP boot works
- the board has an IMSIC which is the most modern interrupt controller on RV and it also works (?)
- posix dies, probably while setting up sysfs for device tree nodes (?)
native prairie
eir: No RSDP available, skipping ACPI table setup
carmine current
that is expected, the board doesn't have acpi
carmine current
okay, the synchronous fault on the APs is negative TLB caching
which Managarm doesn't take into account rn
that should be an easy fix though, just check if the page is accessible and retry
carmine current
okay, that is fixed (who thought allowing negative speculative tlb caches is a good idea though? )
blissful bluff
okay, the synchronous fault on the APs is negative TLB caching
So RISC-V has it as well?
blissful bluff
okay, that is fixed (who thought allowing negative speculative tlb caches is a g...
It makes sense with software page walks
carmine current
risc-v has this unless the Svvptc extension is present
mild jetty
okay, that is fixed (who thought allowing negative speculative tlb caches is a g...
my guess is that they wanted implementors to be able to do software pt walking in M mode
which is harder if you don't allow negative tlb entries
carmine current
why do negative tlbs help with software walks? i never really looked at software walks in detail
blissful bluff
why do negative tlbs help with software walks? i never really looked at software...
I don't know if it's the primary reason, but it allows it to split the exception into the refill and then page fault more easily?
Where the refill would probably drop to M mode, while the pagefault happens in S mode
(I mean loongarch disables paging for the refill exception (and machine check thing), while the page fault doesn't)
carmine current
Ah makes sense
Trapping to m mode would also disable paging since M mode runs identity mapped
blissful bluff
yeah, ik
mild jetty
why do negative tlbs help with software walks? i never really looked at software...
No tlb entry -> tlb miss exception
Negative tlb entry -> page fault exception
If you want software walking without negative tlb entries you have to either unify tlb misses and page faults (slows down the fast path) or have something like a specialized fill-tlb-and-return-from-miss instruction that checks whether the entry to be filled is negative and if so causes a page fault
Whereas if you have negative tlb entries you can just use the normal fault infrastructure without slowing down the fast path at all
carmine current
yeah that makes sense
blissful bluff
But also can't it make some things faster perhaps?
native prairie
my guess is that they wanted implementors to be able to do software pt walking i...
risc-v has software tlb stuff?
blissful bluff
risc-v has software tlb stuff?
It doesn't not have it
hidden sonnet
yo
blissful bluff
Like the spec defines page tables format for the S mode, but afaik you can just do whatever you want in firmware
native prairie
Like the spec defines page tables format for the S mode, but afaik you can just ...
wdym
blissful bluff
wdym
You have paging as a kernel, but it's doesn't mandate the hardware page walking
If I read it correctly
native prairie
so it could be refilled by firmware in the background or smth?
native prairie
oh ok
carmine current
in reality all application profile chips have hw tlb walk though
lament grove
so it could be refilled by firmware in the background or smth?
The spec basically blanket-allows a higher privilege mode to emulate missing features.
blissful bluff
in reality all application profile chips have hw tlb walk though
But why would they have negative TLB entries then?
lament grove
But why would they have negative TLB entries then?
because RISC-V likes being permissive to what the HW is
blissful bluff
because RISC-V likes being permissive to what the HW is
No, I mean on that board specifically
carmine current
But why would they have negative TLB entries then?
you mean specifically on the k3? ig because the spec doesn't forbid it
lament grove
And TBH it really isn't that bad to just sfence.vma if you notice you should have succeeded an access.
lament grove
you mean specifically on the k3? ig because the spec doesn't forbid it
Keep in mind that caching negative entries is easier to do, even for HW!
blissful bluff
Like as korona asked, what's the point if you have hw page walker
carmine current
And TBH it *really* isn't that bad to just `sfence.vma` if you notice you *shoul...
yeah it's not that bad, i just didn't expect it
blissful bluff
Also, how do they get cached in the first place?
I wonder it could make TLB lookups faster
carmine current
we were already handling spurious faults for user mode pages but we didn't expect them for kernel heap
lament grove
Also, how do they get cached in the first place?
- Access happens
- TLB misses
- PT walker resolves the PTE
- Result stored in TLB and access continues (successful or not)
blissful bluff
we were already handling spurious faults for user mode pages but we didn't expec...
I was burned by that when porting my kernel to loongarch64
blissful bluff
1. Access happens
2. TLB misses
3. PT walker resolves the PTE
4. Result stored i...
No, but I mean that those would have to be speculative accesses then
lament grove
No, but I mean that those would have to be speculative accesses then
Yes and CPUs do that all the time
Especially if you're going in a linear pattern
lament grove
Does remind me actually, I should be doing a sfence.vma every time I map a kernel stack, which I currently don't
Everything else should be fine since my heap is just HHDM :P
blissful bluff
you need a tlb shootdown then (?)
lament grove
yes
carmine current
i think it's better to just handle the spurious fault
lament grove
In theory
carmine current
and do a local invalidation in the fault handler
blissful bluff
i think it's better to just handle the spurious fault
but it's difficult with the stack
lament grove
i think it's better to just handle the spurious fault
No my kernel handles interrupts in that exact stack, I don't have per-core IRQ stacks, I use the current kernel thread's stack for that
This is specifically a my kernel thing
carmine current
No my kernel handles interrupts in that exact stack, I don't have per-core IRQ s...
hm, that's a good point
blissful bluff
what you can do instead is touch the beginning and the end of the stack or something?
lament grove
what you can do instead is touch the beginning and the end of the stack or somet...
No every page
lament grove
Wait actually no, I already do this fence because of the prefaulting I do for kernel mappings by default
blissful bluff
huh
lament grove
what you can do instead is touch the beginning and the end of the stack or somet...
Every page because the spec theoretically allows the CPU to cache any PTE at any arbitrary time for any reason
blissful bluff
how large are your stacks?
blissful bluff
lament grove
But in Release mode you get away with a lot smaller
blissful bluff
Yeah
Idk, I feel like I don't have to bother with any of this because of the stack per CPU, which I allocate on boot
carmine current
hm, that's a good point
I didn't consider this. Ig that means that doing a shootdown is better than doing a lazy local invalidation
lament grove
Idk, I feel like I don't have to bother with any of this because of the stack pe...
Oh yeah if your IRQ stacks are per-cpu and permanent then you don't have this problem
blissful bluff
I didn't consider this. Ig that means that doing a shootdown is better than doin...
Now that I think of it, wouldn't it be handled by the TLB flush the first time the thread is scheduled (per ASID)?
No, nevermind
lament grove
Now that I think of it, wouldn't it be handled by the TLB flush the first time t...
No cuz kernel mappings are global so they exist in all ASIDs
native prairie
I didn't consider this. Ig that means that doing a shootdown is better than doin...
wdym by better
like how else would it even work if a core faults on its own stack thats negatively cached
double fault risc-v equivalent?
lament grove
double fault risc-v equivalent?
Yes
native prairie
is that a thing
native prairie
would it just page fault forever?
lament grove
So make sure you don't fuck up your IRQ stack!
lament grove
would it just page fault forever?
Every time your page fault handler accesses through the stack, so yes
carmine current
rv trap entry does not touch the stack
so you could switch to a separate stack if you detect nested pf, for example
native prairie
oh ok
blissful bluff
my trap handler keeps a count on the trap depth
lament grove
so you could switch to a separate stack if you detect nested pf, for example
You could do this but it's not worth it imo
blissful bluff
so you could switch to a separate stack if you detect nested pf, for example
so yeah, you can do that
lament grove
If your VMM is broken the kernel is toast anyway, same thing for the IRQ entry stub
blissful bluff
like on one side, x86 is a bit annoying because it's pushing everything on stack on interrupts, etc.
on the other hand, you've got to deal with a lot of bs as well because risc-v doesn't do it
lament grove
on the other hand, you've got to deal with a lot of bs as well because risc-v do...
Wdym all you need is some scratch space so you have a register free and can get the stack pointer
carmine current
in the case of Managarm we could just detect if we fault with interrupts disabled
lament grove
That'd just be a struct pointer you put in sscratch
carmine current
and switch to a pseudo double fault stack
lament grove
Also AFAIK ARM would have similar issues, it too being a RISC architecture with a soft-stack
carmine current
since outside of this case, we never fault with interrupts disabled
blissful bluff
Wdym all you need is some scratch space so you have a register free and can get ...
no, but like if you get a pagefault (or another interrupt) in a pagefault, scause gets overwritten, etc.
carmine current
I don't think arm allows negative tlb entries
lament grove
no, but like if you get a pagefault (or another interrupt) in a pagefault, scaus...
Yeah so you save that info
blissful bluff
So you can't just push it into the stack
lament grove
So you can't just push it into the stack
You're not supposed to set SP to the same stack top on double fault WTF
This is stack semantics BASICS
lament grove
Like you've got to handle double faults explicitly
I imagine ARM would be the same though
blissful bluff
On x86, the stack is functional by the time you're in an interrupt handler, and at least you can immediately push %cr2 onto it
(FRED is even nicer in that regard)
lament grove
Skim of ARM docs shows it is the same as RISC-V in this regard
No existance of double faults
blissful bluff
On x86, the stack is functional by the time you're in an interrupt handler, and ...
Even if you were to have negative TLB or pageable stacks or whatever
lament grove
Though it does seemingly let you set SP
IDK, this really isn't that big a deal because you only really write the code that interacts with this once
blissful bluff
On risc-v you've got to have some always functional per-CPU struct bs, with a small stack for scause and the other register there before you can touch the stack
slow reef
(FRED is even nicer in that regard)
yeah with fred you don't even need to push anything :3
carmine current
"soft double fault" (or whatever you want to call it) handling seems non-trivial
you need to save some state to memory before it's possible to "double fault" and you need to detect the double fault w/o using the same save location as the outer frame
cinder trench
why do negative tlbs help with software walks? i never really looked at software...
The ultimate reason (I don't think I saw anyone say this) is because it eliminates a branch from the TLB refill code
You don't have to check the valid bit on the PTE and branch to the page fault handler if it's 0
You blindly load the PTE and the hardware checks the valid bit for you
trim eagle
new browser coming right up
native prairie
new browser coming right up
Which one is this
native prairie
Interesting
carmine current
which is a daily drivable browser compared to the webkitgtk minibrowser that we had before
true kernel
can managarm kernel (and it's userspace) be built in managrm?
carmine current
Managarm itself can be built in Managarm but probably not the whole distro
carmine current
I think there are some known issues with autoconf, i have a fix for some of them locally
trim eagle
Managarm itself can be built in Managarm but probably not the whole distro
*testing is pending on that claim
Mlibc is absolutely a thing tho
trim eagle
I think there are some known issues with autoconf, i have a fix for some of them...
you bet there are
carmine current
I did test it in the past
trim eagle
I did test it in the past
LLVM isn’t shipped with clang
So unless you did a llvm package build locally…
carmine current
I think I had that for a while yeah
trim eagle
Then that’s good to know
I was actually wondering if that worked
Good to know that it does
carmine current
I only tested managarm + mlibc though (and maybe only the kernel on the managarm side)
trim eagle
I should enable clang and subpackages it
carmine current
but I'm reasonably confident that it should still work
trim eagle
That’s nice
carmine current
unless clang regressed
but meson is known to work (I use it regularly) and clang used to work
carmine current
yeah i'm also using ninja
trim eagle
Unless Bragi (and therefore python) does funny stuff
carmine current
I'm often doing mlibc compilation as a benchmark for kernel changes
trim eagle
I'm often doing mlibc compilation as a benchmark for kernel changes
It’s a good benchmark
upbeat smelt
Unless Bragi (and therefore python) does funny stuff
bragi is pure python for the most part, only real dep is lark, which i think is also just pure python
onyx cloud
new browser coming right up
😍
brittle mauve
serene portal
Hello
carmine current
very cool
vestal sapphire
Dennis on watch?
trim eagle
Dennis on watch?
You’re number 3 that said it
I blame the fucking clanker
The worst part? I think I had the rust patching issue sorted out as well
carmine current
there was basically no rust work needed
just updating the vendored crates to versions we already have in bootstrap
vestal sapphire
damn
carmine current
i mentioned before a few times that i don't think rust is a problem, so i was right
trim eagle
just updating the vendored crates to versions we already have in bootstrap
And how much pain was that? And I know it was clankered but was it that doable by hand?
carmine current
the main problem is probably indeed dealing with the build system which LLMs definitely help a lot with
I think it's doable by hand but yeah, figuring out how to do it was done by claude
serene portal
And how much pain was that? And I know it was clankered but was it that doable b...
yes
besides bumping, libc needed small fixes to the linux constants
trim eagle
besides bumping, libc needed small fixes to the linux constants
That’s not weird. Idk how up to date the bindings are
serene portal
what probably wasn't doable by hands was the mlibc debugging
i discovered about 12-13 issues
trim eagle
And yet I see 0 issues opened
serene portal
the PR i opened also affects firefox btw
trim eagle
Where issues
carmine current
what is the total diff size of the firefox patch?
carmine current
what is the total diff size of the firefox patch?
i assume that definitely needs manual cleanup, right?
serene portal
I see no PR. Only issue
huh
carmine current
Issues are a good start though
serene portal
#1793
carmine current
Issues may be better than clanker generated PRs in some cases
serene portal
yes i need to split it, but it also fixes some firefox hangs
serene portal
Issues may be better than clanker generated PRs in some cases <:meme:57544509458...
yes
carmine current
okay, so I did so the aligned alloc this morning and it works but there is one edge case that i need to think about
serene portal
firefox wants memalign, which i wired to posix_memalign
secure_getenv is broken
the Relhack shit in ld.so
ill upstream stuff today
but slavery first
also managarm had some race condition in ext2 and corrupted truncated inodes
cinder trench
bitches come and go bruh but you know i stay
serene portal
W
carmine current
also managarm had some race condition in ext2 and corrupted truncated inodes
had = you have a fix?
serene portal
👍
that one i made myself
something about how the sizes are rounded was broken too
i have about 30 changed files in my local tree
dense umbra
You should make a youtube video post "vibe coding a firefox port using ai" and get vc funding
serene portal
i still have some form of self respect
limber grail
how do i build an ISO or something i can flash on an usb and boot managarm on a real computer?
trim eagle
Either pull the nightly or follow the handbook on how to make an image. That image should be bootable from an usb too
limber grail
Either pull the nightly or follow the handbook on how to make an image. That ima...
okay
trim eagle
That said, nightly seems to not boot??
@carmine current @vestal sapphire https://builds.managarm.org/projects/managarm/2026-06-09T22:57:38/logs/pdJl7uwrKXvl01oqn75jRg/raw
limber grail
That said, nightly seems to not boot??
https://builds.managarm.org/projects/managarm/2026-06-08T17:59:42/jobs i took this image
imma try writing it to an USB and booting it
trim eagle
Alright let us know how that goes
limber grail
Alright let us know how that goes
tho i have to go to school now and the ETA for the usb write is 15min, so i will prob do it later lmaoo
limber grail
trim eagle
2 new blog posts today!
molten meteor
indeed
btw, do you restrict devices from interacting with system resources by default using the iommu, or you allow a device to access anything unless there's a driver in place which can decide what can be isolated or not?
right now in my kernel i set up the iommu and apply whatever settings are recommended by the firmware, but i dont do anything further
vestal sapphire
recommended by firmware == RMRRs?
currently, the default is to "deny all" for a device, but drivers can enable either passthrough mode or DMA remapping mode
molten meteor
the only iommu i implement is the amd one, and the firmware doensr report to me any exclusion memory ranges, so by firmware settings i mean smi filters/some weird caching and ht bits
vestal sapphire
ah right
molten meteor
nothing else, devices can access memory freely
i just don't know what to do with the south bridge or the gpu, which i won't have a driver for it anytime soon
molten meteor
okie
so, for video devices for example
what do you do? do you disable memory access, as you say by default?
vestal sapphire
we switch them to use passthrough mode, so they just continue to run
hmm maybe we should generally put devices with RMRRs into pt mode straight away, otherwise you get races
vestal sapphire
passthrough mode is an IOMMU feature, where it just passes through all DMA requests without translation
iirc AMD also has it
molten meteor
ah okay, so its an intel terminology thing probably
have you tried restricting memory access for the gpu to access its framebuffer memory?
im not sure whether a device would send a memory transaction towards its own BAR, and whether it would be redirected upstream
vestal sapphire
ah amd passthrough is probably controlled in the DTE by
I = 1
IW = 1
IR = 1
Mode = 0b000
molten meteor
i have never looked into vt-d but i suppose amd iommu is saner lol
does the intel iommu give an irq when a command is processed?
vestal sapphire
I think they are very similar except for
- VT-d has a legacy register interface for invalidation, which is not that useful really
- IOMMU discovery is done differently
obv register and data layouts are different, but they end up doing the same
vestal sapphire
does the intel iommu give an irq when a command is processed?
the only 'commands' we send are invalidations, and you can enable a cache-coherent dword write and/or a MSI
molten meteor
and can you enable that for any command?
vestal sapphire
yesn't, you post descriptors to the ring, and the completion is configured in a wait descriptor that you can post
molten meteor
ah okay, then it works the same
vestal sapphire
so that wait descriptor (and its dword write/MSI) only get tripped once all preceding cmds have completed
molten meteor
yeah
it's exactly the same then
does vt-d also allow to place an unmodified cr3 page table hierarchy as a pasid translation table, and treat requests with no pasid as if it had some pasid?
with the amd iommu you can do this, so if the intel one can do too it would be extremely based
vestal sapphire
I have not dealt with PASID stuff, idk
carmine current
hmm maybe we should generally put devices with RMRRs into pt mode straight away,...
actually, i think we should switch everything to empty spaces with only RMRRs mapped
vestal sapphire
empty space vs deny-all is the same, except for RMRRs anyway
(with what we impl rn)
carmine current
well yeah but not mapping RMRRs is a bug
carmine current
because you can just put your cr3
doesn't really sound that useful imo
we don't map all the driver's memory into the dma space
we only map the subset that's needed for DMA
molten meteor
i plan to use that feature once i implement svm
because i could use the nested page tables and not have to deal with the nested page tables and the iommu page tables separately
but yeah, considering that managarm is a microkernel and therefore most stuff is in userspace page table entries, it doesn't sound useful
valid heath
this chat is like 90% mods lol
native prairie
this chat is like 90% mods lol
because this project is mostly developed by the mods of this server
raven iris
I submitted one package to the repos I'm a managarm dev fr fr
valid heath
I submitted one package to the repos I'm a managarm dev fr fr
yeaaaaa :D
vestal sapphire
cooking
native prairie
Is this 3d accel coming up?
vestal sapphire
no, DMA remapping support for nvidia
vestal sapphire
Is this 3d accel coming up?
for that, somebody needs to fix up https://github.com/no92/mesa-nvk-on-nvo
native prairie
for that, somebody needs to fix up https://github.com/no92/mesa-nvk-on-nvo
How much work would that be
vestal sapphire
they have, with the proprietary nvidia libs
that mesa fork makes some vulkan apps work with the mesa NVK + nvidia-open driver combo
but e.g. anything running on Zink is broken
native prairie
Ah I see
carmine current
We could try running the proprietary driver with the abi translation that qwinci was working on 
vestal sapphire
It will do raw syscalls tho
golden maple
when managarm linuxlator
carmine current
It will do raw syscalls tho
that's the point of the abi translation
(which is not implemented yet for arbitrary syscalls)
vestal sapphire
Yes but not entirely
The most obvious work is matching up stuff that is libc internal, such as pthread structs
Like say someone has a pthread_once global which uses the initializer macro
That would need adapting from a program compiled against glibc to run on mlibc
carmine current
yeah true
native prairie
its probably still less work than trying to get the mesa userspace libraries to work ig
maybe an actual syscall redirection layer would be easier
to a special linux server
carmine current
you could probably let an LLM explain to you how the mesa concepts map to the DRM ones etc
after letting it dig through the mesa source
native prairie
yeah the clanker is extremely good at explaining a codebase tbh
carmine current
that might be significantly easier than going through a couple 10k lines manually :^)
native prairie
if you have enough tokens you can make it do the work even
as long as theres a test case it can spam
carmine current
Managarm's kernel running under RISC-V virtualization on Managarm, by @brittle mauve
native prairie
@brittle mauve is the risc-v virt api really that easy to use
brittle mauve
The most obvious work is matching up stuff that is libc internal, such as pthrea...
I wonder if they'd work with the preloaded compat library, that could be interesting to test (ig I could also do that now that I have a second screen again )
brittle mauve
<@379250891838193667> is the risc-v virt api really that easy to use
compared to e.g. vmx yeah, there are like 5 registers that you use to configure whether some instructions trap + what interrupts/exceptions are delegated to the guest. then there are the guest copies for a lot of the CSRs that the guest sees as the real CSRs when in virt mode (which you enter by using the same instruction you use to return from exception/interrupt, just setting a bit that tells it to enter the virt mode + at which mode (virtual supervisor/virtual user))
native prairie
thank god paolo bonzini exists (iirc he was the one who told them how to do it)
brittle mauve
the only complain I have is the fact that the vmexits go to the generic trap handler on the host so you basically have to overwrite the trap handler register unless you want to have additional complexity in the generic trap handler (as then you'd need to tell apart not only user/kernel but the hypervisor case too + the hypervisor stuff needs sscratch too as there is no automatic saving/restoring of sp)
and then that a register that's supposed to contain the instruction that trapped is allowed to be zero but ig that's probably not a thing on real hw (hopefully at least)
brittle mauve
probably yeah or if its some small embedded core
native prairie
but also like its not x86 where a decode assist is super useful
you could probably cover those manually
brittle mauve
yeah, there are also instructions that you can use to read the bytes that use the guest translation tables with the appropriate permission checks (though you do have to be careful because they can generate exceptions), without those it could be very painful as you don't necessarily get the faulting guest phys addr either
native prairie
Interesting
carmine current
and then that a register that's supposed to contain the instruction that trapped...
does that register contain the instruction bytes?
so effectively it allows you to skip a page walk if it's implemented, right?
brittle mauve
yes
carmine current
rv has vm load/store instructions anyway, right? so getting the instruction would be easy in any case
brittle mauve
the only slight annoyance is the fact that they can fault
carmine current
ah
but for that you can just make a doCopy{To,From}User-like function
and re-use the same mechanism
brittle mauve
it should probably work yeah, at least as far as I understand the spec wording it should just generate a normal page fault
for the instruction fetch case its also not really a concern whether the guest phys->host phys map has it mapped, if it doesn't then the guest couldn't execute it anyway. it'd be a concern if you would try to use the instructions to read memory that wasn't accessed by the guest (as then it wouldn't necessarily be properly mapped due to the lazy mapping)
carmine current
well, the guest could have a second vcpu running in parallel that changes the mapping
for the trap handler, what's the problem that requires you to have a separate stvec?
brittle mauve
one problem is that the host tp has to be saved somewhere and I just used sscratch for that but that would mean that it alone can't be used to distingush between user/kernel (there is a bit in the hstatus CSR that tells whether the previous mode was hypervisor, ig that could technically work but then there has to be logic gated behind the hypervisor feature in the asm)
carmine current
Hmm
brittle mauve
and it'd mean that the stuff the hypervisor vcpu run loop does would either have to be done from inside the generic trap handler or it'd have to return to the vcpu loop with the guest regs stored inside the vcpu (instead of returning back to the guest) which it basically has to do anyway at least in the case where the vcpu run syscall must exit back to usermode
carmine current
actually, instead of pointing sscratch to kernel tp when in userspace (as we do right now), we could let sscratch point to a
struct TrapSaveState {
uintptr_t scratchSp;
uintptr_t handlerSp;
uintptr_t kernelTp;
};
so basically that'd mean:
sscratch = 0on entry => keep using current stacksscratch != 0on entry => write sp to TrapSaveState::scratchSp and load TrapSaveState::handlerSp
carmine current
You can now, on Managarm:
- open epiphany, navigate to our GitHub
- ssh-keygen, copy the pubkey from Konsole to Epiphany and add it to GitHub
- git clone managarm over SSH
- make changes
- push and post a PR
forest bear
btw I've been meaning to ask, what is the incentive for nlnet to sponsor such projects?
carmine current
it's a fund to support smaller open source projects in Europe
specifically (but not only) projects that contribute to an open internet
trim eagle
You can now, on Managarm:
- open epiphany, navigate to our GitHub
- ssh-keygen, ...
merged from Managarm too
vestal sapphire
rate my local shit
vestal sapphire
I'm having to debug the nvidia-open driver on managarm now
something seems to have broken it at some point, and I can't tell what
it's probably some stupid trivial thing
on the other hand, it would be nice to have that driver on some other OS; I'd be willing to help with porting that over. the prerequisites should be simple, have (most of) the infrastructure already in place and tested; any volunteers?
carmine current
That's quite a detour, I'd test it with hard coded DRM calls
I doubt that porting the driver to another OS gives you any insight
it'll either be: it doesn't work on the other OS or it works
and in the "doesn't work" case you don't know what's broken
vestal sapphire
having a data point for how it behaves on another OS would be massively useful to me
linux is not useful for this, though
carmine current
I think the usefulness doesn't justify the cost though
why is linux not useful?
have you tried running a small DRM test program instead of a full window manager?
vestal sapphire
problem is that I sometimes even get problems during init
carmine current
if you get early failures, can't you log what's happening etc?
vestal sapphire
Not enough
carmine current
i doubt that porting is going to help then
you'll just run into different issues that are equally hard to debug
IME investing into sophisticated debugging techniques almost never pays off in the short term vs. just logging more etc
vestal sapphire
oh no I actually have a suspicion
I see sddm getting killed by SIGCONT, is that a problem
sddm failing would only explain half of the issue tho
carmine current
I think you should just test a simpler test case first
Just launch a test program with a systemd unit instead of launching sddm
vestal sapphire
WTF
I am now basically just running https://github.com/dvdhrm/docs/tree/master/drm-howto
and it still doesn't do jack shit
WHY
it works on virtio-gpu
trim eagle
I see sddm getting killed by SIGCONT, is that a problem
That might just be sddm going to sleep after auto booting to Weston
And we don’t handle SIGCONT and friends properly yet iirc
raven iris
on the other hand, it would be nice to have that driver on some other OS; I'd be...
I've been thinking about porting it to Genode but idk
Although my only pc with an nvidia gpu currently can't boot sculpt os which is an issue
raven iris
Well it boots to Leitzentrale but the graphics are glitchy and it freezes right after
vestal sapphire
if you can run it on qemu, you can just do PCI passthrough
you will need to fiddle a bit with the layout, but it can be done
iirc you need to put all PCI functions of the GPU onto one PCI device on qemu, and I think that should be behind a bridge
raven iris
if you can run it on qemu, you can just do PCI passthrough
Yeah maybe
I noticed that i can run Sculpt 25.10 fine but 26.04 and beyond lock up instantly
I'm thinking it's a buggy driver somewhere
I was considering passthrough though yeah
dusk solstice
btw I've been meaning to ask, what is the incentive for nlnet to sponsor such pr...
adding to this, what will it actually be used for (i know the article mentions updates that it will be used for but I'm curious how the money would actually help with things like that) out of curiosity?
carmine current
The money helps contributors pay their bills and thus encourages contributions :^)
The money is paid out for completed milestones
dusk solstice
The money is paid out for completed milestones
oh I see! I didn't actually realise contributers weren't volunteers
carmine current
oh I see! I didn't actually realise contributers weren't volunteers
Contributors are volunteers
dusk solstice
seems like a flexible definition for volunteer if they get paid for specific milestones lol
carmine current
seems like a flexible definition for volunteer if they get paid for specific mil...
I'm not sure if you have the right picture in mind lol
"they" include me, right?
This is a grant that NLnet pays us (= the ppl working on the project) for completing specific milestones
native prairie
seems like a flexible definition for volunteer if they get paid for specific mil...
it's mostly also preexisting people that worked on managarm before nlnet
carmine current
It's not that I (or anybody else) select who gets paid and what amount they get paid
Yeah, we all wrote the grant application together
And everybody on the grant contributed to Managarm voluntarily before
The grant's task plan says something like: implementing RISC-V virtualization is worth xxxx€ and whoever (out of the set of ppl listed on the application) does the work gets the money
dusk solstice
This is a grant that NLnet pays us (= the ppl working on the project) for comple...
ohh that makes sense
vestal sapphire
some are, some are not
carmine current
all syscalls that do any io are async
valid heath
all syscalls that do any io are async
Even file io?
Does it return a pointer to some kind of promise?
trim eagle
oh I see! I didn't actually realise contributers weren't volunteers
I wish I was paid a proper salary to work on Managarm. You looking to sponsor?
Slavery (minimum wage grocery store) gets boring quickly
dusk solstice
I wish I was paid a proper salary to work on Managarm. You looking to sponsor? <...
if I'm ever an eccentric millionaire I'll be paying every osdev a salary
trim eagle
Deal