Hello! I made a RISC-V emulator with some basic aah instructions so far
https://github.com/PetrarkaR/apocacore
And I was wondering if someone could take a look at just check if this is the right way to go about decoding instructions executing them. Currently everything works, you can run the thing with
python3 cpu.py -f test.apo -r Run -d debug
Maybe the argument parsing needs some... redoing
any other possible suggestions are very much appreciated
#๐ RISC-V emulator overview
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@slate onyx
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Just to the CLI, I'd personally lean towards python3 cpu.py run -d debug test.apo i.e. a pattern with a "run" subcommand (even if it's the only subcommand) so you don't need -r, and "run" would always need a .apo file so you don't need -f.
Otherwise the code itself seems reasonable to me. @slate onyx
thanks, imma think about that, this is gonna be awesome
As an outsider it could do with some comments. There's quite a few magic numbers in there (the shift sizes, the names of the op codes etc). Just one liners.
Well those are fixed in the documentation of the RISC ISA but aight, I guess I could make it more accessible, wont hurt, thanks sir cameron
Also, an overall comment up the top with a URL to the RISC ISA docs on the web. That lets the reader go to your reference source.
Example: https://github.com/cameron-simpson/css/blob/d72f226a0d6a92ae15b3c35d34912f70d3ca19ba/lib/python/cs/iso14496.py#L10
lib/python/cs/iso14496.py line 10
ISO make the standard available here:```
Gonna put that in tonight, gonna be a long one, implementing all the instructions probably along with some RVV instructions
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