#๐Ÿ”’ RISC-V emulator overview

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slate onyx
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Hello! I made a RISC-V emulator with some basic aah instructions so far
https://github.com/PetrarkaR/apocacore
And I was wondering if someone could take a look at just check if this is the right way to go about decoding instructions executing them. Currently everything works, you can run the thing with
python3 cpu.py -f test.apo -r Run -d debug
Maybe the argument parsing needs some... redoing
any other possible suggestions are very much appreciated

GitHub

A RISC-V based processor simulator? I am not really sure what this is. I am not good at this stuff yet. - PetrarkaR/apocacore

versed umbraBOT
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@slate onyx

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still fulcrum
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Just to the CLI, I'd personally lean towards python3 cpu.py run -d debug test.apo i.e. a pattern with a "run" subcommand (even if it's the only subcommand) so you don't need -r, and "run" would always need a .apo file so you don't need -f.

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Otherwise the code itself seems reasonable to me. @slate onyx

slate onyx
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thanks, imma think about that, this is gonna be awesome

still fulcrum
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As an outsider it could do with some comments. There's quite a few magic numbers in there (the shift sizes, the names of the op codes etc). Just one liners.

slate onyx
still fulcrum
versed umbraBOT
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lib/python/cs/iso14496.py line 10

ISO make the standard available here:```
slate onyx
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Gonna put that in tonight, gonna be a long one, implementing all the instructions probably along with some RVV instructions

versed umbraBOT
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