I'd like to see some form of memory component that has an input defining the write width. It would make it so much easier to create memory for architectures that have variable width memory operations (Ex: Risc-V has save word and save byte)
#Configurable width memory by wire
last pivot
I couldn't find any other posts with the same idea, but there still might be ones out there.
muted pumice
The IO -> Advanced -> Delay Line Config and Register Config components already do that. If you don't see them, go to the Sandbox and open the Component Factory from there
formal axle
Sounds like they want dynamic control, not static.
muted pumice
In that case yes you need to write your own component to perform a large read into a buffer, overwrite some or all of it, and then write back the buffer
trim valley
And as long as you're not using latency ram, it can all be done in one tick