custom level ideas

[deep oracle]

I am curious to discuss custom level ideas somewhere. Maybe we could do some prototyping in advance using the Sandbox ?

Some topics i am curious about :

• floating point encoding and basic ops
• same with decimal floating point (yes i know very niche subject)
• endianness with some real examples from the history of computing (https://justine.lol/endian.html)

• basic principles of graphic acceleration, again using real examples from the history... think https://en.wikipedia.org/wiki/Bit_blit and friends, sprites, etc..

• vector display (not sure it can be done)

• hardware based data encryption (again ideally using algorithms used in the past)

• hardware based data compression (generic data, image data)

• soundchip style sound generation (not sure it can be done)

• historical sound effects and stereo mix from digital audio samples (using real examples from history ?) maybe audio I/O to show how audio can be used to save data like with classic tapes in 8 bits era.

• hardware terminal implementation on top of the raster display

• "hardware only" video game tutorial, in the style of https://www.youtube.com/watch?v=ppmM2zAbeEU or other verilog/vhdl games ideally creating reusable components along the way.

• some kind of SIMD extension for the base game processor (needs a concrete application and maybe a naive implementation without SIMD to show the performance boost) maybe applicable to audio processing ?

I am not sure if custom level could be mostly software oriented too. Like a Forth implementation, a 8 bits era like Basic implementation...

[sand notch]

Definitely efficient graphics stuff would be awesome

Needless to say tho, I'm incredibly excited for the custom levels

[deep oracle]

I fear the complexity of the distribution of the custom levels. Some issues i see are save compatibility when the levels are updated, who can translate them... Anyway this will be stabilized in time for sure. But the dependency hell is around the corner.

If the level can use components from the base game, these components may need to be versioned too

once there will be a lot of custom levels, maybe this will make it difficult to update the base game

The more complex stuff we build inside TC, the more performance we will ask from the simulation engine

and the more features we will need to troubleshoot the designs (think logic analyzer). This is an endless endeavor..

If the project is going to continue in this "prosumer" direction, i feel the logic analyzer could be a DLC.

[sand notch]

Perhaps you could make a series of levels focusing on multiple-tick computers

Code and data in the same RAM

[deep oracle]

I am not familiar with this multiple tick concept.

[deep oracle]

the pedantic name is Von Neumann architecture ? in opposition to Harvard Architecture

[sand notch]

I'm still not really sure about the definition of Von Neumann architecture

[deep oracle]

Some writer used this name but obviously Von Neumann means the whole architecture not only the memory busses design originally. There is a wikipedia page also https://en.wikipedia.org/wiki/Von_Neumann_architecture

[sand notch]

I guess what I mean is indeed a Von Neumann architecture

[deep oracle]

This shared RAM makes it easier to generate or modify code. This level could be used to demo self modifying code which was a big optimization in the days of cacheless CPUs.

Were you thinking of another use case ?

[sand notch]

I'm thinking of it being a guide of how to actually build that thing

[deep oracle]

Obviously this design with one bus / RAM component is cheaper than design with two busses / RAM components. This could show up in scores.

And also more flexible

[deep oracle]

Do you mean a microcoded CPU ?

[sand notch]

I mean a CPU that takes multiple ticks to do an instruction

Classic fetch->decode->execute->store

[deep oracle]

microcode is an implementation design in which cpu instructions are called macro instructions and are themselves implemented as a sequence of microinstructions, which means they execute in more than one ticks.

the CPU then executes the microinstructions in hardware and contains some kind of table/ROM to describe the macro instructions

[tribal tinsel]

you can do multi-tick CPUs (at least in TC) without a table of micro instructions. would that then be a multi-tick CPU without microcode?

or is this kind of multi-tick definition only relevant in TC with its somewhat rigit ticking system?

[deep oracle]

TC clock is somewhat rigid but the concept of multi cycle cpu is a real thing, there is indeed also a wikipedia page for it.

Early microprocessors did not have the transistor budget for full blown microcode ROM so the designs were more coupled but i feel it is easier to explain a microcoded design.

[tribal tinsel]

https://en.m.wikipedia.org/wiki/Multi-cycle_processor

this article is a stub
welp

[deep oracle]

A crazy level would be like : find the bug in this microcode... It's often more difficult to debug something than to write it from scratch

I would like to spend some time in "brainstorming mode" to gather ideas. Obviously implementation will start with small steps, and I know that i could already spend a lot of time with floating point. Decimal FP and endianess are things i am quite confident i would like to do.

I am not sure if the base game explains the concept of interrupts (for IO). After that, there is Direct Memory Access (DMA)

[deep oracle]

emulation : overture emulator, turing machine emulator ?

[deep oracle]

new idea from the discussion about decimal floating point : component performing binary coded decimal operations in some legacy style https://en.wikipedia.org/wiki/Intel_BCD_opcode : not high priority for me as it is both obsolete and low performance (unless we include the need to convert the result to ASCII)

[sturdy rampart]

Better division level would be nice

[tribal tinsel]

what kind of suggestions for a better division level do you have?

[sturdy rampart]

Hardware Division, I know it can be done I don’t fully understand it thou

The division level in game intends for you to use an algorithm with ur computer

[tribal tinsel]

tbh it "intends you to use algorithm" as much as any architecture intends for you to do that - and all levels can be turned into asics

[deep oracle]

in the 90s history department : level serie inspired by Motorola's 56000 DSPs (24bit fixed point, Harvard architecture, used for signal processing at the time typical algorithm FFT)

https://en.wikipedia.org/wiki/Motorola_56000

[rapid comet]

I'm pretty sure that once the custom levels are rolled out, players will begin to create the most difficult and complex levels known to man. Just look at SpaceChem!

Here are my (utterly deranged) ideas:

• Build a 64-bit Carry-Lookahead Adder with carry in and carry out (delay limit will be imposed to prevent the use of shitty Ripple-Carry Adder or chaining multiple 8-bit CLA).
• Recreate the OVERTURE architecture using only ( not allowed) and Delay Lines. Oh, and no custom component for you, too!
• Same as above, but for LEG architecture, and RAM (only up to 16 values are checked), stack (up to 8 values), and the PUSH/POP instructions (will be checked, no "can we trust you" shenanigans) included.

[deep oracle]

80's History/ classic toy department : lpc10 speech synthesizer https://handwiki.org/wiki/Texas_Instruments_LPC_Speech_Chips

[deep oracle]

early electronic toy microcontroller based : https://en.wikipedia.org/wiki/Simon_(game)

[deep oracle]

• Level serie to introduce https://en.wikipedia.org/wiki/Hamming_code needs a source of error / entropy in the game engine ? (this guy is my hero)

[deep oracle]

In the IO serie, after interrupts, DMA, maybe some memory mapped peripheral controllers

Of historical interest : https://en.wikipedia.org/wiki/SWEET16

[rapid comet]

Some more utterly deranged custom level ideas:

• Build a 128-bit ALU similar to the one used in OVERTURE.
• Build an exponentiation machine that accepts two 8-bit numbers and outputs 64-bit numbers (modulo 2^64, obviously)
• Find the square root of a 64-bit number, rounded down to the nearest integer.
• Generate a random prime number between the given two 64-bit number range.

[deep oracle]

• some kind of fantasy console (TIC 80 like)

[deep oracle]

looks like an int numerical challenge level serie ?

[rapid comet]

No. Just batshit insanely difficult easy to make, hard to execute levels.

[deep oracle]

ok why not

it makes me think of https://en.wikipedia.org/wiki/Enigma_machine algorithm implementation (would be a Turing tribute too)

[rapid comet]

I've already thought about crazy custom levels here: https://discordapp.com/channels/828292123936948244/828292126328487998/905872467459973121

[deep oracle]

I see risc-v is too easy for you. I write crazy stuff as i am brainstorming not because i search for extreme difficulty in itself. But with the public that TC has, there will obviously be an audience for hard levels

[rapid comet]

I don't consider RISC-V to be easy, I'm not a hardware developer. But even if I don't make these levels... someone else will.

[deep oracle]

RISC-V 128 bits will be quite a curiosity. For now i think it only exists as an emulator https://bellard.org/tinyemu/readme.txt

[shrewd fractal]

I would guess that you can't upload levels that you don't provide a working solution for

[deep oracle]

I completely agree that TC will need such a feature

But also there is a need for team development of levels

Beating the custom level author implementation performance could be some kind of achievement

• Some implementation of the https://en.wikipedia.org/wiki/Compare-and-swap and https://en.wikipedia.org/wiki/Double_compare-and-swap ideas. (CAS2 has been mostly abandoned http://68k.hax.com/CAS2) maybe in a lock management / multiprocessing level serie / ASM data structures serie

[deep oracle]

• ARM1 implementation (instruction set designed by https://en.wikipedia.org/wiki/Sophie_Wilson in 1983-84)

[deep oracle]

• hw implementation of cellular automata (like Conway's Game of Life or some other examples from Wolfram's https://en.wikipedia.org/wiki/A_New_Kind_of_Science)

• assembly programming problems maybe inspired from https://projecteuler.net/archives or https://rosettacode.org/wiki/Category:ARM_Assembly)

[deep oracle]

-Assembly optimization puzzles inspired by https://agner.org/optimize/optimizing_assembly.pdf and https://agner.org/optimize/microarchitecture.pdf including self modifying code

• level serie focused on parrallel processing (the kind of processing we currently have on GPUs, maybe starting with ancient design like https://en.wikipedia.org/wiki/Transputer) this is really unfamiliar stuff for me. This is not https://en.wikipedia.org/wiki/Symmetric_multiprocessing.

[deep oracle]

• blinkenlights for LEG (possible inspiration : https://www.theregister.com/2018/05/21/raspberry_pi_pdp_11_revival/ http://retrocmp.com/projects/blinkenbone/simulated-panels/247-blinkenbone-simulated-pdp11-40-panel)

[deep oracle]

• cs theory geeks may find inspiration in https://justine.lol/lambda/ and https://github.com/jart/sectorlisp (lambda beeing again some sort of Turing tribute)

[rapid comet]

I don't think self-modifying code is possible, knowing that program component are read-only memory.

[shrewd fractal]

It's possible by first copying code into RAM or by creating a special wrapping component that sometimes overwrites the values returned by the Program

[deep oracle]

• hardware energy management and monitoring of energy consumption during operations. Probably an engine feature request : performance/watt scoring, may help to make TC more environment friendly. Vintage CPUs had very low energy consumption due to their low clock frequencies. Performance / Watt is a recent concept, so i am not sure how to demonstrate it in a "simple" tutorial. Pentiums were the first Intel Cpus with fans, 486s had only heatsinks, 68000s had nothing. When CPUs started to "fry" some people were surprised and hw protections had to be implemented.

[fair breach]

what about a custom campaign for developing basic networking infrastructure?

[deep oracle]

Do you mean something similar to the original ethernet standard https://en.wikipedia.org/wiki/IEEE_802.3 ?

Alternatives were https://en.wikipedia.org/wiki/AppleTalk and https://en.wikipedia.org/wiki/Token_Ring

[deep oracle]

Details of ethernet frames are in https://en.wikipedia.org/wiki/Ethernet_frame This protocol has to detect/manage collisions (aka noisy / truncated frames)

not clear if there are interesting concepts in the modem department. AT commands ? V42bis hardware compression ? handshaking protocols ? Teletypes / VT escape commands ? Sounds a little too "analogic" to me. https://youtu.be/8Ab3ArE8W3s?t=1015

[deep oracle]

Tutorial to build a 1970's state of the art "4 ops calculator on a chip". http://vintagecalculators.com/html/the_pocket_calculator_race.html

• a more ambitious target would be a ti57 clone which was one of the first "mass market" personal programmable device. Programs for it can be found in the hobbyist press like Basic programs would be a few years later. https://en.m.wikipedia.org/wiki/TI-57 manual is https://archive.org/details/programmingTI57TexasInstruments1977/Assembly_300x4/mode/2up

[deep oracle]

New source of inspiration : the Radioshack catalog history https://radioshackcatalogs.com/ With time more and more products were based on digital electronics. The 1979 catalog includes https://en.wikipedia.org/wiki/555_timer_IC chips, many refs from https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits, digital alarm clocks, pocket, desktop and programmable calculators, 8080A cpu chip and computer systems.

[deep oracle]

Other family of digital IC : https://en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits

a level serie could restrict component choice to 4000/7400 series. Sample of manual for digital "science kit" : https://web.archive.org/web/20130902100205/http://www.radioshack.com/graphics/uc/rsk/Support/ProductManuals/2800027_P2_PM_EN.pdf Still confused about what to do with the analog / power part of the content.

other IC seen in the radioshack catalog in the 80's : ICL8038 waveform generator
SN76495 sound effects generator
AY-3-1350 melody synthetiser
SPO256-AL2 voice synthetizer (includes 16k ROM, requires 3.12MHZ clock crystal)
modem TCM1512A (ring detector) XR-2206 (generator) XR-2211 (decoder) (used as kit for their computers)
LM-567 tone decoder
LED Display drivers

[deep oracle]

Radioshack sold for a long time xxx-in-1 electronic project kits with manual written by https://en.wikipedia.org/wiki/Forrest_Mims I am still looking for the latest version of the digital projects manual

Before custom ASICs became the norm, appliances build from standard 4000/7400 series logic components were repairable by hobbyists, everything was big enough to be setup by hand on breadboards. Electronics could be self tought by doing using Radioshack kits and Forrests' books. Forrest himself was self taught. Maybe TC custom levels could bring some of this "hands on" attitude and satisfaction.

[deep oracle]

Found looking for 90's book teaching digital electronics : https://www.amazon.com/Digital-Computer-Electronics-Albert-Malvino/dp/0028005945

This book is on libgen and includes 3 computer designs SAP-1 to SAP-3 "Simple As Possible" including microcoded design. Second part of the book is a polyglot tutorial of ASM programming targeting the CPUs of the time (6800 6502 8080 8088). SAP computers are compatible with 8085.

What i find striking in the books of this time is that they have huge chapters devoted to Analog Digital Conversion. The authors were still in an analog world and digital processing had to cope with that. TC does not and i am not sure if this is a bad thing.

[deep oracle]

• Wikipedia has a table of major instruction sets https://en.wikipedia.org/wiki/Comparison_of_instruction_set_architectures Maybe some have ideas that could be turned into levels. The table includes the fictional https://en.wikipedia.org/wiki/MMIX created for Knuth's TAOCP books, whose exercises may also be a source of inspiration.

[deep oracle]

Chess computer project in the 80s/90s style. Technical description of Real products : https://www.schach-computer.info/wiki/index.php/Kategorie:Prozessor some are supported by emulators so software is available too. Many early products were 6502 based, later products were m68k based.

[deep oracle]

Game & Watch clone. Original used 4bit micro controllers from Sharp. Requires custom LCD screen component https://en.m.wikipedia.org/wiki/4-bit_computing http://seanriddle.com/dj101.html https://www.gameandwatch.ch/en/game-watch-information/all-60-games/535-donkey-kong-jr-dj-101.html

[deep oracle]

This indeed an interesting topic : show how software based implementations compare against pure hardware implementations for a few algorithms / applications, in term of absolute performance or other metrics. I read people saying that hardware has no systematic advantage but my experience has always been different. Or put differently can optimized software beat Less optimized hardware ?

[shrewd fractal]

If it's only a single specialized task, no

You could always take the CPU that executes the software and strip off everything that isn't needed

[deep oracle]

we agree then. I should try to find where i read this opinion

[deep oracle]

https://en.wikipedia.org/wiki/Hardware_acceleration mentions regular expression coprocessors

[deep oracle]

https://en.m.wikipedia.org/wiki/Apollo_Guidance_Computer is US government IP so public domain

[deep oracle]

• in the retro artistic department : a palette based matrix display could be used to perform palette based animations. demo available : http://www.effectgames.com/demos/worlds/ (vintage systems used lower resolutions or smaller pallettes - palette based matrix display used less RAM and were less memory intensive than true color displays they were the only option at the time). real retro example : https://www.youtube.com/watch?v=7Xfrlc3GHgQ

[deep oracle]

• the first coin op arcade video game produced in numbers, https://en.wikipedia.org/wiki/Computer_Space is build with components of the 7400 IC serie. The gameplay is cloned from the software game https://en.wikipedia.org/wiki/Spacewar! Schematics of a clone unit : https://archive.org/details/ArcadeGameManualComputerspace

[deep oracle]

• cryptographic algorithm implementations could be reused to implement some kind of https://en.wikipedia.org/wiki/Smart_card

[deep oracle]

• in the math / signed integers curiosity department : implement a base -2 CPU or at least the 4 integer operations on base -2 representation

[rapid comet]

How can it check?

You could probably make a level with a "backdoor" that only you know to bypass completing the level manually.

But if level script is made open, then players would start abusing the "backdoor". So making the script open to viewing would be one way to avoid impossible levels.

If the script is allowed to check time (possibly for randomizing puzzle), then you could make a level that completes automatically before a certain time, and then impossible after that time. So I guess the script is not allowed to be random or check time. In other words, the script must be completely deterministic.

But even then, it doesn't need to be impossible, it just needs to be really hard to solve.
What if the level asks you to "factor a product of two prime numbers"? Only the level maker knows the answer, obviously. The level maker can complete it trivially, but for others, it'll take obscenely long to complete.

[shrewd fractal]

You just convinced me that the level code should be easily visible always

[deep oracle]

In most levels i can think of the level checking code does not contain any clue towards a solution so it could indeed be open source. Maybe github or similar can be used as a repository to manage versioning collaboration and licensing.

[deep oracle]

I have a bunch of ideas that requires analog or mechanical interfaces and are probably out of scope for TC, maybe they can inspire someone else : Steeve Wozniak's https://www.bigmessowires.com/2021/11/12/the-amazing-disk-ii-controller-card/ 80's pen plotters and their https://en.wikipedia.org/wiki/HP-GL language, analog video signal generators, mechanical mouse circuit, keyboard controller circuit with https://en.wikipedia.org/wiki/Keyboard_technology#Debouncing algorithm.

[deep oracle]

I feel TC would be an ideal platform to port vintage ASM tutorials, maybe in the form of (simulated ?) vintage magazine articles. A Risc-V CPU component would allow to target a modern architecture in the same tutorial style.

[slim ether]

Or even some early C code.

[rapid comet]

I wonder if custom levels will ever be allowed to draw to the level screen?
Oh, it will open up so much possibilities!

• Visual representation of the problem provided by the level like Divide, Delicious Order, Planet Names, Water World, etc.
• Robotron our beloved, and it's back!
• To get rid of the NO SIGNAL screen.
• Custom minigame in custom levels!
• Easter eggs in custom levels?

[deep oracle]

Concerning minigames, here is a feature request to add an interface to system gamepads and joysticks : https://github.com/Turing-Complete-Game/Suggestions-and-Issues/issues/548

Controlling a custom display / visual representation with the custom level code is an interesting concept. Maybe this can be used to implement something like vintage LCD screens (fixed elements) or even simple mechanical devices like flippers.

[sand notch]

I understood the language as being a do-it-all

not just basic custom level stuff

[deep oracle]

Courtesy of Hacker News : CPU state visualisation ideas : https://monster6502.com/

[deep oracle]

Another state viz "product" : https://obsolescence.wixsite.com/obsolescence/pidp-11 + option to use switches to write/load the bootloader

[deep oracle]

how early ? First Unix was running on a PDP-11/20

[slim ether]

K&R C.

[deep oracle]

K&R first edition means 1978, there is quite a difference between first and second editions (1988)

[slim ether]

You start there, then eventually work up to C23.
Another interesting twist is to build a speedcode (One of the oldest compiled programming languages ever, not in use anymore, based straight off of machine code/assembly language), then off of Fortran (The oldest still-extant programming language), then C. From there, you have about a dozen offshoots to other modern programming languages.

[deep oracle]

Wikipedia says https://en.wikipedia.org/wiki/Speedcoding is an interpreter. https://archive.computerhistory.org/resources/access/text/2018/02/102678975-05-01-acc.pdf is the manual. Not sure that it can really be described as high level. My understanding is that the instructions were 3 digits numbers (table page 16 and later) The whole syntax was designed around the punch card.

[slim ether]

C would qualify as a High-level language back in its heyday.

[deep oracle]

maybe we have to jump to new machines as much as to new languages.

[deep oracle]

high is absolute. higher is relative. People meant higher

There was the notion of 1st gen language, 2nd gen, 3rd gen... the thing crashed at 4th gen it seems because at this stage this became a buzzword https://en.wikipedia.org/wiki/Fourth-generation_programming_language

[slim ether]

We now have a way to objectify programming languages?! That's cool!

[deep oracle]

we seems to be stuck at 3rd gen https://en.wikipedia.org/wiki/Third-generation_programming_language

https://en.wikipedia.org/wiki/Second-generation_programming_language is (macro) ASM

https://en.wikipedia.org/wiki/First-generation_programming_language is machine language (binary)

[slim ether]

So, 1GL is machine code, 2GL is assembly, 3GL is everything else, and there's no 4GL or 5GL.

[deep oracle]

i would say it's debatable if 4/5GL exist

https://windev.com/ pretends to be a L4G and Wikipedia pretends that some AI L5G prototypes exist.

[slim ether]

I can already tell you that a 4GL language exists: https://esolangs.org/wiki/Category:Pseudonatural.

[deep oracle]

https://chat.openai.com/ may be used as a L5G for example https://6502.is-a.dev/posts/aoc-2022/

[slim ether]

Or probably a brainfu- maker, as a gateway to esolangs in general. Piet'll have to skip out on this one, though...

[deep oracle]

4GL has no clear definitions. The whole concept broke down

If i had to propose some kind of criteria, this would be about dev productivity and number of potential users

But it's meaningless to compare the productivity of devs between 1950 and 2020. So we can't compare Rust to Fortran II either. It's like comparing prices between 1950 and 2020. (almost ?) Nothing we do/buy in 2022 was available in 1950.

Anyway TC explains second generation programming, cool to know.

[deep oracle]

Registerless ABI aka Stack machine (registers allowed inside the CPU but not in the instruction set) see WASM spec for an example

[deep oracle]

From HN : https://wiki.xxiivv.com/site/uxn.html

[deep oracle]

Maybe also https://www.smecc.org/The Architecture of the Burroughs B-5000.htm https://en.m.wikipedia.org/wiki/Intel_iAPX_432

[deep oracle]

If the new language / architecture allows to write custom components for the custom levels, i feel an "analog/CRT" color screen allowing "racing the beam" style programming could be very useful for retro oriented levels. I just found a book about this style of circuit design : https://worldradiohistory.com/BOOKSHELF-ARH/TAB-Books/TAB-How-to-Design-and-Build-Your-Own-Custom-TV-Games.1978-Heiser.pdf (catalog : https://worldradiohistory.com/BOOKSHELF-ARH/Bookshelf_TAB.htm)

[deep oracle]

descriptions of classic 74C / 4000 series of digital components can be found in this book : https://worldradiohistory.com/BOOKSHELF-ARH/TAB-Books/TAB-The-Master-IC-Cookbook-1980.pdf

[deep oracle]

Corewar inspired level series ? refs : https://en.wikipedia.org/wiki/Core_War https://github.com/evgenkarlson/ALL_SCHOOL_42/blob/master/00_Projects__(Основное_Обучение)/02_Algorithmic/04_1___corewar/corewar_(new).pdf

[deep oracle]

Original m68k ASM and Pascal QuickDraw sources seems to have been released. A level series on similar ASM 2D drawing routines may be interesting both for the challenge and the retrohistoric value. https://news.ycombinator.com/item?id=34447214

diskzero

The QuickDraw code (LISA_OS/LIBS/LIBQD) is just glorious. While reading it, I am overcome by the creative genius of Bill Atkinson. [1]. Bill went on to become quite accomplished at cooking lunch for the team at General Magic. [2][1] https://en.wikipedia.org/wiki/Bill_Atkinson[2] https://en.wikipedia.org/wiki/General_Magic

Hacker News · Jan 19, 2023, 11:38 PM

[deep oracle]

I just discovered that recent space missions use a FORTH dedicated CPU design : https://en.wikipedia.org/wiki/RTX2010 maybe this is simple enough to be implemented in a custom level series and demonstrated using software very similar to what the missions used. Development seems still active towards arrays of 144 simple FORTH CPUs : https://www.greenarraychips.com/home/documents/greg/DB001-221113-F18A.pdf

[rapid comet]

RTX 2060 when RTX2010 walks into the room:
...Now I wonder if we can somehow program that to do raytracing?

[sage aurora]

Crazy level idea:
Every prime ticks, return every primeth prime

[shrewd fractal]

So you want an O(n) prime algorithm? Tough luck, that doesn't exists.

[deep oracle]

A solution would need a precomputation step with a corresponding ticks budget.

[deep oracle]

Maybe custom levels can be used to integrate third party project with a copyleft licence. https://github.com/Klaus2m5/6502_65C02_functional_tests could be integrated in a GPL licensed level to provide 6502 functional testing for example.

[deep oracle]

FPGA history level series : Make the player design and or experiment with the concepts of Programmable Logic Arrays (PLAs) , Programmable Array Logic (PAL), Complex Programmable Logic Device (CPLD) towards the first reprogrammable FPGA, the XC2064

[shrewd fractal]

IIRC, these designs require engine support for bidirectional switches, which is quite complex

[deep oracle]

I agree but this is a brainstorming topic so I wrote it anyway. Maybe there will be a way to implement at least a PLA.

Now the next idea comes from GPT4. (I asked about elegant circuit design without comparable solution in software)

------ GPT4 output starts - Don't trust it ------

Content-addressable memory (CAM): CAM is a type of digital circuit that can quickly search its memory for a specific data value, providing a constant-time lookup. Software-based searching algorithms (e.g., binary search) typically have higher time complexity, making them less efficient.

Here's a step-by-step approach to introducing CAM to a digital logic student and creating a simple CAM component from basic building blocks.

Introduce the concept: Start by explaining what CAM is and how it differs from regular memory, such as RAM or ROM. Highlight the key difference: CAM searches for data based on content rather than an address.

Explain the use cases: Discuss common applications of CAM, such as high-speed searching in routers, associative caches, and pattern-matching in artificial intelligence. This helps students understand the practical significance of CAM.

Introduce the building blocks: Present the basic components required for a simple CAM cell:
a. Storage element: Typically, a flip-flop or latch is used to store data bits.
b. Comparators: These are used to compare the input search data with the stored data in each CAM cell.
c. Logic gates: These are needed for building comparators and creating the match line.

Design a simple CAM cell: Begin by designing a basic CAM cell that can store a single bit of data and compare it with an input search bit. The cell should include:
a. A flip-flop or latch to store the data bit.
b. An XOR gate to compare the stored data bit with the input search bit. The XOR gate output will be 0 if both bits are equal and 1 if they are different.
c. An inverter to generate the match signal. If the output of the XOR gate is 0, the match signal will be 1 (indicating a match), and if the output is 1, the match signal will be 0 (indicating a mismatch).

Expand to multiple bits: To create a CAM cell for multi-bit data, duplicate the single-bit CAM cell design for each bit and connect the match signals using an AND gate. The output of the AND gate indicates if all bits in the cell match the input search data.

Build the CAM array: To store multiple data words, arrange the multi-bit CAM cells in an array. Each row in the array represents a stored data word, and each column represents a bit position. Connect the match lines of all cells in a row to a common match line.

Implement the read and write operations: Design the control logic for reading and writing data to the CAM array. For writing, use a write enable signal to control the storage elements in the CAM cells. For reading, use the match signals to select the corresponding row with the matching data. Additionally, consider adding output registers to store the results of the read operation, which can help synchronize the output with other parts of the system.

Integrate an address encoder: To provide an address for the matched data, add a priority encoder or another type of address encoder to the design. This encoder will take the match signals from each row as inputs and generate a binary-encoded address corresponding to the highest-priority matching row.

Introduce optimizations and variations: After the basic CAM design is understood, discuss optimization techniques such as pipelining, hierarchical structures, and power-saving methods. Also, introduce other CAM types like ternary CAM (TCAM), which can store and search for data with "don't care" bits.

By following these steps, students can build an understanding of CAM from basic concepts to a working design, using fundamental digital logic components as building blocks.

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• Look-up tables (LUTs): D1igital circuits that can implement any logic function by directly storing its output values.

• Error-detection and correction codes: Hardware implementations of error detection and correction codes, such as Hamming codes or Reed-Solomon codes, can operate at high speeds with minimal overhead, providing real-time error detection and correction.

[deep oracle]

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Introducing bitonic sort networks to a digital logic student requires explaining the concepts and working through the process of creating a sorting network using basic building blocks. Here's a step-by-step approach:

Introduce the concept: Explain the purpose of sorting networks, which sort a fixed number of input elements using a predefined sequence of comparisons and data exchanges. Emphasize that sorting networks are deterministic and perform sorting in parallel, making them suitable for hardware implementations.

Explain the basic building blocks: The primary components of sorting networks are comparators, which compare two input values and output them in a sorted order. Introduce the concept of a basic comparator (also known as a "min-max" or "sorting" comparator) that takes two inputs A and B and produces the smaller value as output X and the larger value as output Y.

Introduce the bitonic sequence: Explain that a bitonic sequence is a sequence of numbers that first monotonically increases and then monotonically decreases or vice versa. Teach students how to create bitonic sequences by merging two ordered sequences with opposite orderings.

Construct a bitonic sorter: Demonstrate how to build a bitonic sorter for two input elements using a single comparator. Then, teach students how to expand the sorter to handle four input elements by combining two smaller bitonic sorters and adding additional comparators to merge the bitonic sequences.

Recursive construction: Show students how to construct larger bitonic sort networks recursively. For an n-element bitonic sorter:
a. Divide the input elements into two groups of n/2 elements each.
b. Sort the first group in ascending order and the second group in descending order using (n/2)-element bitonic sorters.
c. Merge the two sorted groups into an n-element bitonic sequence using a "bitonic merge" stage, which consists of log2(n) layers of comparators.
d. Apply the same process recursively until the smallest bitonic sorters have only two elements.

Building the bitonic merge stage: Teach students how to construct the bitonic merge stage for an n-element bitonic sequence. The merge stage consists of log2(n) layers of comparators, with each layer performing a specific pattern of comparisons and exchanges.

Connecting the comparators: Explain the wiring pattern for connecting the comparators in the bitonic sort network. Show students how to connect the inputs and outputs of comparators in each layer to form the complete sorting network.

Analyzing performance: Discuss the performance characteristics of the bitonic sort network, including its parallelism, latency, and hardware complexity. Compare it with other sorting algorithms and hardware sorting networks such as the odd-even merge sort or Batcher's merge-exchange network.

By following these steps, students can learn the concepts and design of a bitonic sort network, and create one using basic building blocks such as comparators. This will enable them to understand the advantages of parallel sorting in hardware and the intricacies of constructing efficient sorting networks.

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Introducing hardware CORDIC (Coordinate Rotation Digital Computer) to a digital logic student involves explaining the concepts and working through the process of creating a digital circuit to perform CORDIC algorithms using basic building blocks. Here's a step-by-step approach:

Introduce the concept: Explain that CORDIC is an iterative algorithm used to compute trigonometric, hyperbolic, logarithmic, and other mathematical functions efficiently using only simple arithmetic operations, such as shift, add, and subtract.

Explain the basic idea: Describe how the CORDIC algorithm works by breaking down the desired mathematical function into a series of elementary rotations or operations. For example, in trigonometric mode, the algorithm calculates the sine and cosine of an angle by performing a series of rotations.

Illustrate with an example: Start with the simplest case of using CORDIC to compute the sine and cosine of an angle in trigonometric mode. Introduce the rotation equations:
x' = x - yd2^(-i)
y' = y + xd2^(-i)
z' = z - d*atan(2^(-i))
where (x, y, z) are the input coordinates and angle, (x', y', z') are the updated coordinates and angle, d is the direction of rotation, and i is the iteration index.

Introduce the building blocks: Identify the basic components needed for the digital implementation of the CORDIC algorithm:
a. Registers: To store the input and output values (x, y, z) and intermediate results.
b. Shifters: To perform the right shift operation by the iteration index (i).
c. Adders/subtractors: To perform the addition and subtraction operations in the rotation equations.
d. Multiplexers: To select the direction of rotation (d) and control the data flow.
e. ROM or LUT (Look-Up Table): To store the precomputed arctangent values for each iteration.

Design the processing pipeline: Divide the CORDIC algorithm into sequential stages, including:
a. Initialization: Load the input values (x, y, z) into registers, and initialize the iteration index (i) and the direction of rotation (d).
b. Iteration: Perform the rotation equations for each iteration, updating the (x, y, z) values and incrementing the iteration index (i).
c. Termination: After a fixed number of iterations, store the final (x, y) values as the sine and cosine of the input angle.

Implement the stages: Design and implement digital circuits for each stage using the basic building blocks, and connect the stages to form a complete CORDIC processing pipeline.

Parameterize the design: Make the design flexible by allowing the user to specify the number of iterations, the input data width, and the output data width. This enables the user to balance the trade-off between accuracy and resource utilization.

Discuss other modes and functions: After covering the trigonometric mode, introduce other CORDIC modes, such as linear and hyperbolic, and discuss how the algorithm can be adapted to compute different mathematical functions, such as square roots, logarithms, and exponentials.

By following these steps, students can learn the concepts and design of a hardware CORDIC implementation and create a digital circuit to perform CORDIC algorithms using basic building blocks. This will enable them to understand the advantages of efficient hardware-based mathematical function computation in various applications.

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Introducing Hough Transforms to a digital logic student involves explaining the concepts and working through the process of creating a digital circuit to perform the Hough Transform using basic building blocks. Here's a step-by-step approach:

Introduce the concept: Explain that the Hough Transform is a feature extraction technique used in image processing and computer vision to detect simple shapes, such as lines, circles, or other parametric forms, in binary images.

Explain the basic idea: Describe how the Hough Transform works by mapping image points (edge pixels) to a parameter space representing the shape's parameters, then detecting the shape by identifying peaks in the parameter space. For example, when detecting lines, each point in the image space corresponds to a sinusoidal curve in the Hough (parameter) space.

Line detection example: Start with the simplest case of detecting straight lines in a binary image using the Hough Transform. Introduce the line equation in polar coordinates (ρ = xcos(θ) + ysin(θ)), where (ρ, θ) are the parameters of a line and (x, y) are the image points.

Introduce the accumulator array: Explain that the Hough Transform uses an accumulator array to represent the parameter space. The accumulator array is a 2D matrix where each cell (ρ, θ) accumulates votes from edge pixels that could belong to a line with parameters (ρ, θ).

Basic building blocks: Identify the basic components needed for the digital implementation of the Hough Transform:
a. Memory: To store the input binary image and the accumulator array.
b. Arithmetic and logic units (ALUs): To compute the parameter space coordinates (ρ, θ) for each edge pixel.
c. Counter and accumulator circuits: To increment the accumulator array values.
d. Peak detection logic: To identify local maxima in the accumulator array.

Design the processing pipeline: Divide the Hough Transform process into sequential stages, including:
a. Image preprocessing: Apply an edge detection algorithm to the input image, such as the Canny edge detector or the Sobel operator.
b. Parameter space computation: For each edge pixel (x, y), calculate the parameter space coordinates (ρ, θ) using the line equation in polar coordinates.
c. Voting and accumulation: Increment the accumulator array values corresponding to the calculated (ρ, θ) coordinates.
d. Thresholding and peak detection: Identify the peaks in the accumulator array above a certain threshold, which represent the detected lines.

Implement the stages: Design and implement digital circuits for each stage using the basic building blocks, and connect the stages to form a complete Hough Transform pipeline.

Optimize for performance and resources: Discuss potential optimizations, such as parallel processing, pipelining, and resource sharing, to improve the performance and resource utilization of the digital Hough Transform implementation.

By following these steps, students can learn the concepts and design of a digital Hough Transform, and create a digital circuit to perform the Hough Transform using basic building blocks. This will enable them to understand the advantages of hardware-based feature extraction techniques in image processing and computer vision applications.

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[deep oracle]

what about a series to build a minimal two memory operands ISA implementation ? Would this require some kind of microcoding ?

[deep oracle]

what about implementing https://forwardcom.info

[tribal tinsel]

two connected levels:

1. generate/draw multiple mazes using the same algorithm (e.g randomised depth-first-search + PRNG) and different starting seed each test (expected output can be X Y coordinates of path tiles in the maze in correct order and position)
2. take the code from lvl 1 and the same seeds, but now have robotron-like agent solve that maze (so, input is still only the seed, nothing else, but now you are supposed to output instructions to the robot to allow it to reach the exit within the maze with that seed)

[devout bloom]

relative to CAMs i feel like its a mistake to never mention that it stands for "content addressable memory"

because that name is extremly on the nose lol

[shrewd fractal]

It is, literally the first message

[devout bloom]

wow i really cannot read

[shrewd fractal]

Really cool suggestion mentioned by @desert dagger #1088864445037547651 message :

A lot of fixed components (which is hopefully possible with the some iteration of the custom level system) And you have to figure out and fix how it works

For example, a small serial decoder/encoder system, or a slightly more complicated multi-pin serial bus interface

Or even a full CPU architecture with a few small missing pieces, and you only know what the configured program is supposed to do, but nothing about how the machine code is actually designed

[deep oracle]

-TMR (Triple Modular Redundancy)
In a TMR protection scheme, three identical copies of a system or component, called "modules," operate simultaneously and independently. Each module receives the same input and produces an output. A voting mechanism, typically a majority voter, then compares the outputs of the three modules and selects the output that occurs at least twice (i.e., the majority).

• a level could implement a TMR protected ALU, a TMR protected register, etc. and demonstrates the error protection.

TMR technology is widely used in various application domains where high reliability, fault tolerance, and system resilience are critical.

[deep oracle]

Digital logic design concepts series : Karnaugh maps, Mux used for logic.. Maybe a time limited KM challenge for practice? May contains bibliography / reference links too

[sand notch]

Space Shuttle flight computer comes to mind

[deep oracle]

These days I looked at the projects on opencores.org website. I wonder if https://en.wikipedia.org/wiki/Wishbone_(computer_bus) would be of interest for custom TC levels. This seems to be potentially useful to make a bridge between TC designs and existing open hardware out there.

[deep oracle]

I see at least two different types of challenge in this message : black box reverse engineering and white box system debugging and / or completion which are two types of mission that could happen in the real world.

Black box reverse engineering seems potentially the hardest kind.

[deep oracle]

I am low in new realistic project ideas so today I will add an unrealistic one, it's a brainstorming thread anyway. https://www.retroreversing.com/n64rdp

Maybe more realistic and more instructive in terms of retro engineering https://en.m.wikipedia.org/wiki/Xerox_Alto which did not used an integrated circuit as CPU

It seems the schematic is available in the same way that we have the schematic for the first arcade game

[deep oracle]

Inspiration for a small compiler in ASM for an intermediate architecture: https://xorvoid.com/sectorc.html

[devout bloom]

This is so, so, so cursed lol

When I do compiler custom levels I think it will be scheme => etca and we'll actually start with an interpreter, then write the compiler in scheme and compile itself by interpreting it

I'm just not sure what to do about the compiler (or interpreter) input/output. Input from a (host machine) file is easy, but output to a (host machine) file not so much. Having a filesystem on an HDD inside the game might be a way to dodge that issue but then running the compiled code is hard because we have to either know where it will be loaded (it's in an HDD, so can't be run directly) or include information about how to load it in the object file in which case we also have to write a loader. Lots to think about.

[noble zinc]

Depending on what exactly you want supported, you could implement a basic FAT driver in a provided kernel so that it's natively mountable in linux or WSL. If you want native windows disk management support, you could also use a VHD file which is super simple for the fixed format since it's just a footer at the end of the file. If you do it as a VHD though, you might need to then add support for MBR partitioning so that windows can properly mount the file system and then on linux it would need to be setup as a loop device first.

[devout bloom]

Probably easier to write any FS in C and just extract data from a virtual hard drive using the C code

I remember looking at fat and deciding to try VSFS instead

[devout bloom]

And I made some progress on implementing VSFS but didn't have much time last semester, we'll see how this semester is

I was starting with a variation with no indirect blocks but the file size limit with no indirect blocks could be a problem so

There's probably some custom levels in there too but my main concern is that even though this seems preferable because it ends up with a self-contained TC thing, it doesn't make self-contained levels

So I'm more inclined to try having it read from a file (or keyboard, perhaps with a constant in the architecture that can be changed to switch modes?) and write its output to a ROM connected to the console. This way you see output while it runs but you also get the output as a file on the host machine

But then the ROM won't clear between runs so...

[noble zinc]

That is very true.

You could always output to a RAM connected to console and ROM. That way the duplicate data isn't displayed and you can do arbitrary formatting for the display

[devout bloom]

The real problem is that after a run is finished (e.g. compiling) in the file on the host machine you don't know where it actually ends

Anyway anyone interested in working with me on such levels (which would be very helpful - compilers are hard) is welcome to help. I have experience building compilers so I will probably do it regardless but I'm happy to organize a project with more people

Can start-ish even before custom levels release

[deep oracle]

Software is a form of art, and as such, it encompasses many styles. I realize that this particular sectorC may not appeal to everyone's tastes. However, an important style that I believe should be represented in the TC community is that of Niklaus Wirth, which is quite minimalistic, especially in his latest programming language. By the way, it is with sadness that I share the news of Prof. Wirth's recent passing.

[devout bloom]

What I was calling cursed specifically was the "atoi as a lexer"

Obviously by not handling collisions theyve created a language where random, seemingly unrelated variable names might be interpreted the same, or even worse as keywords lol

Making things to go in one sector is a very interesting challenge