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#VHDL/Verilog
snow oxideBOT
quaint schooner
I need help modifying the code (that I will send in file attahcments below). So that it gives me the correct CAD simulation output required (which should be 4,9).
We also have to follow these instructions.
To be done before coming to the lab (CAD simulation). Use Figure 4.24 (page 271) as a reference to implement load and store instructions. You only have to modify the top-level file and port map the components needed to implement the load and store instructions. You can use the register file component to make a small data memory. The MemWrite signal will be connected to where RegWrite is connected in the register file. The memory address, which is the result computed by the ALU should be connected to both the read address port and the write address port. You can ignore the MemRead signal. The MemRead signal will be used only when you have a real DRAM memory. You can modify the register file component to remove the second read port, or just connect place holder signals to the second read port.
Note that this memory is word-addressed as opposed to byte addressed. Therefore, array indices should not be multiplied by 4. Encode and simulate the following program. Initialize registers and data memory with the following values: r1=0; DMem[0]=5; DMem[1]=4.
lw r2, 0(r1)
lw r3, 1(r1)
add r2, r2, r3
sw r2, 0(r1)
