Its slightly more complicated than that. If a device needs 4x4.0 lanes it won't get the same performance at 2x5.0. Current gen nand won't likely be able to reach the maxed out 5.0x4 speeds until there are controllers with more channels.
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old moon
old moon
Also routing is much more difficult as the Pcie gens increase. 1-3 could be through hole design, 4.0 could be smt or lower loss through hole, while 5.0 requires smt design.