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I have tried the following so far:
F D E M W
I am not sure whether or not this is correct since I need to take Pipe hardware (inlc. forwarding and pipeline control logic) into account of the program
y86-64 is kinda madeup CS instructions so Ive been reading about what this should be
What you have is the optimal case
You've assumed no dependencies
If you have data dependencies you may have to stall for a cycle or so, so that you can wait for the data to be available
forwarding helps with this but it doesn't fully eliminate it
Hmmm.. Could you help? I am really lost where to start
not really ... I don't know what exact information you've been given
or what spec you're following
there will be a spec
I suggest asking someone in your course to help if you're stuck
The only information Ive been given is this:
The program runs on Y86-64:
and that I need to indicate, for each of the following clock cycles during program execution, which program instruction is in which stage of the
pipeline (i.e. in which of the F, D, E, M, W pipeline registers). In each field, indicate the instruction number of the instruction
there, or blank for pipeline bubble.
Assume D = 1, S = 3, and that the program is running on PIPE hardware (incl. forwarding- and pipeline-control-logic).
The stages for the first four cycles have prefilled
well thats not true
Y86-64
they clearly will have mentioned this before
and likely PIPE hardware
whatever that is
I wish more was stated in the document, but thats all there is really
I can also assume that the program is running on SEQ hardware