plain idol
i have built a logic filter to create a MaM however the wires retain a value once they have been given a value. for example the "OR" logic will continually put out a value of 1 even if there is no reason for it to be doing so. I have attached a picture of the layout i have. Any help would be great.
viscid juniper
I'm not sure but in your picture you have a retro feed loop from your fourth OR gate to your first. If I understand your wire setting, if you have one of your "EQUAL" gate that is set to True, all your OR gates are True. Since you have a retro feeding loop, even if you came back to all False for your "EQUAL" gate, your signal in your OR gates will always stay True
graceful spruce
flip flops are sus, wires are a bit too unstable for that rn